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Searched refs:rptr_offset (Results 1 – 11 of 11) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dmub/src/
Ddmub_dcn31.c277 void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) in dmub_dcn31_set_outbox1_rptr() argument
283 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); in dmub_dcn31_set_outbox1_rptr()
401 void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) in dmub_dcn31_set_outbox0_rptr() argument
403 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); in dmub_dcn31_set_outbox0_rptr()
Ddmub_dcn20.c322 void dmub_dcn20_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) in dmub_dcn20_set_outbox1_rptr() argument
328 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); in dmub_dcn20_set_outbox1_rptr()
344 void dmub_dcn20_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) in dmub_dcn20_set_outbox0_rptr() argument
346 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); in dmub_dcn20_set_outbox0_rptr()
Ddmub_dcn32.c306 void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) in dmub_dcn32_set_outbox1_rptr() argument
312 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); in dmub_dcn32_set_outbox1_rptr()
410 void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) in dmub_dcn32_set_outbox0_rptr() argument
412 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); in dmub_dcn32_set_outbox0_rptr()
Ddmub_dcn35.c328 void dmub_dcn35_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) in dmub_dcn35_set_outbox1_rptr() argument
334 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); in dmub_dcn35_set_outbox1_rptr()
454 void dmub_dcn35_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) in dmub_dcn35_set_outbox0_rptr() argument
456 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); in dmub_dcn35_set_outbox0_rptr()
Ddmub_dcn401.c289 void dmub_dcn401_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) in dmub_dcn401_set_outbox1_rptr() argument
295 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); in dmub_dcn401_set_outbox1_rptr()
395 void dmub_dcn401_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) in dmub_dcn401_set_outbox0_rptr() argument
397 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); in dmub_dcn401_set_outbox0_rptr()
Ddmub_dcn20.h217 void dmub_dcn20_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
224 void dmub_dcn20_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
Ddmub_dcn31.h219 void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
250 void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
Ddmub_dcn32.h226 void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
253 void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
Ddmub_dcn35.h239 void dmub_dcn35_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
268 void dmub_dcn35_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
Ddmub_dcn401.h235 void dmub_dcn401_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
262 void dmub_dcn401_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
/linux-6.12.1/drivers/gpu/drm/amd/display/dmub/
Ddmub_srv.h409 void (*set_outbox1_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset);
416 void (*set_outbox0_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset);