| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| D | dcn302_resource.c | 711 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create()
746 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create()
1007 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn302_resource_destruct()
1037 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn302_resource_destruct()
1050 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn302_resource_destruct()
1055 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn302_resource_destruct()
1062 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn302_resource_destruct()
1086 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn302_resource_destruct()
1209 pool->res_cap = &res_cap_dcn302; in dcn302_resource_construct()
1217 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| D | dcn303_resource.c | 673 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create()
708 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create()
952 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn303_resource_destruct()
982 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn303_resource_destruct()
995 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn303_resource_destruct()
1000 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn303_resource_destruct()
1007 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn303_resource_destruct()
1031 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn303_resource_destruct()
1151 pool->res_cap = &res_cap_dcn303; in dcn303_resource_construct()
1159 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| D | dcn301_resource.c | 1056 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn301_destruct()
1086 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn301_destruct()
1099 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn301_destruct()
1104 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct()
1111 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn301_destruct()
1134 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn301_destruct()
1150 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct()
1179 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_dwbc_create()
1204 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_mmhubbub_create()
1303 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; in init_soc_bounding_box()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| D | dcn316_resource.c | 1112 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1382 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn316_resource_destruct()
1412 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn316_resource_destruct()
1425 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn316_resource_destruct()
1430 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_destruct()
1437 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn316_resource_destruct()
1460 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn316_resource_destruct()
1476 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_destruct()
1510 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1535 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| D | dcn314_resource.c | 1176 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1443 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn314_resource_destruct()
1472 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn314_resource_destruct()
1485 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn314_resource_destruct()
1490 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_destruct()
1497 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn314_resource_destruct()
1520 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn314_resource_destruct()
1536 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_destruct()
1573 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1598 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| D | dcn351_resource.c | 1105 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1435 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn351_resource_destruct()
1465 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn351_resource_destruct()
1478 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn351_resource_destruct()
1483 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn351_resource_destruct()
1490 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn351_resource_destruct()
1513 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn351_resource_destruct()
1529 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn351_resource_destruct()
1582 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1621 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| D | dcn315_resource.c | 1118 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1386 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn315_resource_destruct()
1416 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn315_resource_destruct()
1429 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn315_resource_destruct()
1434 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_destruct()
1441 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn315_resource_destruct()
1464 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn315_resource_destruct()
1480 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_destruct()
1517 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1542 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| D | dcn31_resource.c | 1120 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1386 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn31_resource_destruct()
1416 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn31_resource_destruct()
1429 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn31_resource_destruct()
1434 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct()
1441 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn31_resource_destruct()
1464 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn31_resource_destruct()
1480 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct()
1517 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1542 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| D | dcn35_resource.c | 1125 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1455 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn35_resource_destruct()
1485 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn35_resource_destruct()
1498 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn35_resource_destruct()
1503 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn35_resource_destruct()
1510 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn35_resource_destruct()
1533 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn35_resource_destruct()
1549 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn35_resource_destruct()
1602 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1641 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| D | dcn30_resource.c | 1085 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn30_resource_destruct()
1115 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn30_resource_destruct()
1128 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn30_resource_destruct()
1133 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn30_resource_destruct()
1140 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn30_resource_destruct()
1163 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn30_resource_destruct()
1219 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create()
1244 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create()
1444 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_acquire_post_bldn_3dlut()
1474 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_release_post_bldn_3dlut()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_resource.c | 372 static const struct resource_caps res_cap = { variable
822 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_resource_destruct()
952 pool->base.res_cap = &res_cap; in dce60_construct()
960 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
961 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce60_construct()
1073 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_construct()
1147 pool->base.res_cap = &res_cap_61; in dce61_construct()
1271 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce61_construct()
1345 pool->base.res_cap = &res_cap_64; in dce64_construct()
1465 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce64_construct()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce80/ |
| D | dce80_resource.c | 374 static const struct resource_caps res_cap = { variable
828 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_resource_destruct()
958 pool->base.res_cap = &res_cap; in dce80_construct()
966 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
967 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce80_construct()
1086 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_construct()
1160 pool->base.res_cap = &res_cap_81; in dce81_construct()
1286 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce81_construct()
1360 pool->base.res_cap = &res_cap_83; in dce83_construct()
1483 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce83_construct()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| D | dcn321_resource.c | 1373 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn321_resource_destruct()
1402 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn321_resource_destruct()
1415 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn321_resource_destruct()
1420 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_destruct()
1427 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn321_resource_destruct()
1450 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn321_resource_destruct()
1466 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_destruct()
1488 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_dwbc_create()
1517 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_mmhubbub_create()
1677 pool->base.res_cap = &res_cap_dcn321; in dcn321_resource_construct()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| D | dcn401_resource.c | 1371 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn401_resource_destruct()
1401 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn401_resource_destruct()
1414 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn401_resource_destruct()
1419 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn401_resource_destruct()
1426 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn401_resource_destruct()
1449 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn401_resource_destruct()
1465 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn401_resource_destruct()
1487 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn401_dwbc_create()
1518 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn401_mmhubbub_create()
1764 pool->base.res_cap = &res_cap_dcn4_01; in dcn401_resource_construct()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| D | dcn32_resource.c | 1390 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn32_resource_destruct()
1420 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn32_resource_destruct()
1433 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn32_resource_destruct()
1438 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_destruct()
1445 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn32_resource_destruct()
1468 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn32_resource_destruct()
1484 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_destruct()
1506 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_dwbc_create()
1535 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_mmhubbub_create()
1626 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn32_release_post_bldn_3dlut()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| D | dce100_resource.c | 374 static const struct resource_caps res_cap = { variable
781 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_destruct()
993 pool->base.res_cap = &res_cap; in dce100_resource_construct()
1068 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1069 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce100_resource_construct()
1125 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_construct()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_link_enc_cfg.c | 40 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in is_dig_link_enc_stream()
180 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
189 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
274 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in clear_enc_assignments()
551 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in link_enc_cfg_get_next_avail_link_enc()
718 for (j = 0; j < dc->res_pool->res_cap->num_dig_link_enc; j++) { in link_enc_cfg_validate()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| D | dcn20_resource.c | 1094 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn20_resource_destruct()
1124 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn20_resource_destruct()
1137 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn20_resource_destruct()
1142 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn20_resource_destruct()
1149 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn20_resource_destruct()
1338 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { in dcn20_acquire_dsc()
1352 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_acquire_dsc()
1366 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_release_dsc()
2267 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_dwbc_create()
2290 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_mmhubbub_create()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce120/ |
| D | dce120_resource.c | 497 static const struct resource_caps res_cap = { variable
625 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_destruct()
1067 pool->base.res_cap = &res_cap; in dce120_resource_construct()
1071 pool->base.pipe_count = res_cap.num_timing_generator; in dce120_resource_construct()
1072 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce120_resource_construct()
1217 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_construct()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| D | dcn201_resource.c | 950 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_destruct()
955 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_destruct()
1096 pool->base.res_cap = &res_cap_dnc201; in dcn201_resource_construct()
1194 dcn201_ip.max_num_otg = pool->base.res_cap->num_timing_generator; in dcn201_resource_construct()
1229 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_construct()
1238 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn201_resource_construct()
1254 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_construct()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| D | dcn21_resource.c | 665 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_destruct()
694 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_destruct()
707 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn21_resource_destruct()
712 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn21_resource_destruct()
719 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn21_resource_destruct()
1397 pool->base.res_cap = &res_cap_rn; in dcn21_resource_construct()
1407 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()
1620 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_construct()
1656 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_construct()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| D | dcn10_resource.c | 488 static const struct resource_caps res_cap = { variable
956 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_destruct()
1330 pool->base.res_cap = &rv2_res_cap; in dcn10_resource_construct()
1332 pool->base.res_cap = &res_cap; in dcn10_resource_construct()
1346 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
1614 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_construct()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce112/ |
| D | dce112_resource.c | 802 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_destruct()
1233 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); in dce112_resource_construct()
1240 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1241 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1375 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_construct()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| D | dcn201_hwseq.c | 186 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn201_init_blank()
297 for (i = 0; i < res_pool->res_cap->num_opp; i++) { in dcn201_init_hw()
330 for (i = 0; i < res_pool->res_cap->num_dwb; i++) in dcn201_init_hw()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| D | dce110_resource.c | 837 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_destruct()
1361 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); in dce110_resource_construct()
1368 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1370 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1486 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_construct()
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