| /linux-6.12.1/drivers/gpu/drm/amd/display/dmub/src/ |
| D | dmub_reg.h | 37 #define REG_OFFSET(reg_name) (BASE(mm##reg_name##_BASE_IDX) + mm##reg_name) argument
39 #define FD_SHIFT(reg_name, field) reg_name##__##field##__SHIFT argument
41 #define FD_MASK(reg_name, field) reg_name##__##field##_MASK argument
47 #define FN(reg_name, field) FD(reg_name##__##field) argument
58 #define REG_SET_N(reg_name, n, initial_val, ...) \ argument
59 dmub_reg_set(CTX, REG(reg_name), initial_val, n, __VA_ARGS__)
61 #define REG_SET(reg_name, initial_val, field, val) \ argument
62 REG_SET_N(reg_name, 1, initial_val, \
63 FN(reg_name, field), val)
85 #define REG_UPDATE_N(reg_name, n, ...)\ argument
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/inc/ |
| D | reg_helper.h | 39 #define REG_READ(reg_name) \ argument
40 dm_read_reg(CTX, REG(reg_name))
42 #define REG_WRITE(reg_name, value) \ argument
43 dm_write_reg(CTX, REG(reg_name), value)
54 #define REG_SET_N(reg_name, n, initial_val, ...) \ argument
56 REG(reg_name), \
60 #define FN(reg_name, field) \ argument
61 FD(reg_name##__##field)
63 #define REG_SET(reg_name, initial_val, field, val) \ argument
64 REG_SET_N(reg_name, 1, initial_val, \
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| /linux-6.12.1/tools/perf/util/ |
| D | perf_regs.c | 35 const char *reg_name = NULL; in perf_reg_name() local
38 reg_name = __perf_reg_name_csky(id); in perf_reg_name()
40 reg_name = __perf_reg_name_loongarch(id); in perf_reg_name()
42 reg_name = __perf_reg_name_mips(id); in perf_reg_name()
44 reg_name = __perf_reg_name_powerpc(id); in perf_reg_name()
46 reg_name = __perf_reg_name_riscv(id); in perf_reg_name()
48 reg_name = __perf_reg_name_s390(id); in perf_reg_name()
50 reg_name = __perf_reg_name_x86(id); in perf_reg_name()
52 reg_name = __perf_reg_name_arm(id); in perf_reg_name()
54 reg_name = __perf_reg_name_arm64(id); in perf_reg_name()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/gpio/dcn21/ |
| D | hw_factory_dcn21.c | 57 #define REG(reg_name)\ argument
58 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
60 #define SF_HPD(reg_name, field_name, post_fix)\ argument
61 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
63 #define REGI(reg_name, block, id)\ argument
64 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
65 mm ## block ## id ## _ ## reg_name
67 #define SF(reg_name, field_name, post_fix)\ argument
68 .field_name = reg_name ## __ ## field_name ## post_fix
99 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/gpio/dce120/ |
| D | hw_factory_dce120.c | 46 #define SF_HPD(reg_name, field_name, post_fix)\ argument
47 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
50 #define SF_HPD(reg_name, field_name, post_fix)\ argument
51 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
60 #define REG(reg_name)\ argument
61 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
63 #define REGI(reg_name, block, id)\ argument
64 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
65 mm ## block ## id ## _ ## reg_name
96 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/gpio/dcn30/ |
| D | hw_factory_dcn30.c | 66 #define REG(reg_name)\ argument
67 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
69 #define SF_HPD(reg_name, field_name, post_fix)\ argument
70 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
72 #define REGI(reg_name, block, id)\ argument
73 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
74 mm ## block ## id ## _ ## reg_name
76 #define SF(reg_name, field_name, post_fix)\ argument
77 .field_name = reg_name ## __ ## field_name ## post_fix
109 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/gpio/dcn32/ |
| D | hw_factory_dcn32.c | 59 #define REG(reg_name)\ argument
60 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
62 #define SF_HPD(reg_name, field_name, post_fix)\ argument
63 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
65 #define REGI(reg_name, block, id)\ argument
66 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
67 reg ## block ## id ## _ ## reg_name
69 #define SF(reg_name, field_name, post_fix)\ argument
70 .field_name = reg_name ## __ ## field_name ## post_fix
101 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/gpio/dcn401/ |
| D | hw_factory_dcn401.c | 39 #define REG(reg_name)\ argument
40 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
42 #define SF_HPD(reg_name, field_name, post_fix)\ argument
43 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
45 #define REGI(reg_name, block, id)\ argument
46 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
47 reg ## block ## id ## _ ## reg_name
49 #define SF(reg_name, field_name, post_fix)\ argument
50 .field_name = reg_name ## __ ## field_name ## post_fix
81 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/gpio/dcn20/ |
| D | hw_factory_dcn20.c | 59 #define REG(reg_name)\ argument
60 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
62 #define SF_HPD(reg_name, field_name, post_fix)\ argument
63 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
65 #define REGI(reg_name, block, id)\ argument
66 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
67 mm ## block ## id ## _ ## reg_name
69 #define SF(reg_name, field_name, post_fix)\ argument
70 .field_name = reg_name ## __ ## field_name ## post_fix
102 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/gpio/dcn315/ |
| D | hw_factory_dcn315.c | 63 #define REG(reg_name)\ argument
64 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
66 #define SF_HPD(reg_name, field_name, post_fix)\ argument
67 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
69 #define REGI(reg_name, block, id)\ argument
70 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
71 reg ## block ## id ## _ ## reg_name
73 #define SF(reg_name, field_name, post_fix)\ argument
74 .field_name = reg_name ## __ ## field_name ## post_fix
105 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/ |
| D | dm_services.h | 96 #define get_reg_field_value(reg_value, reg_name, reg_field)\ argument
99 reg_name ## __ ## reg_field ## _MASK,\
100 reg_name ## __ ## reg_field ## __SHIFT)
112 #define set_reg_field_value(reg_value, value, reg_name, reg_field)\ argument
116 reg_name ## __ ## reg_field ## _MASK,\
117 reg_name ## __ ## reg_field ## __SHIFT)
157 #define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\ argument
158 …generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name +…
161 #define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\ argument
162 …generic_reg_set_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + ins…
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/gpio/dcn10/ |
| D | hw_factory_dcn10.c | 47 #define SF_HPD(reg_name, field_name, post_fix)\ argument
48 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
57 #define REG(reg_name)\ argument
58 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
60 #define REGI(reg_name, block, id)\ argument
61 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
62 mm ## block ## id ## _ ## reg_name
92 #define SF_DDC(reg_name, field_name, post_fix)\ argument
93 .field_name = reg_name ## __ ## field_name ## post_fix
128 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_panel_cntl.h | 32 #define DCE_PANEL_CNTL_SR(reg_name, block)\ argument
33 .reg_name = mm ## block ## _ ## reg_name
45 #define DCN_PANEL_CNTL_SR(reg_name, block)\ argument
46 .reg_name = BASE(mm ## block ## _ ## reg_name ## _BASE_IDX) + \
47 mm ## block ## _ ## reg_name
59 #define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\ argument
60 .field_name = reg_name ## __ ## field_name ## post_fix
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| D | dcn321_resource.c | 117 #define SR(reg_name)\ argument
118 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
119 reg ## reg_name
120 #define SR_ARR(reg_name, id)\ argument
121 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
122 reg ## reg_name
123 #define SR_ARR_INIT(reg_name, id, value)\ argument
124 REG_STRUCT[id].reg_name = value
126 #define SRI(reg_name, block, id)\ argument
127 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| D | dcn401_resource.c | 102 #define SR(reg_name)\ argument
103 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
104 reg ## reg_name
105 #define SR_ARR(reg_name, id)\ argument
106 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
107 reg ## reg_name
108 #define SR_ARR_INIT(reg_name, id, value)\ argument
109 REG_STRUCT[id].reg_name = value
111 #define SRI(reg_name, block, id)\ argument
112 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/gpio/dce110/ |
| D | hw_factory_dce110.c | 42 #define SF_HPD(reg_name, field_name, post_fix)\ argument
43 .field_name = reg_name ## __ ## field_name ## post_fix
45 #define REG(reg_name)\ argument
46 mm ## reg_name
48 #define REGI(reg_name, block, id)\ argument
49 mm ## block ## id ## _ ## reg_name
79 #define SF_DDC(reg_name, field_name, post_fix)\ argument
80 .field_name = reg_name ## __ ## field_name ## post_fix
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| D | dcn351_resource.c | 111 #define SR(reg_name)\ argument
112 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
113 reg ## reg_name
115 #define SR_ARR(reg_name, id) \ argument
116 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
118 #define SR_ARR_INIT(reg_name, id, value) \ argument
119 REG_STRUCT[id].reg_name = value
121 #define SRI(reg_name, block, id)\ argument
122 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123 reg ## block ## id ## _ ## reg_name
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| D | dcn35_resource.c | 131 #define SR(reg_name)\ argument
132 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
133 reg ## reg_name
135 #define SR_ARR(reg_name, id) \ argument
136 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
138 #define SR_ARR_INIT(reg_name, id, value) \ argument
139 REG_STRUCT[id].reg_name = value
141 #define SRI(reg_name, block, id)\ argument
142 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
143 reg ## block ## id ## _ ## reg_name
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| D | dcn301_resource.c | 116 #define SR(reg_name)\ argument
117 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
118 mm ## reg_name
120 #define SRI(reg_name, block, id)\ argument
121 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
122 mm ## block ## id ## _ ## reg_name
124 #define SRI2(reg_name, block, id)\ argument
125 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
126 mm ## reg_name
128 #define SRIR(var_name, reg_name, block, id)\ argument
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| /linux-6.12.1/tools/testing/selftests/kvm/aarch64/ |
| D | debug-exceptions.c | 40 #define GEN_DEBUG_WRITE_REG(reg_name) \ argument
41 static void write_##reg_name(int num, uint64_t val) \
45 write_sysreg(val, reg_name##0_el1); \
48 write_sysreg(val, reg_name##1_el1); \
51 write_sysreg(val, reg_name##2_el1); \
54 write_sysreg(val, reg_name##3_el1); \
57 write_sysreg(val, reg_name##4_el1); \
60 write_sysreg(val, reg_name##5_el1); \
63 write_sysreg(val, reg_name##6_el1); \
66 write_sysreg(val, reg_name##7_el1); \
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| /linux-6.12.1/tools/lib/bpf/ |
| D | usdt.c | 1237 static int calc_pt_regs_off(const char *reg_name) in calc_pt_regs_off() argument
1273 if (strcmp(reg_name, reg_map[i].names[j]) == 0) in calc_pt_regs_off()
1278 pr_warn("usdt: unrecognized register '%s'\n", reg_name); in calc_pt_regs_off()
1284 char reg_name[16]; in parse_usdt_arg() local
1288 if (sscanf(arg_str, " %d @ %ld ( %%%15[^)] ) %n", arg_sz, &off, reg_name, &len) == 3) { in parse_usdt_arg()
1292 reg_off = calc_pt_regs_off(reg_name); in parse_usdt_arg()
1296 } else if (sscanf(arg_str, " %d @ ( %%%15[^)] ) %n", arg_sz, reg_name, &len) == 2) { in parse_usdt_arg()
1300 reg_off = calc_pt_regs_off(reg_name); in parse_usdt_arg()
1304 } else if (sscanf(arg_str, " %d @ %%%15s %n", arg_sz, reg_name, &len) == 2) { in parse_usdt_arg()
1309 reg_off = calc_pt_regs_off(reg_name); in parse_usdt_arg()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_dwb.h | 34 #define SR(reg_name)\ argument
35 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
36 mm ## reg_name
38 #define SRI(reg_name, block, id)\ argument
39 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
40 mm ## block ## id ## _ ## reg_name
43 #define SRII(reg_name, block, id)\ argument
44 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
45 mm ## block ## id ## _ ## reg_name
47 #define SF(reg_name, field_name, post_fix)\ argument
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| D | dcn32_resource.c | 116 #define SR(reg_name)\ argument
117 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
118 reg ## reg_name
119 #define SR_ARR(reg_name, id) \ argument
120 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
122 #define SR_ARR_INIT(reg_name, id, value) \ argument
123 REG_STRUCT[id].reg_name = value
125 #define SRI(reg_name, block, id)\ argument
126 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
127 reg ## block ## id ## _ ## reg_name
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| D | dcn201_resource.c | 251 #define SR(reg_name)\ argument
252 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
253 mm ## reg_name
255 #define SRI(reg_name, block, id)\ argument
256 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
257 mm ## block ## id ## _ ## reg_name
259 #define SRIR(var_name, reg_name, block, id)\ argument
260 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
261 mm ## block ## id ## _ ## reg_name
263 #define SRII(reg_name, block, id)\ argument
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| D | dcn302_resource.c | 167 #define NBIO_SR(reg_name)\ argument
168 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
169 mm ## reg_name
176 #define SR(reg_name)\ argument
177 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
179 #define SF(reg_name, field_name, post_fix)\ argument
180 .field_name = reg_name ## __ ## field_name ## post_fix
182 #define SRI(reg_name, block, id)\ argument
183 ….reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_…
185 #define SRI2(reg_name, block, id)\ argument
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|