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Searched refs:reg_mask (Results 1 – 25 of 43) sorted by relevance

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/linux-6.12.1/drivers/clk/ux500/
Dclk-sysctrl.c27 u8 reg_mask[SYSCTRL_MAX_NUM_PARENTS]; member
40 ret = ab8500_sysctrl_write(clk->reg_sel[0], clk->reg_mask[0], in clk_sysctrl_prepare()
53 if (ab8500_sysctrl_clear(clk->reg_sel[0], clk->reg_mask[0])) in clk_sysctrl_unprepare()
73 clk->reg_mask[old_index]); in clk_sysctrl_set_parent()
80 clk->reg_mask[index], in clk_sysctrl_set_parent()
85 clk->reg_mask[old_index], in clk_sysctrl_set_parent()
123 u8 *reg_mask, in clk_reg_sysctrl() argument
150 clk->reg_mask[0] = reg_mask[0]; in clk_reg_sysctrl()
156 clk->reg_mask[i] = reg_mask[i]; in clk_reg_sysctrl()
182 u8 reg_mask, in clk_reg_sysctrl_gate() argument
[all …]
Dclk.h72 u8 reg_mask,
81 u8 reg_mask,
92 u8 *reg_mask,
/linux-6.12.1/drivers/power/reset/
Datc260x-poweroff.c25 uint reg_mask, reg_val; in atc2603c_do_poweroff() local
44 reg_mask = ATC2603C_PMU_SYS_CTL3_EN_S2 | ATC2603C_PMU_SYS_CTL3_EN_S3; in atc2603c_do_poweroff()
46 ret = regmap_update_bits(pwrc->regmap, ATC2603C_PMU_SYS_CTL3, reg_mask, in atc2603c_do_poweroff()
54 reg_mask = restart ? ATC2603C_PMU_SYS_CTL0_RESTART_EN in atc2603c_do_poweroff()
60 reg_mask, reg_val); in atc2603c_do_poweroff()
76 uint reg_mask, reg_val; in atc2609a_do_poweroff() local
95 reg_mask = ATC2609A_PMU_SYS_CTL3_EN_S2 | ATC2609A_PMU_SYS_CTL3_EN_S3; in atc2609a_do_poweroff()
97 ret = regmap_update_bits(pwrc->regmap, ATC2609A_PMU_SYS_CTL3, reg_mask, in atc2609a_do_poweroff()
105 reg_mask = restart ? ATC2609A_PMU_SYS_CTL0_RESTART_EN in atc2609a_do_poweroff()
111 reg_mask, reg_val); in atc2609a_do_poweroff()
/linux-6.12.1/drivers/irqchip/
Dirq-mmp.c43 void __iomem *reg_mask; member
86 r = readl_relaxed(data->reg_mask) | (1 << hwirq); in icu_mask_ack_irq()
87 writel_relaxed(r, data->reg_mask); in icu_mask_ack_irq()
115 r = readl_relaxed(data->reg_mask) | (1 << hwirq); in icu_mask_irq()
116 writel_relaxed(r, data->reg_mask); in icu_mask_irq()
134 r = readl_relaxed(data->reg_mask) & ~(1 << hwirq); in icu_unmask_irq()
135 writel_relaxed(r, data->reg_mask); in icu_unmask_irq()
169 mask = readl_relaxed(data->reg_mask); in icu_mux_irq_demux()
388 icu_data[i].reg_mask = mmp_icu_base + reg[2]; in mmp2_mux_of_init()
/linux-6.12.1/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_init.h569 } reg_mask; /* Register mask (all valid bits) */ member
695 return bnx2x_blocks_parity_data[idx].reg_mask.e1; in bnx2x_parity_reg_mask()
697 return bnx2x_blocks_parity_data[idx].reg_mask.e1h; in bnx2x_parity_reg_mask()
699 return bnx2x_blocks_parity_data[idx].reg_mask.e2; in bnx2x_parity_reg_mask()
701 return bnx2x_blocks_parity_data[idx].reg_mask.e3; in bnx2x_parity_reg_mask()
741 u32 reg_mask = bnx2x_parity_reg_mask(bp, i); in bnx2x_clear_blocks_parity() local
743 if (reg_mask) { in bnx2x_clear_blocks_parity()
746 if (reg_val & reg_mask) in bnx2x_clear_blocks_parity()
750 reg_val & reg_mask); in bnx2x_clear_blocks_parity()
774 u32 reg_mask = bnx2x_parity_reg_mask(bp, i); in bnx2x_enable_blocks_parity() local
[all …]
/linux-6.12.1/drivers/gpio/
Dgpio-htc-egpio.c38 int reg_mask; member
192 reg, (egpio->cached_values >> shift) & ei->reg_mask); in egpio_set()
199 egpio_writew((egpio->cached_values >> shift) & ei->reg_mask, ei, reg); in egpio_set()
245 if (!((egpio->is_out >> shift) & ei->reg_mask)) in egpio_write_cache()
249 (egpio->cached_values >> shift) & ei->reg_mask, in egpio_write_cache()
253 & ei->reg_mask, ei, reg); in egpio_write_cache()
301 ei->reg_mask = (1 << pdata->reg_width) - 1; in egpio_probe()
/linux-6.12.1/drivers/pci/controller/dwc/
Dpcie-al.c126 u8 reg_mask; member
225 unsigned int busnr_reg = busnr & target_bus_cfg->reg_mask; in al_pcie_conf_addr_map_bus()
233 target_bus_cfg->reg_mask); in al_pcie_conf_addr_map_bus()
274 target_bus_cfg->reg_mask = ~target_bus_cfg->ecam_mask; in al_pcie_config_prepare()
275 target_bus_cfg->reg_val = bus->start & target_bus_cfg->reg_mask; in al_pcie_config_prepare()
278 target_bus_cfg->reg_mask); in al_pcie_config_prepare()
/linux-6.12.1/drivers/gpu/drm/imagination/
Dpvr_device.h583 u32 reg_mask, u64 timeout_usec) in pvr_cr_poll_reg32() argument
588 (value & reg_mask) == reg_value, 0, timeout_usec); in pvr_cr_poll_reg32()
606 u64 reg_mask, u64 timeout_usec) in pvr_cr_poll_reg64() argument
611 (value & reg_mask) == reg_value, 0, timeout_usec); in pvr_cr_poll_reg64()
/linux-6.12.1/drivers/net/ethernet/stmicro/stmmac/
Dstmmac_mdio.c288 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; in stmmac_mdio_read_c22()
328 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; in stmmac_mdio_read_c45()
333 value &= ~priv->hw->mii.reg_mask; in stmmac_mdio_read_c45()
334 value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; in stmmac_mdio_read_c45()
387 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; in stmmac_mdio_write_c22()
428 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; in stmmac_mdio_write_c45()
435 value &= ~priv->hw->mii.reg_mask; in stmmac_mdio_write_c45()
436 value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; in stmmac_mdio_write_c45()
Dcommon.h581 unsigned int reg_mask; /* MII reg mask */ member
616 u32 reg_mask; member
Ddwmac100_core.c190 mac->mii.reg_mask = 0x000007C0; in dwmac100_setup()
Ddwxgmac2_core.c171 value &= ~dwxgmac2_route_possibilities[packet - 1].reg_mask; in dwxgmac2_rx_queue_routing()
173 dwxgmac2_route_possibilities[packet - 1].reg_mask; in dwxgmac2_rx_queue_routing()
1666 mac->mii.reg_mask = GENMASK(15, 0); in dwxgmac2_setup()
1708 mac->mii.reg_mask = GENMASK(15, 0); in dwxlgmac2_setup()
/linux-6.12.1/drivers/pinctrl/samsung/
Dpinctrl-exynos.c56 unsigned long reg_mask; in exynos_irq_mask() local
61 reg_mask = bank->pctl_offset + bank->eint_mask_offset; in exynos_irq_mask()
63 reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
73 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
75 writel(mask, bank->eint_base + reg_mask); in exynos_irq_mask()
110 unsigned long reg_mask; in exynos_irq_unmask() local
126 reg_mask = bank->pctl_offset + bank->eint_mask_offset; in exynos_irq_unmask()
128 reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_unmask()
138 mask = readl(bank->eint_base + reg_mask); in exynos_irq_unmask()
140 writel(mask, bank->eint_base + reg_mask); in exynos_irq_unmask()
/linux-6.12.1/drivers/memory/
Dstm32-fmc2-ebi.c231 u32 reg_mask; member
505 regmap_update_bits(ebi->regmap, reg, prop->reg_mask, in stm32_fmc2_ebi_set_bit_field()
506 setup ? prop->reg_mask : 0); in stm32_fmc2_ebi_set_bit_field()
934 .reg_mask = FMC2_BCR1_CCLKEN,
942 .reg_mask = FMC2_BCR_MUXEN,
955 .reg_mask = FMC2_BCR_WAITPOL,
962 .reg_mask = FMC2_BCR_WAITCFG,
970 .reg_mask = FMC2_BCR_WAITEN,
978 .reg_mask = FMC2_BCR_ASYNCWAIT,
1099 .reg_mask = FMC2_CFGR_CCLKEN,
[all …]
/linux-6.12.1/drivers/net/phy/
Dnxp-tja11xx.c291 u16 reg_mask, reg_val; in tja11xx_config_init() local
304 reg_mask = MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK | in tja11xx_config_init()
309 reg_mask |= MII_CFG1_INTERFACE_MODE_MASK; in tja11xx_config_init()
315 ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val); in tja11xx_config_init()
320 reg_mask = MII_CFG1_INTERFACE_MODE_MASK; in tja11xx_config_init()
326 ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val); in tja11xx_config_init()
/linux-6.12.1/drivers/pinctrl/ti/
Dpinctrl-ti-iodelay.c219 u32 reg_mask, reg_val, tmp_val; in ti_iodelay_pinconf_set() local
238 reg_mask = reg->signature_mask; in ti_iodelay_pinconf_set()
241 reg_mask |= reg->binary_data_coarse_mask; in ti_iodelay_pinconf_set()
250 reg_mask |= reg->binary_data_fine_mask; in ti_iodelay_pinconf_set()
265 reg_mask |= reg->lock_mask; in ti_iodelay_pinconf_set()
267 r = regmap_update_bits(iod->regmap, cfg->offset, reg_mask, reg_val); in ti_iodelay_pinconf_set()
/linux-6.12.1/drivers/pmdomain/qcom/
Dcpr.c463 u32 val, error_steps, reg_mask; in cpr_scale() local
499 reg_mask = RBCPR_CTL_UP_THRESHOLD_MASK; in cpr_scale()
500 reg_mask <<= RBCPR_CTL_UP_THRESHOLD_SHIFT; in cpr_scale()
501 val = reg_mask; in cpr_scale()
502 cpr_ctl_modify(drv, reg_mask, val); in cpr_scale()
536 reg_mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN; in cpr_scale()
539 cpr_ctl_modify(drv, reg_mask, val); in cpr_scale()
568 reg_mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN; in cpr_scale()
572 reg_mask = RBCPR_CTL_UP_THRESHOLD_MASK; in cpr_scale()
573 reg_mask <<= RBCPR_CTL_UP_THRESHOLD_SHIFT; in cpr_scale()
[all …]
/linux-6.12.1/include/sound/
Dpcm_oss.h72 unsigned int reg_mask; member
/linux-6.12.1/drivers/pinctrl/mvebu/
Dpinctrl-armada-37xx.c64 u32 reg_mask; member
118 .reg_mask = 0, \
128 .reg_mask = _mask, \
138 .reg_mask = _mask, \
148 .reg_mask = _mask, \
159 .reg_mask = _mask, \
350 unsigned int mask = grp->reg_mask; in armada_37xx_pmx_set_by_name()
/linux-6.12.1/drivers/media/i2c/
Dmt9m111.c142 #define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \ macro
225 unsigned int reg_mask; member
258 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK,
267 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK,
277 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK,
939 mt9m111->current_mode->reg_mask); in mt9m111_restore_state()
/linux-6.12.1/drivers/phy/broadcom/
Dphy-bcm-ns2-usbdrd.c78 static inline int pll_lock_stat(u32 usb_reg, int reg_mask, in pll_lock_stat() argument
84 val, (val & reg_mask), 1, in pll_lock_stat()
/linux-6.12.1/drivers/video/fbdev/via/
Dhw.c968 int reg_mask; in viafb_load_reg() local
977 reg_mask = 0; in viafb_load_reg()
986 reg_mask = reg_mask | (BIT0 << j); in viafb_load_reg()
993 viafb_write_reg_mask(cr_index, VIACR, data, reg_mask); in viafb_load_reg()
995 viafb_write_reg_mask(cr_index, VIASR, data, reg_mask); in viafb_load_reg()
/linux-6.12.1/drivers/tty/serial/8250/
D8250_aspeed_vuart.c383 u32 reg_offset, u32 reg_mask) in aspeed_vuart_auto_configure_sirq_polarity() argument
399 aspeed_vuart_set_sirq_polarity(vuart, (value & reg_mask) == 0); in aspeed_vuart_auto_configure_sirq_polarity()
/linux-6.12.1/drivers/pci/controller/plda/
Dpcie-microchip-host.c175 u32 reg_mask; member
323 return (reg & field.reg_mask) ? BIT(field.event_bit) : 0; in reg_to_event()
/linux-6.12.1/drivers/crypto/intel/qat/qat_common/
Dqat_hal.c1378 unsigned short reg_mask; in qat_hal_put_rel_wr_xfer() local
1396 reg_mask = (unsigned short)~0x1f; in qat_hal_put_rel_wr_xfer()
1398 reg_mask = (unsigned short)~0xf; in qat_hal_put_rel_wr_xfer()
1400 if (reg_num & reg_mask) in qat_hal_put_rel_wr_xfer()

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