| /linux-6.12.1/drivers/gpu/drm/xe/ |
| D | xe_rtp.h | 242 #define XE_RTP_ACTION_WR(reg_, val_, ...) \ argument
243 { .reg = XE_RTP_DROP_CAST(reg_), \
260 #define XE_RTP_ACTION_SET(reg_, val_, ...) \ argument
261 { .reg = XE_RTP_DROP_CAST(reg_), \
278 #define XE_RTP_ACTION_CLR(reg_, val_, ...) \ argument
279 { .reg = XE_RTP_DROP_CAST(reg_), \
295 #define XE_RTP_ACTION_FIELD_SET(reg_, mask_bits_, val_, ...) \ argument
296 { .reg = XE_RTP_DROP_CAST(reg_), \
300 #define XE_RTP_ACTION_FIELD_SET_NO_READ_MASK(reg_, mask_bits_, val_, ...) \ argument
301 { .reg = XE_RTP_DROP_CAST(reg_), \
[all …]
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| /linux-6.12.1/drivers/pinctrl/aspeed/ |
| D | pinctrl-aspeed.h | 37 #define ASPEED_SB_PINCONF(param_, pin0_, pin1_, reg_, bit_) { \ argument
40 .reg = reg_, \
44 #define ASPEED_PULL_DOWN_PINCONF(pin_, reg_, bit_) \ argument
45 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, pin_, pin_, reg_, bit_), \
46 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_)
48 #define ASPEED_PULL_UP_PINCONF(pin_, reg_, bit_) \ argument
49 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_UP, pin_, pin_, reg_, bit_), \
50 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_)
|
| /linux-6.12.1/drivers/net/ipa/ |
| D | reg.h | 36 static const struct reg reg_ ## __reg_id = { \
46 static const struct reg reg_ ## __name = { \
50 .fcount = ARRAY_SIZE(reg_ ## __name ## _fmask), \
51 .fmask = reg_ ## __name ## _fmask, \
|
| /linux-6.12.1/drivers/ufs/host/ |
| D | ufs-exynos.h | 255 writel(val, ufs->reg_##name + reg); \
260 return readl(ufs->reg_##name + reg); \
|
| /linux-6.12.1/drivers/iio/light/ |
| D | stk3310.c | 61 data->reg_##name = \
64 if (IS_ERR(data->reg_##name)) { \
66 return PTR_ERR(data->reg_##name); \
|
| /linux-6.12.1/arch/arm64/kernel/ |
| D | cpuinfo.c | 307 return sprintf(buf, "0x%016llx\n", info->reg_##_field); \
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| /linux-6.12.1/drivers/net/ethernet/mellanox/mlx4/ |
| D | en_ethtool.c | 629 #define MLX4_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \ argument
634 cfg = &ptys2ethtool_map[reg_]; \
|
| /linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/ |
| D | en_ethtool.c | 82 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \ argument
87 cfg = &ptys2##table##_ethtool_table[reg_]; \
|