1 /*
2  * Copyright 2023 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef _vpe_6_1_0_OFFSET_HEADER
24 #define _vpe_6_1_0_OFFSET_HEADER
25 
26 
27 
28 // addressBlock: vpe_vpedec
29 // base address: 0x46000
30 #define regVPEC_DEC_START                                                                               0x0000
31 #define regVPEC_DEC_START_BASE_IDX                                                                      0
32 #define regVPEC_UCODE_ADDR                                                                              0x0001
33 #define regVPEC_UCODE_ADDR_BASE_IDX                                                                     0
34 #define regVPEC_UCODE_DATA                                                                              0x0002
35 #define regVPEC_UCODE_DATA_BASE_IDX                                                                     0
36 #define regVPEC_F32_CNTL                                                                                0x0003
37 #define regVPEC_F32_CNTL_BASE_IDX                                                                       0
38 #define regVPEC_VPEP_CTRL                                                                               0x0010
39 #define regVPEC_VPEP_CTRL_BASE_IDX                                                                      0
40 #define regVPEC_CLK_CTRL                                                                                0x0011
41 #define regVPEC_CLK_CTRL_BASE_IDX                                                                       0
42 #define regVPEC_PG_CNTL                                                                                 0x0012
43 #define regVPEC_PG_CNTL_BASE_IDX                                                                        0
44 #define regVPEC_POWER_CNTL                                                                              0x0013
45 #define regVPEC_POWER_CNTL_BASE_IDX                                                                     0
46 #define regVPEC_CNTL                                                                                    0x0014
47 #define regVPEC_CNTL_BASE_IDX                                                                           0
48 #define regVPEC_CNTL1                                                                                   0x0015
49 #define regVPEC_CNTL1_BASE_IDX                                                                          0
50 #define regVPEC_CNTL2                                                                                   0x0016
51 #define regVPEC_CNTL2_BASE_IDX                                                                          0
52 #define regVPEC_GB_ADDR_CONFIG                                                                          0x0017
53 #define regVPEC_GB_ADDR_CONFIG_BASE_IDX                                                                 0
54 #define regVPEC_GB_ADDR_CONFIG_READ                                                                     0x0018
55 #define regVPEC_GB_ADDR_CONFIG_READ_BASE_IDX                                                            0
56 #define regVPEC_PROCESS_QUANTUM0                                                                        0x0019
57 #define regVPEC_PROCESS_QUANTUM0_BASE_IDX                                                               0
58 #define regVPEC_PROCESS_QUANTUM1                                                                        0x001a
59 #define regVPEC_PROCESS_QUANTUM1_BASE_IDX                                                               0
60 #define regVPEC_CONTEXT_SWITCH_THRESHOLD                                                                0x001b
61 #define regVPEC_CONTEXT_SWITCH_THRESHOLD_BASE_IDX                                                       0
62 #define regVPEC_GLOBAL_QUANTUM                                                                          0x001c
63 #define regVPEC_GLOBAL_QUANTUM_BASE_IDX                                                                 0
64 #define regVPEC_WATCHDOG_CNTL                                                                           0x001d
65 #define regVPEC_WATCHDOG_CNTL_BASE_IDX                                                                  0
66 #define regVPEC_ATOMIC_CNTL                                                                             0x001e
67 #define regVPEC_ATOMIC_CNTL_BASE_IDX                                                                    0
68 #define regVPEC_UCODE_VERSION                                                                           0x001f
69 #define regVPEC_UCODE_VERSION_BASE_IDX                                                                  0
70 #define regVPEC_MEMREQ_BURST_CNTL                                                                       0x0020
71 #define regVPEC_MEMREQ_BURST_CNTL_BASE_IDX                                                              0
72 #define regVPEC_TIMESTAMP_CNTL                                                                          0x0021
73 #define regVPEC_TIMESTAMP_CNTL_BASE_IDX                                                                 0
74 #define regVPEC_GLOBAL_TIMESTAMP_LO                                                                     0x0022
75 #define regVPEC_GLOBAL_TIMESTAMP_LO_BASE_IDX                                                            0
76 #define regVPEC_GLOBAL_TIMESTAMP_HI                                                                     0x0023
77 #define regVPEC_GLOBAL_TIMESTAMP_HI_BASE_IDX                                                            0
78 #define regVPEC_FREEZE                                                                                  0x0024
79 #define regVPEC_FREEZE_BASE_IDX                                                                         0
80 #define regVPEC_CE_CTRL                                                                                 0x0025
81 #define regVPEC_CE_CTRL_BASE_IDX                                                                        0
82 #define regVPEC_RELAX_ORDERING_LUT                                                                      0x0026
83 #define regVPEC_RELAX_ORDERING_LUT_BASE_IDX                                                             0
84 #define regVPEC_CREDIT_CNTL                                                                             0x0027
85 #define regVPEC_CREDIT_CNTL_BASE_IDX                                                                    0
86 #define regVPEC_SCRATCH_RAM_DATA                                                                        0x0028
87 #define regVPEC_SCRATCH_RAM_DATA_BASE_IDX                                                               0
88 #define regVPEC_SCRATCH_RAM_ADDR                                                                        0x0029
89 #define regVPEC_SCRATCH_RAM_ADDR_BASE_IDX                                                               0
90 #define regVPEC_QUEUE_RESET_REQ                                                                         0x002a
91 #define regVPEC_QUEUE_RESET_REQ_BASE_IDX                                                                0
92 #define regVPEC_PERFCNT_PERFCOUNTER0_CFG                                                                0x002b
93 #define regVPEC_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX                                                       0
94 #define regVPEC_PERFCNT_PERFCOUNTER1_CFG                                                                0x002c
95 #define regVPEC_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX                                                       0
96 #define regVPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL                                                           0x002d
97 #define regVPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                  0
98 #define regVPEC_PERFCNT_MISC_CNTL                                                                       0x002e
99 #define regVPEC_PERFCNT_MISC_CNTL_BASE_IDX                                                              0
100 #define regVPEC_PERFCNT_PERFCOUNTER_LO                                                                  0x002f
101 #define regVPEC_PERFCNT_PERFCOUNTER_LO_BASE_IDX                                                         0
102 #define regVPEC_PERFCNT_PERFCOUNTER_HI                                                                  0x0030
103 #define regVPEC_PERFCNT_PERFCOUNTER_HI_BASE_IDX                                                         0
104 #define regVPEC_CRC_CTRL                                                                                0x0033
105 #define regVPEC_CRC_CTRL_BASE_IDX                                                                       0
106 #define regVPEC_CRC_DATA                                                                                0x0034
107 #define regVPEC_CRC_DATA_BASE_IDX                                                                       0
108 #define regVPEC_PUB_DUMMY0                                                                              0x0035
109 #define regVPEC_PUB_DUMMY0_BASE_IDX                                                                     0
110 #define regVPEC_PUB_DUMMY1                                                                              0x0036
111 #define regVPEC_PUB_DUMMY1_BASE_IDX                                                                     0
112 #define regVPEC_PUB_DUMMY2                                                                              0x0037
113 #define regVPEC_PUB_DUMMY2_BASE_IDX                                                                     0
114 #define regVPEC_PUB_DUMMY3                                                                              0x0038
115 #define regVPEC_PUB_DUMMY3_BASE_IDX                                                                     0
116 #define regVPEC_PUB_DUMMY4                                                                              0x0039
117 #define regVPEC_PUB_DUMMY4_BASE_IDX                                                                     0
118 #define regVPEC_PUB_DUMMY5                                                                              0x003a
119 #define regVPEC_PUB_DUMMY5_BASE_IDX                                                                     0
120 #define regVPEC_PUB_DUMMY6                                                                              0x003b
121 #define regVPEC_PUB_DUMMY6_BASE_IDX                                                                     0
122 #define regVPEC_PUB_DUMMY7                                                                              0x003c
123 #define regVPEC_PUB_DUMMY7_BASE_IDX                                                                     0
124 #define regVPEC_UCODE1_CHECKSUM                                                                         0x0040
125 #define regVPEC_UCODE1_CHECKSUM_BASE_IDX                                                                0
126 #define regVPEC_VERSION                                                                                 0x0041
127 #define regVPEC_VERSION_BASE_IDX                                                                        0
128 #define regVPEC_UCODE_CHECKSUM                                                                          0x0042
129 #define regVPEC_UCODE_CHECKSUM_BASE_IDX                                                                 0
130 #define regVPEC_CLOCK_GATING_STATUS                                                                     0x0043
131 #define regVPEC_CLOCK_GATING_STATUS_BASE_IDX                                                            0
132 #define regVPEC_RB_RPTR_FETCH                                                                           0x0044
133 #define regVPEC_RB_RPTR_FETCH_BASE_IDX                                                                  0
134 #define regVPEC_RB_RPTR_FETCH_HI                                                                        0x0045
135 #define regVPEC_RB_RPTR_FETCH_HI_BASE_IDX                                                               0
136 #define regVPEC_IB_OFFSET_FETCH                                                                         0x0046
137 #define regVPEC_IB_OFFSET_FETCH_BASE_IDX                                                                0
138 #define regVPEC_CMDIB_OFFSET_FETCH                                                                      0x0047
139 #define regVPEC_CMDIB_OFFSET_FETCH_BASE_IDX                                                             0
140 #define regVPEC_ATOMIC_PREOP_LO                                                                         0x0048
141 #define regVPEC_ATOMIC_PREOP_LO_BASE_IDX                                                                0
142 #define regVPEC_ATOMIC_PREOP_HI                                                                         0x0049
143 #define regVPEC_ATOMIC_PREOP_HI_BASE_IDX                                                                0
144 #define regVPEC_CE_BUSY                                                                                 0x004a
145 #define regVPEC_CE_BUSY_BASE_IDX                                                                        0
146 #define regVPEC_F32_COUNTER                                                                             0x004b
147 #define regVPEC_F32_COUNTER_BASE_IDX                                                                    0
148 #define regVPEC_HOLE_ADDR_LO                                                                            0x004c
149 #define regVPEC_HOLE_ADDR_LO_BASE_IDX                                                                   0
150 #define regVPEC_HOLE_ADDR_HI                                                                            0x004d
151 #define regVPEC_HOLE_ADDR_HI_BASE_IDX                                                                   0
152 #define regVPEC_ERROR_LOG                                                                               0x004e
153 #define regVPEC_ERROR_LOG_BASE_IDX                                                                      0
154 #define regVPEC_INT_STATUS                                                                              0x004f
155 #define regVPEC_INT_STATUS_BASE_IDX                                                                     0
156 #define regVPEC_STATUS                                                                                  0x0050
157 #define regVPEC_STATUS_BASE_IDX                                                                         0
158 #define regVPEC_STATUS1                                                                                 0x0051
159 #define regVPEC_STATUS1_BASE_IDX                                                                        0
160 #define regVPEC_STATUS2                                                                                 0x0052
161 #define regVPEC_STATUS2_BASE_IDX                                                                        0
162 #define regVPEC_STATUS3                                                                                 0x0053
163 #define regVPEC_STATUS3_BASE_IDX                                                                        0
164 #define regVPEC_STATUS4                                                                                 0x0054
165 #define regVPEC_STATUS4_BASE_IDX                                                                        0
166 #define regVPEC_STATUS5                                                                                 0x0055
167 #define regVPEC_STATUS5_BASE_IDX                                                                        0
168 #define regVPEC_STATUS6                                                                                 0x0056
169 #define regVPEC_STATUS6_BASE_IDX                                                                        0
170 #define regVPEC_STATUS7                                                                                 0x0057
171 #define regVPEC_STATUS7_BASE_IDX                                                                        0
172 #define regVPEC_INST                                                                                    0x0058
173 #define regVPEC_INST_BASE_IDX                                                                           0
174 #define regVPEC_QUEUE_STATUS0                                                                           0x0059
175 #define regVPEC_QUEUE_STATUS0_BASE_IDX                                                                  0
176 #define regVPEC_QUEUE_HANG_STATUS                                                                       0x005a
177 #define regVPEC_QUEUE_HANG_STATUS_BASE_IDX                                                              0
178 #define regVPEC_QUEUE0_RB_CNTL                                                                          0x0080
179 #define regVPEC_QUEUE0_RB_CNTL_BASE_IDX                                                                 0
180 #define regVPEC_QUEUE0_SCHEDULE_CNTL                                                                    0x0081
181 #define regVPEC_QUEUE0_SCHEDULE_CNTL_BASE_IDX                                                           0
182 #define regVPEC_QUEUE0_RB_BASE                                                                          0x0082
183 #define regVPEC_QUEUE0_RB_BASE_BASE_IDX                                                                 0
184 #define regVPEC_QUEUE0_RB_BASE_HI                                                                       0x0083
185 #define regVPEC_QUEUE0_RB_BASE_HI_BASE_IDX                                                              0
186 #define regVPEC_QUEUE0_RB_RPTR                                                                          0x0084
187 #define regVPEC_QUEUE0_RB_RPTR_BASE_IDX                                                                 0
188 #define regVPEC_QUEUE0_RB_RPTR_HI                                                                       0x0085
189 #define regVPEC_QUEUE0_RB_RPTR_HI_BASE_IDX                                                              0
190 #define regVPEC_QUEUE0_RB_WPTR                                                                          0x0086
191 #define regVPEC_QUEUE0_RB_WPTR_BASE_IDX                                                                 0
192 #define regVPEC_QUEUE0_RB_WPTR_HI                                                                       0x0087
193 #define regVPEC_QUEUE0_RB_WPTR_HI_BASE_IDX                                                              0
194 #define regVPEC_QUEUE0_RB_RPTR_ADDR_HI                                                                  0x0088
195 #define regVPEC_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX                                                         0
196 #define regVPEC_QUEUE0_RB_RPTR_ADDR_LO                                                                  0x0089
197 #define regVPEC_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX                                                         0
198 #define regVPEC_QUEUE0_RB_AQL_CNTL                                                                      0x008a
199 #define regVPEC_QUEUE0_RB_AQL_CNTL_BASE_IDX                                                             0
200 #define regVPEC_QUEUE0_MINOR_PTR_UPDATE                                                                 0x008b
201 #define regVPEC_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX                                                        0
202 #define regVPEC_QUEUE0_CD_INFO                                                                          0x008c
203 #define regVPEC_QUEUE0_CD_INFO_BASE_IDX                                                                 0
204 #define regVPEC_QUEUE0_RB_PREEMPT                                                                       0x008d
205 #define regVPEC_QUEUE0_RB_PREEMPT_BASE_IDX                                                              0
206 #define regVPEC_QUEUE0_SKIP_CNTL                                                                        0x008e
207 #define regVPEC_QUEUE0_SKIP_CNTL_BASE_IDX                                                               0
208 #define regVPEC_QUEUE0_DOORBELL                                                                         0x008f
209 #define regVPEC_QUEUE0_DOORBELL_BASE_IDX                                                                0
210 #define regVPEC_QUEUE0_DOORBELL_OFFSET                                                                  0x0090
211 #define regVPEC_QUEUE0_DOORBELL_OFFSET_BASE_IDX                                                         0
212 #define regVPEC_QUEUE0_DUMMY0                                                                           0x0091
213 #define regVPEC_QUEUE0_DUMMY0_BASE_IDX                                                                  0
214 #define regVPEC_QUEUE0_DUMMY1                                                                           0x0092
215 #define regVPEC_QUEUE0_DUMMY1_BASE_IDX                                                                  0
216 #define regVPEC_QUEUE0_DUMMY2                                                                           0x0093
217 #define regVPEC_QUEUE0_DUMMY2_BASE_IDX                                                                  0
218 #define regVPEC_QUEUE0_DUMMY3                                                                           0x0094
219 #define regVPEC_QUEUE0_DUMMY3_BASE_IDX                                                                  0
220 #define regVPEC_QUEUE0_DUMMY4                                                                           0x0095
221 #define regVPEC_QUEUE0_DUMMY4_BASE_IDX                                                                  0
222 #define regVPEC_QUEUE0_IB_CNTL                                                                          0x00ac
223 #define regVPEC_QUEUE0_IB_CNTL_BASE_IDX                                                                 0
224 #define regVPEC_QUEUE0_IB_RPTR                                                                          0x00ad
225 #define regVPEC_QUEUE0_IB_RPTR_BASE_IDX                                                                 0
226 #define regVPEC_QUEUE0_IB_OFFSET                                                                        0x00ae
227 #define regVPEC_QUEUE0_IB_OFFSET_BASE_IDX                                                               0
228 #define regVPEC_QUEUE0_IB_BASE_LO                                                                       0x00af
229 #define regVPEC_QUEUE0_IB_BASE_LO_BASE_IDX                                                              0
230 #define regVPEC_QUEUE0_IB_BASE_HI                                                                       0x00b0
231 #define regVPEC_QUEUE0_IB_BASE_HI_BASE_IDX                                                              0
232 #define regVPEC_QUEUE0_IB_SIZE                                                                          0x00b1
233 #define regVPEC_QUEUE0_IB_SIZE_BASE_IDX                                                                 0
234 #define regVPEC_QUEUE0_CMDIB_CNTL                                                                       0x00b2
235 #define regVPEC_QUEUE0_CMDIB_CNTL_BASE_IDX                                                              0
236 #define regVPEC_QUEUE0_CMDIB_RPTR                                                                       0x00b3
237 #define regVPEC_QUEUE0_CMDIB_RPTR_BASE_IDX                                                              0
238 #define regVPEC_QUEUE0_CMDIB_OFFSET                                                                     0x00b4
239 #define regVPEC_QUEUE0_CMDIB_OFFSET_BASE_IDX                                                            0
240 #define regVPEC_QUEUE0_CMDIB_BASE_LO                                                                    0x00b5
241 #define regVPEC_QUEUE0_CMDIB_BASE_LO_BASE_IDX                                                           0
242 #define regVPEC_QUEUE0_CMDIB_BASE_HI                                                                    0x00b6
243 #define regVPEC_QUEUE0_CMDIB_BASE_HI_BASE_IDX                                                           0
244 #define regVPEC_QUEUE0_CMDIB_SIZE                                                                       0x00b7
245 #define regVPEC_QUEUE0_CMDIB_SIZE_BASE_IDX                                                              0
246 #define regVPEC_QUEUE0_CSA_ADDR_LO                                                                      0x00b8
247 #define regVPEC_QUEUE0_CSA_ADDR_LO_BASE_IDX                                                             0
248 #define regVPEC_QUEUE0_CSA_ADDR_HI                                                                      0x00b9
249 #define regVPEC_QUEUE0_CSA_ADDR_HI_BASE_IDX                                                             0
250 #define regVPEC_QUEUE0_CONTEXT_STATUS                                                                   0x00ba
251 #define regVPEC_QUEUE0_CONTEXT_STATUS_BASE_IDX                                                          0
252 #define regVPEC_QUEUE0_DOORBELL_LOG                                                                     0x00bb
253 #define regVPEC_QUEUE0_DOORBELL_LOG_BASE_IDX                                                            0
254 #define regVPEC_QUEUE0_IB_SUB_REMAIN                                                                    0x00bc
255 #define regVPEC_QUEUE0_IB_SUB_REMAIN_BASE_IDX                                                           0
256 #define regVPEC_QUEUE0_PREEMPT                                                                          0x00bd
257 #define regVPEC_QUEUE0_PREEMPT_BASE_IDX                                                                 0
258 #define regVPEC_QUEUE1_RB_CNTL                                                                          0x00d8
259 #define regVPEC_QUEUE1_RB_CNTL_BASE_IDX                                                                 0
260 #define regVPEC_QUEUE1_SCHEDULE_CNTL                                                                    0x00d9
261 #define regVPEC_QUEUE1_SCHEDULE_CNTL_BASE_IDX                                                           0
262 #define regVPEC_QUEUE1_RB_BASE                                                                          0x00da
263 #define regVPEC_QUEUE1_RB_BASE_BASE_IDX                                                                 0
264 #define regVPEC_QUEUE1_RB_BASE_HI                                                                       0x00db
265 #define regVPEC_QUEUE1_RB_BASE_HI_BASE_IDX                                                              0
266 #define regVPEC_QUEUE1_RB_RPTR                                                                          0x00dc
267 #define regVPEC_QUEUE1_RB_RPTR_BASE_IDX                                                                 0
268 #define regVPEC_QUEUE1_RB_RPTR_HI                                                                       0x00dd
269 #define regVPEC_QUEUE1_RB_RPTR_HI_BASE_IDX                                                              0
270 #define regVPEC_QUEUE1_RB_WPTR                                                                          0x00de
271 #define regVPEC_QUEUE1_RB_WPTR_BASE_IDX                                                                 0
272 #define regVPEC_QUEUE1_RB_WPTR_HI                                                                       0x00df
273 #define regVPEC_QUEUE1_RB_WPTR_HI_BASE_IDX                                                              0
274 #define regVPEC_QUEUE1_RB_RPTR_ADDR_HI                                                                  0x00e0
275 #define regVPEC_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX                                                         0
276 #define regVPEC_QUEUE1_RB_RPTR_ADDR_LO                                                                  0x00e1
277 #define regVPEC_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX                                                         0
278 #define regVPEC_QUEUE1_RB_AQL_CNTL                                                                      0x00e2
279 #define regVPEC_QUEUE1_RB_AQL_CNTL_BASE_IDX                                                             0
280 #define regVPEC_QUEUE1_MINOR_PTR_UPDATE                                                                 0x00e3
281 #define regVPEC_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX                                                        0
282 #define regVPEC_QUEUE1_CD_INFO                                                                          0x00e4
283 #define regVPEC_QUEUE1_CD_INFO_BASE_IDX                                                                 0
284 #define regVPEC_QUEUE1_RB_PREEMPT                                                                       0x00e5
285 #define regVPEC_QUEUE1_RB_PREEMPT_BASE_IDX                                                              0
286 #define regVPEC_QUEUE1_SKIP_CNTL                                                                        0x00e6
287 #define regVPEC_QUEUE1_SKIP_CNTL_BASE_IDX                                                               0
288 #define regVPEC_QUEUE1_DOORBELL                                                                         0x00e7
289 #define regVPEC_QUEUE1_DOORBELL_BASE_IDX                                                                0
290 #define regVPEC_QUEUE1_DOORBELL_OFFSET                                                                  0x00e8
291 #define regVPEC_QUEUE1_DOORBELL_OFFSET_BASE_IDX                                                         0
292 #define regVPEC_QUEUE1_DUMMY0                                                                           0x00e9
293 #define regVPEC_QUEUE1_DUMMY0_BASE_IDX                                                                  0
294 #define regVPEC_QUEUE1_DUMMY1                                                                           0x00ea
295 #define regVPEC_QUEUE1_DUMMY1_BASE_IDX                                                                  0
296 #define regVPEC_QUEUE1_DUMMY2                                                                           0x00eb
297 #define regVPEC_QUEUE1_DUMMY2_BASE_IDX                                                                  0
298 #define regVPEC_QUEUE1_DUMMY3                                                                           0x00ec
299 #define regVPEC_QUEUE1_DUMMY3_BASE_IDX                                                                  0
300 #define regVPEC_QUEUE1_DUMMY4                                                                           0x00ed
301 #define regVPEC_QUEUE1_DUMMY4_BASE_IDX                                                                  0
302 #define regVPEC_QUEUE1_IB_CNTL                                                                          0x0104
303 #define regVPEC_QUEUE1_IB_CNTL_BASE_IDX                                                                 0
304 #define regVPEC_QUEUE1_IB_RPTR                                                                          0x0105
305 #define regVPEC_QUEUE1_IB_RPTR_BASE_IDX                                                                 0
306 #define regVPEC_QUEUE1_IB_OFFSET                                                                        0x0106
307 #define regVPEC_QUEUE1_IB_OFFSET_BASE_IDX                                                               0
308 #define regVPEC_QUEUE1_IB_BASE_LO                                                                       0x0107
309 #define regVPEC_QUEUE1_IB_BASE_LO_BASE_IDX                                                              0
310 #define regVPEC_QUEUE1_IB_BASE_HI                                                                       0x0108
311 #define regVPEC_QUEUE1_IB_BASE_HI_BASE_IDX                                                              0
312 #define regVPEC_QUEUE1_IB_SIZE                                                                          0x0109
313 #define regVPEC_QUEUE1_IB_SIZE_BASE_IDX                                                                 0
314 #define regVPEC_QUEUE1_CMDIB_CNTL                                                                       0x010a
315 #define regVPEC_QUEUE1_CMDIB_CNTL_BASE_IDX                                                              0
316 #define regVPEC_QUEUE1_CMDIB_RPTR                                                                       0x010b
317 #define regVPEC_QUEUE1_CMDIB_RPTR_BASE_IDX                                                              0
318 #define regVPEC_QUEUE1_CMDIB_OFFSET                                                                     0x010c
319 #define regVPEC_QUEUE1_CMDIB_OFFSET_BASE_IDX                                                            0
320 #define regVPEC_QUEUE1_CMDIB_BASE_LO                                                                    0x010d
321 #define regVPEC_QUEUE1_CMDIB_BASE_LO_BASE_IDX                                                           0
322 #define regVPEC_QUEUE1_CMDIB_BASE_HI                                                                    0x010e
323 #define regVPEC_QUEUE1_CMDIB_BASE_HI_BASE_IDX                                                           0
324 #define regVPEC_QUEUE1_CMDIB_SIZE                                                                       0x010f
325 #define regVPEC_QUEUE1_CMDIB_SIZE_BASE_IDX                                                              0
326 #define regVPEC_QUEUE1_CSA_ADDR_LO                                                                      0x0110
327 #define regVPEC_QUEUE1_CSA_ADDR_LO_BASE_IDX                                                             0
328 #define regVPEC_QUEUE1_CSA_ADDR_HI                                                                      0x0111
329 #define regVPEC_QUEUE1_CSA_ADDR_HI_BASE_IDX                                                             0
330 #define regVPEC_QUEUE1_CONTEXT_STATUS                                                                   0x0112
331 #define regVPEC_QUEUE1_CONTEXT_STATUS_BASE_IDX                                                          0
332 #define regVPEC_QUEUE1_DOORBELL_LOG                                                                     0x0113
333 #define regVPEC_QUEUE1_DOORBELL_LOG_BASE_IDX                                                            0
334 #define regVPEC_QUEUE1_IB_SUB_REMAIN                                                                    0x0114
335 #define regVPEC_QUEUE1_IB_SUB_REMAIN_BASE_IDX                                                           0
336 #define regVPEC_QUEUE1_PREEMPT                                                                          0x0115
337 #define regVPEC_QUEUE1_PREEMPT_BASE_IDX                                                                 0
338 #define regVPEC_QUEUE2_RB_CNTL                                                                          0x0130
339 #define regVPEC_QUEUE2_RB_CNTL_BASE_IDX                                                                 0
340 #define regVPEC_QUEUE2_SCHEDULE_CNTL                                                                    0x0131
341 #define regVPEC_QUEUE2_SCHEDULE_CNTL_BASE_IDX                                                           0
342 #define regVPEC_QUEUE2_RB_BASE                                                                          0x0132
343 #define regVPEC_QUEUE2_RB_BASE_BASE_IDX                                                                 0
344 #define regVPEC_QUEUE2_RB_BASE_HI                                                                       0x0133
345 #define regVPEC_QUEUE2_RB_BASE_HI_BASE_IDX                                                              0
346 #define regVPEC_QUEUE2_RB_RPTR                                                                          0x0134
347 #define regVPEC_QUEUE2_RB_RPTR_BASE_IDX                                                                 0
348 #define regVPEC_QUEUE2_RB_RPTR_HI                                                                       0x0135
349 #define regVPEC_QUEUE2_RB_RPTR_HI_BASE_IDX                                                              0
350 #define regVPEC_QUEUE2_RB_WPTR                                                                          0x0136
351 #define regVPEC_QUEUE2_RB_WPTR_BASE_IDX                                                                 0
352 #define regVPEC_QUEUE2_RB_WPTR_HI                                                                       0x0137
353 #define regVPEC_QUEUE2_RB_WPTR_HI_BASE_IDX                                                              0
354 #define regVPEC_QUEUE2_RB_RPTR_ADDR_HI                                                                  0x0138
355 #define regVPEC_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX                                                         0
356 #define regVPEC_QUEUE2_RB_RPTR_ADDR_LO                                                                  0x0139
357 #define regVPEC_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX                                                         0
358 #define regVPEC_QUEUE2_RB_AQL_CNTL                                                                      0x013a
359 #define regVPEC_QUEUE2_RB_AQL_CNTL_BASE_IDX                                                             0
360 #define regVPEC_QUEUE2_MINOR_PTR_UPDATE                                                                 0x013b
361 #define regVPEC_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX                                                        0
362 #define regVPEC_QUEUE2_CD_INFO                                                                          0x013c
363 #define regVPEC_QUEUE2_CD_INFO_BASE_IDX                                                                 0
364 #define regVPEC_QUEUE2_RB_PREEMPT                                                                       0x013d
365 #define regVPEC_QUEUE2_RB_PREEMPT_BASE_IDX                                                              0
366 #define regVPEC_QUEUE2_SKIP_CNTL                                                                        0x013e
367 #define regVPEC_QUEUE2_SKIP_CNTL_BASE_IDX                                                               0
368 #define regVPEC_QUEUE2_DOORBELL                                                                         0x013f
369 #define regVPEC_QUEUE2_DOORBELL_BASE_IDX                                                                0
370 #define regVPEC_QUEUE2_DOORBELL_OFFSET                                                                  0x0140
371 #define regVPEC_QUEUE2_DOORBELL_OFFSET_BASE_IDX                                                         0
372 #define regVPEC_QUEUE2_DUMMY0                                                                           0x0141
373 #define regVPEC_QUEUE2_DUMMY0_BASE_IDX                                                                  0
374 #define regVPEC_QUEUE2_DUMMY1                                                                           0x0142
375 #define regVPEC_QUEUE2_DUMMY1_BASE_IDX                                                                  0
376 #define regVPEC_QUEUE2_DUMMY2                                                                           0x0143
377 #define regVPEC_QUEUE2_DUMMY2_BASE_IDX                                                                  0
378 #define regVPEC_QUEUE2_DUMMY3                                                                           0x0144
379 #define regVPEC_QUEUE2_DUMMY3_BASE_IDX                                                                  0
380 #define regVPEC_QUEUE2_DUMMY4                                                                           0x0145
381 #define regVPEC_QUEUE2_DUMMY4_BASE_IDX                                                                  0
382 #define regVPEC_QUEUE2_IB_CNTL                                                                          0x015c
383 #define regVPEC_QUEUE2_IB_CNTL_BASE_IDX                                                                 0
384 #define regVPEC_QUEUE2_IB_RPTR                                                                          0x015d
385 #define regVPEC_QUEUE2_IB_RPTR_BASE_IDX                                                                 0
386 #define regVPEC_QUEUE2_IB_OFFSET                                                                        0x015e
387 #define regVPEC_QUEUE2_IB_OFFSET_BASE_IDX                                                               0
388 #define regVPEC_QUEUE2_IB_BASE_LO                                                                       0x015f
389 #define regVPEC_QUEUE2_IB_BASE_LO_BASE_IDX                                                              0
390 #define regVPEC_QUEUE2_IB_BASE_HI                                                                       0x0160
391 #define regVPEC_QUEUE2_IB_BASE_HI_BASE_IDX                                                              0
392 #define regVPEC_QUEUE2_IB_SIZE                                                                          0x0161
393 #define regVPEC_QUEUE2_IB_SIZE_BASE_IDX                                                                 0
394 #define regVPEC_QUEUE2_CMDIB_CNTL                                                                       0x0162
395 #define regVPEC_QUEUE2_CMDIB_CNTL_BASE_IDX                                                              0
396 #define regVPEC_QUEUE2_CMDIB_RPTR                                                                       0x0163
397 #define regVPEC_QUEUE2_CMDIB_RPTR_BASE_IDX                                                              0
398 #define regVPEC_QUEUE2_CMDIB_OFFSET                                                                     0x0164
399 #define regVPEC_QUEUE2_CMDIB_OFFSET_BASE_IDX                                                            0
400 #define regVPEC_QUEUE2_CMDIB_BASE_LO                                                                    0x0165
401 #define regVPEC_QUEUE2_CMDIB_BASE_LO_BASE_IDX                                                           0
402 #define regVPEC_QUEUE2_CMDIB_BASE_HI                                                                    0x0166
403 #define regVPEC_QUEUE2_CMDIB_BASE_HI_BASE_IDX                                                           0
404 #define regVPEC_QUEUE2_CMDIB_SIZE                                                                       0x0167
405 #define regVPEC_QUEUE2_CMDIB_SIZE_BASE_IDX                                                              0
406 #define regVPEC_QUEUE2_CSA_ADDR_LO                                                                      0x0168
407 #define regVPEC_QUEUE2_CSA_ADDR_LO_BASE_IDX                                                             0
408 #define regVPEC_QUEUE2_CSA_ADDR_HI                                                                      0x0169
409 #define regVPEC_QUEUE2_CSA_ADDR_HI_BASE_IDX                                                             0
410 #define regVPEC_QUEUE2_CONTEXT_STATUS                                                                   0x016a
411 #define regVPEC_QUEUE2_CONTEXT_STATUS_BASE_IDX                                                          0
412 #define regVPEC_QUEUE2_DOORBELL_LOG                                                                     0x016b
413 #define regVPEC_QUEUE2_DOORBELL_LOG_BASE_IDX                                                            0
414 #define regVPEC_QUEUE2_IB_SUB_REMAIN                                                                    0x016c
415 #define regVPEC_QUEUE2_IB_SUB_REMAIN_BASE_IDX                                                           0
416 #define regVPEC_QUEUE2_PREEMPT                                                                          0x016d
417 #define regVPEC_QUEUE2_PREEMPT_BASE_IDX                                                                 0
418 #define regVPEC_QUEUE3_RB_CNTL                                                                          0x0188
419 #define regVPEC_QUEUE3_RB_CNTL_BASE_IDX                                                                 0
420 #define regVPEC_QUEUE3_SCHEDULE_CNTL                                                                    0x0189
421 #define regVPEC_QUEUE3_SCHEDULE_CNTL_BASE_IDX                                                           0
422 #define regVPEC_QUEUE3_RB_BASE                                                                          0x018a
423 #define regVPEC_QUEUE3_RB_BASE_BASE_IDX                                                                 0
424 #define regVPEC_QUEUE3_RB_BASE_HI                                                                       0x018b
425 #define regVPEC_QUEUE3_RB_BASE_HI_BASE_IDX                                                              0
426 #define regVPEC_QUEUE3_RB_RPTR                                                                          0x018c
427 #define regVPEC_QUEUE3_RB_RPTR_BASE_IDX                                                                 0
428 #define regVPEC_QUEUE3_RB_RPTR_HI                                                                       0x018d
429 #define regVPEC_QUEUE3_RB_RPTR_HI_BASE_IDX                                                              0
430 #define regVPEC_QUEUE3_RB_WPTR                                                                          0x018e
431 #define regVPEC_QUEUE3_RB_WPTR_BASE_IDX                                                                 0
432 #define regVPEC_QUEUE3_RB_WPTR_HI                                                                       0x018f
433 #define regVPEC_QUEUE3_RB_WPTR_HI_BASE_IDX                                                              0
434 #define regVPEC_QUEUE3_RB_RPTR_ADDR_HI                                                                  0x0190
435 #define regVPEC_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX                                                         0
436 #define regVPEC_QUEUE3_RB_RPTR_ADDR_LO                                                                  0x0191
437 #define regVPEC_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX                                                         0
438 #define regVPEC_QUEUE3_RB_AQL_CNTL                                                                      0x0192
439 #define regVPEC_QUEUE3_RB_AQL_CNTL_BASE_IDX                                                             0
440 #define regVPEC_QUEUE3_MINOR_PTR_UPDATE                                                                 0x0193
441 #define regVPEC_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX                                                        0
442 #define regVPEC_QUEUE3_CD_INFO                                                                          0x0194
443 #define regVPEC_QUEUE3_CD_INFO_BASE_IDX                                                                 0
444 #define regVPEC_QUEUE3_RB_PREEMPT                                                                       0x0195
445 #define regVPEC_QUEUE3_RB_PREEMPT_BASE_IDX                                                              0
446 #define regVPEC_QUEUE3_SKIP_CNTL                                                                        0x0196
447 #define regVPEC_QUEUE3_SKIP_CNTL_BASE_IDX                                                               0
448 #define regVPEC_QUEUE3_DOORBELL                                                                         0x0197
449 #define regVPEC_QUEUE3_DOORBELL_BASE_IDX                                                                0
450 #define regVPEC_QUEUE3_DOORBELL_OFFSET                                                                  0x0198
451 #define regVPEC_QUEUE3_DOORBELL_OFFSET_BASE_IDX                                                         0
452 #define regVPEC_QUEUE3_DUMMY0                                                                           0x0199
453 #define regVPEC_QUEUE3_DUMMY0_BASE_IDX                                                                  0
454 #define regVPEC_QUEUE3_DUMMY1                                                                           0x019a
455 #define regVPEC_QUEUE3_DUMMY1_BASE_IDX                                                                  0
456 #define regVPEC_QUEUE3_DUMMY2                                                                           0x019b
457 #define regVPEC_QUEUE3_DUMMY2_BASE_IDX                                                                  0
458 #define regVPEC_QUEUE3_DUMMY3                                                                           0x019c
459 #define regVPEC_QUEUE3_DUMMY3_BASE_IDX                                                                  0
460 #define regVPEC_QUEUE3_DUMMY4                                                                           0x019d
461 #define regVPEC_QUEUE3_DUMMY4_BASE_IDX                                                                  0
462 #define regVPEC_QUEUE3_IB_CNTL                                                                          0x01b4
463 #define regVPEC_QUEUE3_IB_CNTL_BASE_IDX                                                                 0
464 #define regVPEC_QUEUE3_IB_RPTR                                                                          0x01b5
465 #define regVPEC_QUEUE3_IB_RPTR_BASE_IDX                                                                 0
466 #define regVPEC_QUEUE3_IB_OFFSET                                                                        0x01b6
467 #define regVPEC_QUEUE3_IB_OFFSET_BASE_IDX                                                               0
468 #define regVPEC_QUEUE3_IB_BASE_LO                                                                       0x01b7
469 #define regVPEC_QUEUE3_IB_BASE_LO_BASE_IDX                                                              0
470 #define regVPEC_QUEUE3_IB_BASE_HI                                                                       0x01b8
471 #define regVPEC_QUEUE3_IB_BASE_HI_BASE_IDX                                                              0
472 #define regVPEC_QUEUE3_IB_SIZE                                                                          0x01b9
473 #define regVPEC_QUEUE3_IB_SIZE_BASE_IDX                                                                 0
474 #define regVPEC_QUEUE3_CMDIB_CNTL                                                                       0x01ba
475 #define regVPEC_QUEUE3_CMDIB_CNTL_BASE_IDX                                                              0
476 #define regVPEC_QUEUE3_CMDIB_RPTR                                                                       0x01bb
477 #define regVPEC_QUEUE3_CMDIB_RPTR_BASE_IDX                                                              0
478 #define regVPEC_QUEUE3_CMDIB_OFFSET                                                                     0x01bc
479 #define regVPEC_QUEUE3_CMDIB_OFFSET_BASE_IDX                                                            0
480 #define regVPEC_QUEUE3_CMDIB_BASE_LO                                                                    0x01bd
481 #define regVPEC_QUEUE3_CMDIB_BASE_LO_BASE_IDX                                                           0
482 #define regVPEC_QUEUE3_CMDIB_BASE_HI                                                                    0x01be
483 #define regVPEC_QUEUE3_CMDIB_BASE_HI_BASE_IDX                                                           0
484 #define regVPEC_QUEUE3_CMDIB_SIZE                                                                       0x01bf
485 #define regVPEC_QUEUE3_CMDIB_SIZE_BASE_IDX                                                              0
486 #define regVPEC_QUEUE3_CSA_ADDR_LO                                                                      0x01c0
487 #define regVPEC_QUEUE3_CSA_ADDR_LO_BASE_IDX                                                             0
488 #define regVPEC_QUEUE3_CSA_ADDR_HI                                                                      0x01c1
489 #define regVPEC_QUEUE3_CSA_ADDR_HI_BASE_IDX                                                             0
490 #define regVPEC_QUEUE3_CONTEXT_STATUS                                                                   0x01c2
491 #define regVPEC_QUEUE3_CONTEXT_STATUS_BASE_IDX                                                          0
492 #define regVPEC_QUEUE3_DOORBELL_LOG                                                                     0x01c3
493 #define regVPEC_QUEUE3_DOORBELL_LOG_BASE_IDX                                                            0
494 #define regVPEC_QUEUE3_IB_SUB_REMAIN                                                                    0x01c4
495 #define regVPEC_QUEUE3_IB_SUB_REMAIN_BASE_IDX                                                           0
496 #define regVPEC_QUEUE3_PREEMPT                                                                          0x01c5
497 #define regVPEC_QUEUE3_PREEMPT_BASE_IDX                                                                 0
498 #define regVPEC_QUEUE4_RB_CNTL                                                                          0x01e0
499 #define regVPEC_QUEUE4_RB_CNTL_BASE_IDX                                                                 0
500 #define regVPEC_QUEUE4_SCHEDULE_CNTL                                                                    0x01e1
501 #define regVPEC_QUEUE4_SCHEDULE_CNTL_BASE_IDX                                                           0
502 #define regVPEC_QUEUE4_RB_BASE                                                                          0x01e2
503 #define regVPEC_QUEUE4_RB_BASE_BASE_IDX                                                                 0
504 #define regVPEC_QUEUE4_RB_BASE_HI                                                                       0x01e3
505 #define regVPEC_QUEUE4_RB_BASE_HI_BASE_IDX                                                              0
506 #define regVPEC_QUEUE4_RB_RPTR                                                                          0x01e4
507 #define regVPEC_QUEUE4_RB_RPTR_BASE_IDX                                                                 0
508 #define regVPEC_QUEUE4_RB_RPTR_HI                                                                       0x01e5
509 #define regVPEC_QUEUE4_RB_RPTR_HI_BASE_IDX                                                              0
510 #define regVPEC_QUEUE4_RB_WPTR                                                                          0x01e6
511 #define regVPEC_QUEUE4_RB_WPTR_BASE_IDX                                                                 0
512 #define regVPEC_QUEUE4_RB_WPTR_HI                                                                       0x01e7
513 #define regVPEC_QUEUE4_RB_WPTR_HI_BASE_IDX                                                              0
514 #define regVPEC_QUEUE4_RB_RPTR_ADDR_HI                                                                  0x01e8
515 #define regVPEC_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX                                                         0
516 #define regVPEC_QUEUE4_RB_RPTR_ADDR_LO                                                                  0x01e9
517 #define regVPEC_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX                                                         0
518 #define regVPEC_QUEUE4_RB_AQL_CNTL                                                                      0x01ea
519 #define regVPEC_QUEUE4_RB_AQL_CNTL_BASE_IDX                                                             0
520 #define regVPEC_QUEUE4_MINOR_PTR_UPDATE                                                                 0x01eb
521 #define regVPEC_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX                                                        0
522 #define regVPEC_QUEUE4_CD_INFO                                                                          0x01ec
523 #define regVPEC_QUEUE4_CD_INFO_BASE_IDX                                                                 0
524 #define regVPEC_QUEUE4_RB_PREEMPT                                                                       0x01ed
525 #define regVPEC_QUEUE4_RB_PREEMPT_BASE_IDX                                                              0
526 #define regVPEC_QUEUE4_SKIP_CNTL                                                                        0x01ee
527 #define regVPEC_QUEUE4_SKIP_CNTL_BASE_IDX                                                               0
528 #define regVPEC_QUEUE4_DOORBELL                                                                         0x01ef
529 #define regVPEC_QUEUE4_DOORBELL_BASE_IDX                                                                0
530 #define regVPEC_QUEUE4_DOORBELL_OFFSET                                                                  0x01f0
531 #define regVPEC_QUEUE4_DOORBELL_OFFSET_BASE_IDX                                                         0
532 #define regVPEC_QUEUE4_DUMMY0                                                                           0x01f1
533 #define regVPEC_QUEUE4_DUMMY0_BASE_IDX                                                                  0
534 #define regVPEC_QUEUE4_DUMMY1                                                                           0x01f2
535 #define regVPEC_QUEUE4_DUMMY1_BASE_IDX                                                                  0
536 #define regVPEC_QUEUE4_DUMMY2                                                                           0x01f3
537 #define regVPEC_QUEUE4_DUMMY2_BASE_IDX                                                                  0
538 #define regVPEC_QUEUE4_DUMMY3                                                                           0x01f4
539 #define regVPEC_QUEUE4_DUMMY3_BASE_IDX                                                                  0
540 #define regVPEC_QUEUE4_DUMMY4                                                                           0x01f5
541 #define regVPEC_QUEUE4_DUMMY4_BASE_IDX                                                                  0
542 #define regVPEC_QUEUE4_IB_CNTL                                                                          0x020c
543 #define regVPEC_QUEUE4_IB_CNTL_BASE_IDX                                                                 0
544 #define regVPEC_QUEUE4_IB_RPTR                                                                          0x020d
545 #define regVPEC_QUEUE4_IB_RPTR_BASE_IDX                                                                 0
546 #define regVPEC_QUEUE4_IB_OFFSET                                                                        0x020e
547 #define regVPEC_QUEUE4_IB_OFFSET_BASE_IDX                                                               0
548 #define regVPEC_QUEUE4_IB_BASE_LO                                                                       0x020f
549 #define regVPEC_QUEUE4_IB_BASE_LO_BASE_IDX                                                              0
550 #define regVPEC_QUEUE4_IB_BASE_HI                                                                       0x0210
551 #define regVPEC_QUEUE4_IB_BASE_HI_BASE_IDX                                                              0
552 #define regVPEC_QUEUE4_IB_SIZE                                                                          0x0211
553 #define regVPEC_QUEUE4_IB_SIZE_BASE_IDX                                                                 0
554 #define regVPEC_QUEUE4_CMDIB_CNTL                                                                       0x0212
555 #define regVPEC_QUEUE4_CMDIB_CNTL_BASE_IDX                                                              0
556 #define regVPEC_QUEUE4_CMDIB_RPTR                                                                       0x0213
557 #define regVPEC_QUEUE4_CMDIB_RPTR_BASE_IDX                                                              0
558 #define regVPEC_QUEUE4_CMDIB_OFFSET                                                                     0x0214
559 #define regVPEC_QUEUE4_CMDIB_OFFSET_BASE_IDX                                                            0
560 #define regVPEC_QUEUE4_CMDIB_BASE_LO                                                                    0x0215
561 #define regVPEC_QUEUE4_CMDIB_BASE_LO_BASE_IDX                                                           0
562 #define regVPEC_QUEUE4_CMDIB_BASE_HI                                                                    0x0216
563 #define regVPEC_QUEUE4_CMDIB_BASE_HI_BASE_IDX                                                           0
564 #define regVPEC_QUEUE4_CMDIB_SIZE                                                                       0x0217
565 #define regVPEC_QUEUE4_CMDIB_SIZE_BASE_IDX                                                              0
566 #define regVPEC_QUEUE4_CSA_ADDR_LO                                                                      0x0218
567 #define regVPEC_QUEUE4_CSA_ADDR_LO_BASE_IDX                                                             0
568 #define regVPEC_QUEUE4_CSA_ADDR_HI                                                                      0x0219
569 #define regVPEC_QUEUE4_CSA_ADDR_HI_BASE_IDX                                                             0
570 #define regVPEC_QUEUE4_CONTEXT_STATUS                                                                   0x021a
571 #define regVPEC_QUEUE4_CONTEXT_STATUS_BASE_IDX                                                          0
572 #define regVPEC_QUEUE4_DOORBELL_LOG                                                                     0x021b
573 #define regVPEC_QUEUE4_DOORBELL_LOG_BASE_IDX                                                            0
574 #define regVPEC_QUEUE4_IB_SUB_REMAIN                                                                    0x021c
575 #define regVPEC_QUEUE4_IB_SUB_REMAIN_BASE_IDX                                                           0
576 #define regVPEC_QUEUE4_PREEMPT                                                                          0x021d
577 #define regVPEC_QUEUE4_PREEMPT_BASE_IDX                                                                 0
578 #define regVPEC_QUEUE5_RB_CNTL                                                                          0x0238
579 #define regVPEC_QUEUE5_RB_CNTL_BASE_IDX                                                                 0
580 #define regVPEC_QUEUE5_SCHEDULE_CNTL                                                                    0x0239
581 #define regVPEC_QUEUE5_SCHEDULE_CNTL_BASE_IDX                                                           0
582 #define regVPEC_QUEUE5_RB_BASE                                                                          0x023a
583 #define regVPEC_QUEUE5_RB_BASE_BASE_IDX                                                                 0
584 #define regVPEC_QUEUE5_RB_BASE_HI                                                                       0x023b
585 #define regVPEC_QUEUE5_RB_BASE_HI_BASE_IDX                                                              0
586 #define regVPEC_QUEUE5_RB_RPTR                                                                          0x023c
587 #define regVPEC_QUEUE5_RB_RPTR_BASE_IDX                                                                 0
588 #define regVPEC_QUEUE5_RB_RPTR_HI                                                                       0x023d
589 #define regVPEC_QUEUE5_RB_RPTR_HI_BASE_IDX                                                              0
590 #define regVPEC_QUEUE5_RB_WPTR                                                                          0x023e
591 #define regVPEC_QUEUE5_RB_WPTR_BASE_IDX                                                                 0
592 #define regVPEC_QUEUE5_RB_WPTR_HI                                                                       0x023f
593 #define regVPEC_QUEUE5_RB_WPTR_HI_BASE_IDX                                                              0
594 #define regVPEC_QUEUE5_RB_RPTR_ADDR_HI                                                                  0x0240
595 #define regVPEC_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX                                                         0
596 #define regVPEC_QUEUE5_RB_RPTR_ADDR_LO                                                                  0x0241
597 #define regVPEC_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX                                                         0
598 #define regVPEC_QUEUE5_RB_AQL_CNTL                                                                      0x0242
599 #define regVPEC_QUEUE5_RB_AQL_CNTL_BASE_IDX                                                             0
600 #define regVPEC_QUEUE5_MINOR_PTR_UPDATE                                                                 0x0243
601 #define regVPEC_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX                                                        0
602 #define regVPEC_QUEUE5_CD_INFO                                                                          0x0244
603 #define regVPEC_QUEUE5_CD_INFO_BASE_IDX                                                                 0
604 #define regVPEC_QUEUE5_RB_PREEMPT                                                                       0x0245
605 #define regVPEC_QUEUE5_RB_PREEMPT_BASE_IDX                                                              0
606 #define regVPEC_QUEUE5_SKIP_CNTL                                                                        0x0246
607 #define regVPEC_QUEUE5_SKIP_CNTL_BASE_IDX                                                               0
608 #define regVPEC_QUEUE5_DOORBELL                                                                         0x0247
609 #define regVPEC_QUEUE5_DOORBELL_BASE_IDX                                                                0
610 #define regVPEC_QUEUE5_DOORBELL_OFFSET                                                                  0x0248
611 #define regVPEC_QUEUE5_DOORBELL_OFFSET_BASE_IDX                                                         0
612 #define regVPEC_QUEUE5_DUMMY0                                                                           0x0249
613 #define regVPEC_QUEUE5_DUMMY0_BASE_IDX                                                                  0
614 #define regVPEC_QUEUE5_DUMMY1                                                                           0x024a
615 #define regVPEC_QUEUE5_DUMMY1_BASE_IDX                                                                  0
616 #define regVPEC_QUEUE5_DUMMY2                                                                           0x024b
617 #define regVPEC_QUEUE5_DUMMY2_BASE_IDX                                                                  0
618 #define regVPEC_QUEUE5_DUMMY3                                                                           0x024c
619 #define regVPEC_QUEUE5_DUMMY3_BASE_IDX                                                                  0
620 #define regVPEC_QUEUE5_DUMMY4                                                                           0x024d
621 #define regVPEC_QUEUE5_DUMMY4_BASE_IDX                                                                  0
622 #define regVPEC_QUEUE5_IB_CNTL                                                                          0x0264
623 #define regVPEC_QUEUE5_IB_CNTL_BASE_IDX                                                                 0
624 #define regVPEC_QUEUE5_IB_RPTR                                                                          0x0265
625 #define regVPEC_QUEUE5_IB_RPTR_BASE_IDX                                                                 0
626 #define regVPEC_QUEUE5_IB_OFFSET                                                                        0x0266
627 #define regVPEC_QUEUE5_IB_OFFSET_BASE_IDX                                                               0
628 #define regVPEC_QUEUE5_IB_BASE_LO                                                                       0x0267
629 #define regVPEC_QUEUE5_IB_BASE_LO_BASE_IDX                                                              0
630 #define regVPEC_QUEUE5_IB_BASE_HI                                                                       0x0268
631 #define regVPEC_QUEUE5_IB_BASE_HI_BASE_IDX                                                              0
632 #define regVPEC_QUEUE5_IB_SIZE                                                                          0x0269
633 #define regVPEC_QUEUE5_IB_SIZE_BASE_IDX                                                                 0
634 #define regVPEC_QUEUE5_CMDIB_CNTL                                                                       0x026a
635 #define regVPEC_QUEUE5_CMDIB_CNTL_BASE_IDX                                                              0
636 #define regVPEC_QUEUE5_CMDIB_RPTR                                                                       0x026b
637 #define regVPEC_QUEUE5_CMDIB_RPTR_BASE_IDX                                                              0
638 #define regVPEC_QUEUE5_CMDIB_OFFSET                                                                     0x026c
639 #define regVPEC_QUEUE5_CMDIB_OFFSET_BASE_IDX                                                            0
640 #define regVPEC_QUEUE5_CMDIB_BASE_LO                                                                    0x026d
641 #define regVPEC_QUEUE5_CMDIB_BASE_LO_BASE_IDX                                                           0
642 #define regVPEC_QUEUE5_CMDIB_BASE_HI                                                                    0x026e
643 #define regVPEC_QUEUE5_CMDIB_BASE_HI_BASE_IDX                                                           0
644 #define regVPEC_QUEUE5_CMDIB_SIZE                                                                       0x026f
645 #define regVPEC_QUEUE5_CMDIB_SIZE_BASE_IDX                                                              0
646 #define regVPEC_QUEUE5_CSA_ADDR_LO                                                                      0x0270
647 #define regVPEC_QUEUE5_CSA_ADDR_LO_BASE_IDX                                                             0
648 #define regVPEC_QUEUE5_CSA_ADDR_HI                                                                      0x0271
649 #define regVPEC_QUEUE5_CSA_ADDR_HI_BASE_IDX                                                             0
650 #define regVPEC_QUEUE5_CONTEXT_STATUS                                                                   0x0272
651 #define regVPEC_QUEUE5_CONTEXT_STATUS_BASE_IDX                                                          0
652 #define regVPEC_QUEUE5_DOORBELL_LOG                                                                     0x0273
653 #define regVPEC_QUEUE5_DOORBELL_LOG_BASE_IDX                                                            0
654 #define regVPEC_QUEUE5_IB_SUB_REMAIN                                                                    0x0274
655 #define regVPEC_QUEUE5_IB_SUB_REMAIN_BASE_IDX                                                           0
656 #define regVPEC_QUEUE5_PREEMPT                                                                          0x0275
657 #define regVPEC_QUEUE5_PREEMPT_BASE_IDX                                                                 0
658 #define regVPEC_QUEUE6_RB_CNTL                                                                          0x0290
659 #define regVPEC_QUEUE6_RB_CNTL_BASE_IDX                                                                 0
660 #define regVPEC_QUEUE6_SCHEDULE_CNTL                                                                    0x0291
661 #define regVPEC_QUEUE6_SCHEDULE_CNTL_BASE_IDX                                                           0
662 #define regVPEC_QUEUE6_RB_BASE                                                                          0x0292
663 #define regVPEC_QUEUE6_RB_BASE_BASE_IDX                                                                 0
664 #define regVPEC_QUEUE6_RB_BASE_HI                                                                       0x0293
665 #define regVPEC_QUEUE6_RB_BASE_HI_BASE_IDX                                                              0
666 #define regVPEC_QUEUE6_RB_RPTR                                                                          0x0294
667 #define regVPEC_QUEUE6_RB_RPTR_BASE_IDX                                                                 0
668 #define regVPEC_QUEUE6_RB_RPTR_HI                                                                       0x0295
669 #define regVPEC_QUEUE6_RB_RPTR_HI_BASE_IDX                                                              0
670 #define regVPEC_QUEUE6_RB_WPTR                                                                          0x0296
671 #define regVPEC_QUEUE6_RB_WPTR_BASE_IDX                                                                 0
672 #define regVPEC_QUEUE6_RB_WPTR_HI                                                                       0x0297
673 #define regVPEC_QUEUE6_RB_WPTR_HI_BASE_IDX                                                              0
674 #define regVPEC_QUEUE6_RB_RPTR_ADDR_HI                                                                  0x0298
675 #define regVPEC_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX                                                         0
676 #define regVPEC_QUEUE6_RB_RPTR_ADDR_LO                                                                  0x0299
677 #define regVPEC_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX                                                         0
678 #define regVPEC_QUEUE6_RB_AQL_CNTL                                                                      0x029a
679 #define regVPEC_QUEUE6_RB_AQL_CNTL_BASE_IDX                                                             0
680 #define regVPEC_QUEUE6_MINOR_PTR_UPDATE                                                                 0x029b
681 #define regVPEC_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX                                                        0
682 #define regVPEC_QUEUE6_CD_INFO                                                                          0x029c
683 #define regVPEC_QUEUE6_CD_INFO_BASE_IDX                                                                 0
684 #define regVPEC_QUEUE6_RB_PREEMPT                                                                       0x029d
685 #define regVPEC_QUEUE6_RB_PREEMPT_BASE_IDX                                                              0
686 #define regVPEC_QUEUE6_SKIP_CNTL                                                                        0x029e
687 #define regVPEC_QUEUE6_SKIP_CNTL_BASE_IDX                                                               0
688 #define regVPEC_QUEUE6_DOORBELL                                                                         0x029f
689 #define regVPEC_QUEUE6_DOORBELL_BASE_IDX                                                                0
690 #define regVPEC_QUEUE6_DOORBELL_OFFSET                                                                  0x02a0
691 #define regVPEC_QUEUE6_DOORBELL_OFFSET_BASE_IDX                                                         0
692 #define regVPEC_QUEUE6_DUMMY0                                                                           0x02a1
693 #define regVPEC_QUEUE6_DUMMY0_BASE_IDX                                                                  0
694 #define regVPEC_QUEUE6_DUMMY1                                                                           0x02a2
695 #define regVPEC_QUEUE6_DUMMY1_BASE_IDX                                                                  0
696 #define regVPEC_QUEUE6_DUMMY2                                                                           0x02a3
697 #define regVPEC_QUEUE6_DUMMY2_BASE_IDX                                                                  0
698 #define regVPEC_QUEUE6_DUMMY3                                                                           0x02a4
699 #define regVPEC_QUEUE6_DUMMY3_BASE_IDX                                                                  0
700 #define regVPEC_QUEUE6_DUMMY4                                                                           0x02a5
701 #define regVPEC_QUEUE6_DUMMY4_BASE_IDX                                                                  0
702 #define regVPEC_QUEUE6_IB_CNTL                                                                          0x02bc
703 #define regVPEC_QUEUE6_IB_CNTL_BASE_IDX                                                                 0
704 #define regVPEC_QUEUE6_IB_RPTR                                                                          0x02bd
705 #define regVPEC_QUEUE6_IB_RPTR_BASE_IDX                                                                 0
706 #define regVPEC_QUEUE6_IB_OFFSET                                                                        0x02be
707 #define regVPEC_QUEUE6_IB_OFFSET_BASE_IDX                                                               0
708 #define regVPEC_QUEUE6_IB_BASE_LO                                                                       0x02bf
709 #define regVPEC_QUEUE6_IB_BASE_LO_BASE_IDX                                                              0
710 #define regVPEC_QUEUE6_IB_BASE_HI                                                                       0x02c0
711 #define regVPEC_QUEUE6_IB_BASE_HI_BASE_IDX                                                              0
712 #define regVPEC_QUEUE6_IB_SIZE                                                                          0x02c1
713 #define regVPEC_QUEUE6_IB_SIZE_BASE_IDX                                                                 0
714 #define regVPEC_QUEUE6_CMDIB_CNTL                                                                       0x02c2
715 #define regVPEC_QUEUE6_CMDIB_CNTL_BASE_IDX                                                              0
716 #define regVPEC_QUEUE6_CMDIB_RPTR                                                                       0x02c3
717 #define regVPEC_QUEUE6_CMDIB_RPTR_BASE_IDX                                                              0
718 #define regVPEC_QUEUE6_CMDIB_OFFSET                                                                     0x02c4
719 #define regVPEC_QUEUE6_CMDIB_OFFSET_BASE_IDX                                                            0
720 #define regVPEC_QUEUE6_CMDIB_BASE_LO                                                                    0x02c5
721 #define regVPEC_QUEUE6_CMDIB_BASE_LO_BASE_IDX                                                           0
722 #define regVPEC_QUEUE6_CMDIB_BASE_HI                                                                    0x02c6
723 #define regVPEC_QUEUE6_CMDIB_BASE_HI_BASE_IDX                                                           0
724 #define regVPEC_QUEUE6_CMDIB_SIZE                                                                       0x02c7
725 #define regVPEC_QUEUE6_CMDIB_SIZE_BASE_IDX                                                              0
726 #define regVPEC_QUEUE6_CSA_ADDR_LO                                                                      0x02c8
727 #define regVPEC_QUEUE6_CSA_ADDR_LO_BASE_IDX                                                             0
728 #define regVPEC_QUEUE6_CSA_ADDR_HI                                                                      0x02c9
729 #define regVPEC_QUEUE6_CSA_ADDR_HI_BASE_IDX                                                             0
730 #define regVPEC_QUEUE6_CONTEXT_STATUS                                                                   0x02ca
731 #define regVPEC_QUEUE6_CONTEXT_STATUS_BASE_IDX                                                          0
732 #define regVPEC_QUEUE6_DOORBELL_LOG                                                                     0x02cb
733 #define regVPEC_QUEUE6_DOORBELL_LOG_BASE_IDX                                                            0
734 #define regVPEC_QUEUE6_IB_SUB_REMAIN                                                                    0x02cc
735 #define regVPEC_QUEUE6_IB_SUB_REMAIN_BASE_IDX                                                           0
736 #define regVPEC_QUEUE6_PREEMPT                                                                          0x02cd
737 #define regVPEC_QUEUE6_PREEMPT_BASE_IDX                                                                 0
738 #define regVPEC_QUEUE7_RB_CNTL                                                                          0x02e8
739 #define regVPEC_QUEUE7_RB_CNTL_BASE_IDX                                                                 0
740 #define regVPEC_QUEUE7_SCHEDULE_CNTL                                                                    0x02e9
741 #define regVPEC_QUEUE7_SCHEDULE_CNTL_BASE_IDX                                                           0
742 #define regVPEC_QUEUE7_RB_BASE                                                                          0x02ea
743 #define regVPEC_QUEUE7_RB_BASE_BASE_IDX                                                                 0
744 #define regVPEC_QUEUE7_RB_BASE_HI                                                                       0x02eb
745 #define regVPEC_QUEUE7_RB_BASE_HI_BASE_IDX                                                              0
746 #define regVPEC_QUEUE7_RB_RPTR                                                                          0x02ec
747 #define regVPEC_QUEUE7_RB_RPTR_BASE_IDX                                                                 0
748 #define regVPEC_QUEUE7_RB_RPTR_HI                                                                       0x02ed
749 #define regVPEC_QUEUE7_RB_RPTR_HI_BASE_IDX                                                              0
750 #define regVPEC_QUEUE7_RB_WPTR                                                                          0x02ee
751 #define regVPEC_QUEUE7_RB_WPTR_BASE_IDX                                                                 0
752 #define regVPEC_QUEUE7_RB_WPTR_HI                                                                       0x02ef
753 #define regVPEC_QUEUE7_RB_WPTR_HI_BASE_IDX                                                              0
754 #define regVPEC_QUEUE7_RB_RPTR_ADDR_HI                                                                  0x02f0
755 #define regVPEC_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX                                                         0
756 #define regVPEC_QUEUE7_RB_RPTR_ADDR_LO                                                                  0x02f1
757 #define regVPEC_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX                                                         0
758 #define regVPEC_QUEUE7_RB_AQL_CNTL                                                                      0x02f2
759 #define regVPEC_QUEUE7_RB_AQL_CNTL_BASE_IDX                                                             0
760 #define regVPEC_QUEUE7_MINOR_PTR_UPDATE                                                                 0x02f3
761 #define regVPEC_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX                                                        0
762 #define regVPEC_QUEUE7_CD_INFO                                                                          0x02f4
763 #define regVPEC_QUEUE7_CD_INFO_BASE_IDX                                                                 0
764 #define regVPEC_QUEUE7_RB_PREEMPT                                                                       0x02f5
765 #define regVPEC_QUEUE7_RB_PREEMPT_BASE_IDX                                                              0
766 #define regVPEC_QUEUE7_SKIP_CNTL                                                                        0x02f6
767 #define regVPEC_QUEUE7_SKIP_CNTL_BASE_IDX                                                               0
768 #define regVPEC_QUEUE7_DOORBELL                                                                         0x02f7
769 #define regVPEC_QUEUE7_DOORBELL_BASE_IDX                                                                0
770 #define regVPEC_QUEUE7_DOORBELL_OFFSET                                                                  0x02f8
771 #define regVPEC_QUEUE7_DOORBELL_OFFSET_BASE_IDX                                                         0
772 #define regVPEC_QUEUE7_DUMMY0                                                                           0x02f9
773 #define regVPEC_QUEUE7_DUMMY0_BASE_IDX                                                                  0
774 #define regVPEC_QUEUE7_DUMMY1                                                                           0x02fa
775 #define regVPEC_QUEUE7_DUMMY1_BASE_IDX                                                                  0
776 #define regVPEC_QUEUE7_DUMMY2                                                                           0x02fb
777 #define regVPEC_QUEUE7_DUMMY2_BASE_IDX                                                                  0
778 #define regVPEC_QUEUE7_DUMMY3                                                                           0x02fc
779 #define regVPEC_QUEUE7_DUMMY3_BASE_IDX                                                                  0
780 #define regVPEC_QUEUE7_DUMMY4                                                                           0x02fd
781 #define regVPEC_QUEUE7_DUMMY4_BASE_IDX                                                                  0
782 #define regVPEC_QUEUE7_IB_CNTL                                                                          0x0314
783 #define regVPEC_QUEUE7_IB_CNTL_BASE_IDX                                                                 0
784 #define regVPEC_QUEUE7_IB_RPTR                                                                          0x0315
785 #define regVPEC_QUEUE7_IB_RPTR_BASE_IDX                                                                 0
786 #define regVPEC_QUEUE7_IB_OFFSET                                                                        0x0316
787 #define regVPEC_QUEUE7_IB_OFFSET_BASE_IDX                                                               0
788 #define regVPEC_QUEUE7_IB_BASE_LO                                                                       0x0317
789 #define regVPEC_QUEUE7_IB_BASE_LO_BASE_IDX                                                              0
790 #define regVPEC_QUEUE7_IB_BASE_HI                                                                       0x0318
791 #define regVPEC_QUEUE7_IB_BASE_HI_BASE_IDX                                                              0
792 #define regVPEC_QUEUE7_IB_SIZE                                                                          0x0319
793 #define regVPEC_QUEUE7_IB_SIZE_BASE_IDX                                                                 0
794 #define regVPEC_QUEUE7_CMDIB_CNTL                                                                       0x031a
795 #define regVPEC_QUEUE7_CMDIB_CNTL_BASE_IDX                                                              0
796 #define regVPEC_QUEUE7_CMDIB_RPTR                                                                       0x031b
797 #define regVPEC_QUEUE7_CMDIB_RPTR_BASE_IDX                                                              0
798 #define regVPEC_QUEUE7_CMDIB_OFFSET                                                                     0x031c
799 #define regVPEC_QUEUE7_CMDIB_OFFSET_BASE_IDX                                                            0
800 #define regVPEC_QUEUE7_CMDIB_BASE_LO                                                                    0x031d
801 #define regVPEC_QUEUE7_CMDIB_BASE_LO_BASE_IDX                                                           0
802 #define regVPEC_QUEUE7_CMDIB_BASE_HI                                                                    0x031e
803 #define regVPEC_QUEUE7_CMDIB_BASE_HI_BASE_IDX                                                           0
804 #define regVPEC_QUEUE7_CMDIB_SIZE                                                                       0x031f
805 #define regVPEC_QUEUE7_CMDIB_SIZE_BASE_IDX                                                              0
806 #define regVPEC_QUEUE7_CSA_ADDR_LO                                                                      0x0320
807 #define regVPEC_QUEUE7_CSA_ADDR_LO_BASE_IDX                                                             0
808 #define regVPEC_QUEUE7_CSA_ADDR_HI                                                                      0x0321
809 #define regVPEC_QUEUE7_CSA_ADDR_HI_BASE_IDX                                                             0
810 #define regVPEC_QUEUE7_CONTEXT_STATUS                                                                   0x0322
811 #define regVPEC_QUEUE7_CONTEXT_STATUS_BASE_IDX                                                          0
812 #define regVPEC_QUEUE7_DOORBELL_LOG                                                                     0x0323
813 #define regVPEC_QUEUE7_DOORBELL_LOG_BASE_IDX                                                            0
814 #define regVPEC_QUEUE7_IB_SUB_REMAIN                                                                    0x0324
815 #define regVPEC_QUEUE7_IB_SUB_REMAIN_BASE_IDX                                                           0
816 #define regVPEC_QUEUE7_PREEMPT                                                                          0x0325
817 #define regVPEC_QUEUE7_PREEMPT_BASE_IDX                                                                 0
818 
819 
820 // addressBlock: vpe_vpep_vpdpp0_dispdec_vpcnvc_cfg_dispdec
821 // base address: 0x0
822 #define regVPCNVC_SURFACE_PIXEL_FORMAT                                                                  0x0744
823 #define regVPCNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                         0
824 #define regVPCNVC_FORMAT_CONTROL                                                                        0x0745
825 #define regVPCNVC_FORMAT_CONTROL_BASE_IDX                                                               0
826 #define regVPCNVC_FCNV_FP_BIAS_R                                                                        0x0746
827 #define regVPCNVC_FCNV_FP_BIAS_R_BASE_IDX                                                               0
828 #define regVPCNVC_FCNV_FP_BIAS_G                                                                        0x0747
829 #define regVPCNVC_FCNV_FP_BIAS_G_BASE_IDX                                                               0
830 #define regVPCNVC_FCNV_FP_BIAS_B                                                                        0x0748
831 #define regVPCNVC_FCNV_FP_BIAS_B_BASE_IDX                                                               0
832 #define regVPCNVC_FCNV_FP_SCALE_R                                                                       0x0749
833 #define regVPCNVC_FCNV_FP_SCALE_R_BASE_IDX                                                              0
834 #define regVPCNVC_FCNV_FP_SCALE_G                                                                       0x074a
835 #define regVPCNVC_FCNV_FP_SCALE_G_BASE_IDX                                                              0
836 #define regVPCNVC_FCNV_FP_SCALE_B                                                                       0x074b
837 #define regVPCNVC_FCNV_FP_SCALE_B_BASE_IDX                                                              0
838 #define regVPCNVC_COLOR_KEYER_CONTROL                                                                   0x074c
839 #define regVPCNVC_COLOR_KEYER_CONTROL_BASE_IDX                                                          0
840 #define regVPCNVC_COLOR_KEYER_ALPHA                                                                     0x074d
841 #define regVPCNVC_COLOR_KEYER_ALPHA_BASE_IDX                                                            0
842 #define regVPCNVC_COLOR_KEYER_RED                                                                       0x074e
843 #define regVPCNVC_COLOR_KEYER_RED_BASE_IDX                                                              0
844 #define regVPCNVC_COLOR_KEYER_GREEN                                                                     0x074f
845 #define regVPCNVC_COLOR_KEYER_GREEN_BASE_IDX                                                            0
846 #define regVPCNVC_COLOR_KEYER_BLUE                                                                      0x0750
847 #define regVPCNVC_COLOR_KEYER_BLUE_BASE_IDX                                                             0
848 #define regVPCNVC_ALPHA_2BIT_LUT                                                                        0x0752
849 #define regVPCNVC_ALPHA_2BIT_LUT_BASE_IDX                                                               0
850 #define regVPCNVC_PRE_DEALPHA                                                                           0x0753
851 #define regVPCNVC_PRE_DEALPHA_BASE_IDX                                                                  0
852 #define regVPCNVC_PRE_CSC_MODE                                                                          0x0754
853 #define regVPCNVC_PRE_CSC_MODE_BASE_IDX                                                                 0
854 #define regVPCNVC_PRE_CSC_C11_C12                                                                       0x0755
855 #define regVPCNVC_PRE_CSC_C11_C12_BASE_IDX                                                              0
856 #define regVPCNVC_PRE_CSC_C13_C14                                                                       0x0756
857 #define regVPCNVC_PRE_CSC_C13_C14_BASE_IDX                                                              0
858 #define regVPCNVC_PRE_CSC_C21_C22                                                                       0x0757
859 #define regVPCNVC_PRE_CSC_C21_C22_BASE_IDX                                                              0
860 #define regVPCNVC_PRE_CSC_C23_C24                                                                       0x0758
861 #define regVPCNVC_PRE_CSC_C23_C24_BASE_IDX                                                              0
862 #define regVPCNVC_PRE_CSC_C31_C32                                                                       0x0759
863 #define regVPCNVC_PRE_CSC_C31_C32_BASE_IDX                                                              0
864 #define regVPCNVC_PRE_CSC_C33_C34                                                                       0x075a
865 #define regVPCNVC_PRE_CSC_C33_C34_BASE_IDX                                                              0
866 #define regVPCNVC_COEF_FORMAT                                                                           0x075b
867 #define regVPCNVC_COEF_FORMAT_BASE_IDX                                                                  0
868 #define regVPCNVC_PRE_DEGAM                                                                             0x075c
869 #define regVPCNVC_PRE_DEGAM_BASE_IDX                                                                    0
870 #define regVPCNVC_PRE_REALPHA                                                                           0x075d
871 #define regVPCNVC_PRE_REALPHA_BASE_IDX                                                                  0
872 
873 
874 // addressBlock: vpe_vpep_vpdpp0_dispdec_vpdscl_dispdec
875 // base address: 0x0
876 #define regVPDSCL_COEF_RAM_TAP_SELECT                                                                   0x0768
877 #define regVPDSCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                          0
878 #define regVPDSCL_COEF_RAM_TAP_DATA                                                                     0x0769
879 #define regVPDSCL_COEF_RAM_TAP_DATA_BASE_IDX                                                            0
880 #define regVPDSCL_MODE                                                                                  0x076a
881 #define regVPDSCL_MODE_BASE_IDX                                                                         0
882 #define regVPDSCL_TAP_CONTROL                                                                           0x076b
883 #define regVPDSCL_TAP_CONTROL_BASE_IDX                                                                  0
884 #define regVPDSCL_CONTROL                                                                               0x076c
885 #define regVPDSCL_CONTROL_BASE_IDX                                                                      0
886 #define regVPDSCL_2TAP_CONTROL                                                                          0x076d
887 #define regVPDSCL_2TAP_CONTROL_BASE_IDX                                                                 0
888 #define regVPDSCL_MANUAL_REPLICATE_CONTROL                                                              0x076e
889 #define regVPDSCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                     0
890 #define regVPDSCL_HORZ_FILTER_SCALE_RATIO                                                               0x076f
891 #define regVPDSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                      0
892 #define regVPDSCL_HORZ_FILTER_INIT                                                                      0x0770
893 #define regVPDSCL_HORZ_FILTER_INIT_BASE_IDX                                                             0
894 #define regVPDSCL_HORZ_FILTER_SCALE_RATIO_C                                                             0x0771
895 #define regVPDSCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                    0
896 #define regVPDSCL_HORZ_FILTER_INIT_C                                                                    0x0772
897 #define regVPDSCL_HORZ_FILTER_INIT_C_BASE_IDX                                                           0
898 #define regVPDSCL_VERT_FILTER_SCALE_RATIO                                                               0x0773
899 #define regVPDSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                      0
900 #define regVPDSCL_VERT_FILTER_INIT                                                                      0x0774
901 #define regVPDSCL_VERT_FILTER_INIT_BASE_IDX                                                             0
902 #define regVPDSCL_VERT_FILTER_INIT_BOT                                                                  0x0775
903 #define regVPDSCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                         0
904 #define regVPDSCL_VERT_FILTER_SCALE_RATIO_C                                                             0x0776
905 #define regVPDSCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                    0
906 #define regVPDSCL_VERT_FILTER_INIT_C                                                                    0x0777
907 #define regVPDSCL_VERT_FILTER_INIT_C_BASE_IDX                                                           0
908 #define regVPDSCL_VERT_FILTER_INIT_BOT_C                                                                0x0778
909 #define regVPDSCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                       0
910 #define regVPDSCL_BLACK_COLOR                                                                           0x0779
911 #define regVPDSCL_BLACK_COLOR_BASE_IDX                                                                  0
912 #define regVPDSCL_UPDATE                                                                                0x077a
913 #define regVPDSCL_UPDATE_BASE_IDX                                                                       0
914 #define regVPDSCL_AUTOCAL                                                                               0x077b
915 #define regVPDSCL_AUTOCAL_BASE_IDX                                                                      0
916 #define regVPDSCL_EXT_OVERSCAN_LEFT_RIGHT                                                               0x077c
917 #define regVPDSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                      0
918 #define regVPDSCL_EXT_OVERSCAN_TOP_BOTTOM                                                               0x077d
919 #define regVPDSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                      0
920 #define regVPOTG_H_BLANK                                                                                0x077e
921 #define regVPOTG_H_BLANK_BASE_IDX                                                                       0
922 #define regVPOTG_V_BLANK                                                                                0x077f
923 #define regVPOTG_V_BLANK_BASE_IDX                                                                       0
924 #define regVPDSCL_RECOUT_START                                                                          0x0780
925 #define regVPDSCL_RECOUT_START_BASE_IDX                                                                 0
926 #define regVPDSCL_RECOUT_SIZE                                                                           0x0781
927 #define regVPDSCL_RECOUT_SIZE_BASE_IDX                                                                  0
928 #define regVPMPC_SIZE                                                                                   0x0782
929 #define regVPMPC_SIZE_BASE_IDX                                                                          0
930 #define regVPLB_DATA_FORMAT                                                                             0x0783
931 #define regVPLB_DATA_FORMAT_BASE_IDX                                                                    0
932 #define regVPLB_MEMORY_CTRL                                                                             0x0784
933 #define regVPLB_MEMORY_CTRL_BASE_IDX                                                                    0
934 #define regVPLB_V_COUNTER                                                                               0x0785
935 #define regVPLB_V_COUNTER_BASE_IDX                                                                      0
936 #define regVPDSCL_MEM_PWR_CTRL                                                                          0x0786
937 #define regVPDSCL_MEM_PWR_CTRL_BASE_IDX                                                                 0
938 #define regVPDSCL_MEM_PWR_STATUS                                                                        0x0787
939 #define regVPDSCL_MEM_PWR_STATUS_BASE_IDX                                                               0
940 
941 
942 // addressBlock: vpe_vpep_vpdpp0_dispdec_vpcm_dispdec
943 // base address: 0x0
944 #define regVPCM_CONTROL                                                                                 0x07b8
945 #define regVPCM_CONTROL_BASE_IDX                                                                        0
946 #define regVPCM_POST_CSC_CONTROL                                                                        0x07b9
947 #define regVPCM_POST_CSC_CONTROL_BASE_IDX                                                               0
948 #define regVPCM_POST_CSC_C11_C12                                                                        0x07ba
949 #define regVPCM_POST_CSC_C11_C12_BASE_IDX                                                               0
950 #define regVPCM_POST_CSC_C13_C14                                                                        0x07bb
951 #define regVPCM_POST_CSC_C13_C14_BASE_IDX                                                               0
952 #define regVPCM_POST_CSC_C21_C22                                                                        0x07bc
953 #define regVPCM_POST_CSC_C21_C22_BASE_IDX                                                               0
954 #define regVPCM_POST_CSC_C23_C24                                                                        0x07bd
955 #define regVPCM_POST_CSC_C23_C24_BASE_IDX                                                               0
956 #define regVPCM_POST_CSC_C31_C32                                                                        0x07be
957 #define regVPCM_POST_CSC_C31_C32_BASE_IDX                                                               0
958 #define regVPCM_POST_CSC_C33_C34                                                                        0x07bf
959 #define regVPCM_POST_CSC_C33_C34_BASE_IDX                                                               0
960 #define regVPCM_GAMUT_REMAP_CONTROL                                                                     0x07c0
961 #define regVPCM_GAMUT_REMAP_CONTROL_BASE_IDX                                                            0
962 #define regVPCM_GAMUT_REMAP_C11_C12                                                                     0x07c1
963 #define regVPCM_GAMUT_REMAP_C11_C12_BASE_IDX                                                            0
964 #define regVPCM_GAMUT_REMAP_C13_C14                                                                     0x07c2
965 #define regVPCM_GAMUT_REMAP_C13_C14_BASE_IDX                                                            0
966 #define regVPCM_GAMUT_REMAP_C21_C22                                                                     0x07c3
967 #define regVPCM_GAMUT_REMAP_C21_C22_BASE_IDX                                                            0
968 #define regVPCM_GAMUT_REMAP_C23_C24                                                                     0x07c4
969 #define regVPCM_GAMUT_REMAP_C23_C24_BASE_IDX                                                            0
970 #define regVPCM_GAMUT_REMAP_C31_C32                                                                     0x07c5
971 #define regVPCM_GAMUT_REMAP_C31_C32_BASE_IDX                                                            0
972 #define regVPCM_GAMUT_REMAP_C33_C34                                                                     0x07c6
973 #define regVPCM_GAMUT_REMAP_C33_C34_BASE_IDX                                                            0
974 #define regVPCM_BIAS_CR_R                                                                               0x07c7
975 #define regVPCM_BIAS_CR_R_BASE_IDX                                                                      0
976 #define regVPCM_BIAS_Y_G_CB_B                                                                           0x07c8
977 #define regVPCM_BIAS_Y_G_CB_B_BASE_IDX                                                                  0
978 #define regVPCM_GAMCOR_CONTROL                                                                          0x07c9
979 #define regVPCM_GAMCOR_CONTROL_BASE_IDX                                                                 0
980 #define regVPCM_GAMCOR_LUT_INDEX                                                                        0x07ca
981 #define regVPCM_GAMCOR_LUT_INDEX_BASE_IDX                                                               0
982 #define regVPCM_GAMCOR_LUT_DATA                                                                         0x07cb
983 #define regVPCM_GAMCOR_LUT_DATA_BASE_IDX                                                                0
984 #define regVPCM_GAMCOR_LUT_CONTROL                                                                      0x07cc
985 #define regVPCM_GAMCOR_LUT_CONTROL_BASE_IDX                                                             0
986 #define regVPCM_GAMCOR_RAMA_START_CNTL_B                                                                0x07cd
987 #define regVPCM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                       0
988 #define regVPCM_GAMCOR_RAMA_START_CNTL_G                                                                0x07ce
989 #define regVPCM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                       0
990 #define regVPCM_GAMCOR_RAMA_START_CNTL_R                                                                0x07cf
991 #define regVPCM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                       0
992 #define regVPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                          0x07d0
993 #define regVPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                                 0
994 #define regVPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                          0x07d1
995 #define regVPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                                 0
996 #define regVPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                          0x07d2
997 #define regVPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                                 0
998 #define regVPCM_GAMCOR_RAMA_START_BASE_CNTL_B                                                           0x07d3
999 #define regVPCM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                  0
1000 #define regVPCM_GAMCOR_RAMA_START_BASE_CNTL_G                                                           0x07d4
1001 #define regVPCM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                  0
1002 #define regVPCM_GAMCOR_RAMA_START_BASE_CNTL_R                                                           0x07d5
1003 #define regVPCM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                  0
1004 #define regVPCM_GAMCOR_RAMA_END_CNTL1_B                                                                 0x07d6
1005 #define regVPCM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                        0
1006 #define regVPCM_GAMCOR_RAMA_END_CNTL2_B                                                                 0x07d7
1007 #define regVPCM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                        0
1008 #define regVPCM_GAMCOR_RAMA_END_CNTL1_G                                                                 0x07d8
1009 #define regVPCM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                        0
1010 #define regVPCM_GAMCOR_RAMA_END_CNTL2_G                                                                 0x07d9
1011 #define regVPCM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                        0
1012 #define regVPCM_GAMCOR_RAMA_END_CNTL1_R                                                                 0x07da
1013 #define regVPCM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                        0
1014 #define regVPCM_GAMCOR_RAMA_END_CNTL2_R                                                                 0x07db
1015 #define regVPCM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                        0
1016 #define regVPCM_GAMCOR_RAMA_OFFSET_B                                                                    0x07dc
1017 #define regVPCM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                           0
1018 #define regVPCM_GAMCOR_RAMA_OFFSET_G                                                                    0x07dd
1019 #define regVPCM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                           0
1020 #define regVPCM_GAMCOR_RAMA_OFFSET_R                                                                    0x07de
1021 #define regVPCM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                           0
1022 #define regVPCM_GAMCOR_RAMA_REGION_0_1                                                                  0x07df
1023 #define regVPCM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                         0
1024 #define regVPCM_GAMCOR_RAMA_REGION_2_3                                                                  0x07e0
1025 #define regVPCM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                         0
1026 #define regVPCM_GAMCOR_RAMA_REGION_4_5                                                                  0x07e1
1027 #define regVPCM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                         0
1028 #define regVPCM_GAMCOR_RAMA_REGION_6_7                                                                  0x07e2
1029 #define regVPCM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                         0
1030 #define regVPCM_GAMCOR_RAMA_REGION_8_9                                                                  0x07e3
1031 #define regVPCM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                         0
1032 #define regVPCM_GAMCOR_RAMA_REGION_10_11                                                                0x07e4
1033 #define regVPCM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                       0
1034 #define regVPCM_GAMCOR_RAMA_REGION_12_13                                                                0x07e5
1035 #define regVPCM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                       0
1036 #define regVPCM_GAMCOR_RAMA_REGION_14_15                                                                0x07e6
1037 #define regVPCM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                       0
1038 #define regVPCM_GAMCOR_RAMA_REGION_16_17                                                                0x07e7
1039 #define regVPCM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                       0
1040 #define regVPCM_GAMCOR_RAMA_REGION_18_19                                                                0x07e8
1041 #define regVPCM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                       0
1042 #define regVPCM_GAMCOR_RAMA_REGION_20_21                                                                0x07e9
1043 #define regVPCM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                       0
1044 #define regVPCM_GAMCOR_RAMA_REGION_22_23                                                                0x07ea
1045 #define regVPCM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                       0
1046 #define regVPCM_GAMCOR_RAMA_REGION_24_25                                                                0x07eb
1047 #define regVPCM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                       0
1048 #define regVPCM_GAMCOR_RAMA_REGION_26_27                                                                0x07ec
1049 #define regVPCM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                       0
1050 #define regVPCM_GAMCOR_RAMA_REGION_28_29                                                                0x07ed
1051 #define regVPCM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                       0
1052 #define regVPCM_GAMCOR_RAMA_REGION_30_31                                                                0x07ee
1053 #define regVPCM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                       0
1054 #define regVPCM_GAMCOR_RAMA_REGION_32_33                                                                0x07ef
1055 #define regVPCM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                       0
1056 #define regVPCM_HDR_MULT_COEF                                                                           0x07f0
1057 #define regVPCM_HDR_MULT_COEF_BASE_IDX                                                                  0
1058 #define regVPCM_MEM_PWR_CTRL                                                                            0x07f1
1059 #define regVPCM_MEM_PWR_CTRL_BASE_IDX                                                                   0
1060 #define regVPCM_MEM_PWR_STATUS                                                                          0x07f2
1061 #define regVPCM_MEM_PWR_STATUS_BASE_IDX                                                                 0
1062 #define regVPCM_DEALPHA                                                                                 0x07f4
1063 #define regVPCM_DEALPHA_BASE_IDX                                                                        0
1064 #define regVPCM_COEF_FORMAT                                                                             0x07f5
1065 #define regVPCM_COEF_FORMAT_BASE_IDX                                                                    0
1066 #define regVPCM_TEST_DEBUG_INDEX                                                                        0x07f6
1067 #define regVPCM_TEST_DEBUG_INDEX_BASE_IDX                                                               0
1068 #define regVPCM_TEST_DEBUG_DATA                                                                         0x07f7
1069 #define regVPCM_TEST_DEBUG_DATA_BASE_IDX                                                                0
1070 
1071 
1072 // addressBlock: vpe_vpep_vpdpp0_dispdec_vpdpp_top_dispdec
1073 // base address: 0x0
1074 #define regVPDPP_CONTROL                                                                                0x0738
1075 #define regVPDPP_CONTROL_BASE_IDX                                                                       0
1076 #define regVPDPP_SOFT_RESET                                                                             0x0739
1077 #define regVPDPP_SOFT_RESET_BASE_IDX                                                                    0
1078 #define regVPDPP_CRC_VAL_R_G                                                                            0x073a
1079 #define regVPDPP_CRC_VAL_R_G_BASE_IDX                                                                   0
1080 #define regVPDPP_CRC_VAL_B_A                                                                            0x073b
1081 #define regVPDPP_CRC_VAL_B_A_BASE_IDX                                                                   0
1082 #define regVPDPP_CRC_CTRL                                                                               0x073c
1083 #define regVPDPP_CRC_CTRL_BASE_IDX                                                                      0
1084 #define regVPHOST_READ_CONTROL                                                                          0x073d
1085 #define regVPHOST_READ_CONTROL_BASE_IDX                                                                 0
1086 
1087 
1088 // addressBlock: vpe_vpep_vpmpc_vpmpcc0_dispdec
1089 // base address: 0x0
1090 #define regVPMPCC_TOP_SEL                                                                               0x0dc0
1091 #define regVPMPCC_TOP_SEL_BASE_IDX                                                                      0
1092 #define regVPMPCC_BOT_SEL                                                                               0x0dc1
1093 #define regVPMPCC_BOT_SEL_BASE_IDX                                                                      0
1094 #define regVPMPCC_VPOPP_ID                                                                              0x0dc2
1095 #define regVPMPCC_VPOPP_ID_BASE_IDX                                                                     0
1096 #define regVPMPCC_CONTROL                                                                               0x0dc3
1097 #define regVPMPCC_CONTROL_BASE_IDX                                                                      0
1098 #define regVPMPCC_TOP_GAIN                                                                              0x0dc4
1099 #define regVPMPCC_TOP_GAIN_BASE_IDX                                                                     0
1100 #define regVPMPCC_BOT_GAIN_INSIDE                                                                       0x0dc5
1101 #define regVPMPCC_BOT_GAIN_INSIDE_BASE_IDX                                                              0
1102 #define regVPMPCC_BOT_GAIN_OUTSIDE                                                                      0x0dc6
1103 #define regVPMPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                             0
1104 #define regVPMPCC_MOVABLE_CM_LOCATION_CONTROL                                                           0x0dc7
1105 #define regVPMPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                                  0
1106 #define regVPMPCC_BG_R_CR                                                                               0x0dc8
1107 #define regVPMPCC_BG_R_CR_BASE_IDX                                                                      0
1108 #define regVPMPCC_BG_G_Y                                                                                0x0dc9
1109 #define regVPMPCC_BG_G_Y_BASE_IDX                                                                       0
1110 #define regVPMPCC_BG_B_CB                                                                               0x0dca
1111 #define regVPMPCC_BG_B_CB_BASE_IDX                                                                      0
1112 #define regVPMPCC_MEM_PWR_CTRL                                                                          0x0dcb
1113 #define regVPMPCC_MEM_PWR_CTRL_BASE_IDX                                                                 0
1114 #define regVPMPCC_STATUS                                                                                0x0dcc
1115 #define regVPMPCC_STATUS_BASE_IDX                                                                       0
1116 
1117 
1118 // addressBlock: vpe_vpep_vpmpc_vpmpc_cfg_dispdec
1119 // base address: 0x0
1120 #define regVPMPC_CLOCK_CONTROL                                                                          0x0f8c
1121 #define regVPMPC_CLOCK_CONTROL_BASE_IDX                                                                 0
1122 #define regVPMPC_SOFT_RESET                                                                             0x0f8d
1123 #define regVPMPC_SOFT_RESET_BASE_IDX                                                                    0
1124 #define regVPMPC_CRC_CTRL                                                                               0x0f8e
1125 #define regVPMPC_CRC_CTRL_BASE_IDX                                                                      0
1126 #define regVPMPC_CRC_SEL_CONTROL                                                                        0x0f8f
1127 #define regVPMPC_CRC_SEL_CONTROL_BASE_IDX                                                               0
1128 #define regVPMPC_CRC_RESULT_AR                                                                          0x0f90
1129 #define regVPMPC_CRC_RESULT_AR_BASE_IDX                                                                 0
1130 #define regVPMPC_CRC_RESULT_GB                                                                          0x0f91
1131 #define regVPMPC_CRC_RESULT_GB_BASE_IDX                                                                 0
1132 #define regVPMPC_CRC_RESULT_C                                                                           0x0f92
1133 #define regVPMPC_CRC_RESULT_C_BASE_IDX                                                                  0
1134 #define regVPMPC_BYPASS_BG_AR                                                                           0x0f95
1135 #define regVPMPC_BYPASS_BG_AR_BASE_IDX                                                                  0
1136 #define regVPMPC_BYPASS_BG_GB                                                                           0x0f96
1137 #define regVPMPC_BYPASS_BG_GB_BASE_IDX                                                                  0
1138 #define regVPMPC_HOST_READ_CONTROL                                                                      0x0f97
1139 #define regVPMPC_HOST_READ_CONTROL_BASE_IDX                                                             0
1140 #define regVPMPC_PENDING_STATUS_MISC                                                                    0x0f98
1141 #define regVPMPC_PENDING_STATUS_MISC_BASE_IDX                                                           0
1142 
1143 
1144 // addressBlock: vpe_vpep_vpmpc_vpmpcc_ogam0_dispdec
1145 // base address: 0x0
1146 #define regVPMPCC_OGAM_CONTROL                                                                          0x0e14
1147 #define regVPMPCC_OGAM_CONTROL_BASE_IDX                                                                 0
1148 #define regVPMPCC_OGAM_LUT_INDEX                                                                        0x0e15
1149 #define regVPMPCC_OGAM_LUT_INDEX_BASE_IDX                                                               0
1150 #define regVPMPCC_OGAM_LUT_DATA                                                                         0x0e16
1151 #define regVPMPCC_OGAM_LUT_DATA_BASE_IDX                                                                0
1152 #define regVPMPCC_OGAM_LUT_CONTROL                                                                      0x0e17
1153 #define regVPMPCC_OGAM_LUT_CONTROL_BASE_IDX                                                             0
1154 #define regVPMPCC_OGAM_RAMA_START_CNTL_B                                                                0x0e18
1155 #define regVPMPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                                       0
1156 #define regVPMPCC_OGAM_RAMA_START_CNTL_G                                                                0x0e19
1157 #define regVPMPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                                       0
1158 #define regVPMPCC_OGAM_RAMA_START_CNTL_R                                                                0x0e1a
1159 #define regVPMPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                                       0
1160 #define regVPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                          0x0e1b
1161 #define regVPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                                 0
1162 #define regVPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                          0x0e1c
1163 #define regVPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                                 0
1164 #define regVPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                          0x0e1d
1165 #define regVPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                                 0
1166 #define regVPMPCC_OGAM_RAMA_START_BASE_CNTL_B                                                           0x0e1e
1167 #define regVPMPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                                  0
1168 #define regVPMPCC_OGAM_RAMA_START_BASE_CNTL_G                                                           0x0e1f
1169 #define regVPMPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                                  0
1170 #define regVPMPCC_OGAM_RAMA_START_BASE_CNTL_R                                                           0x0e20
1171 #define regVPMPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                                  0
1172 #define regVPMPCC_OGAM_RAMA_END_CNTL1_B                                                                 0x0e21
1173 #define regVPMPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                                        0
1174 #define regVPMPCC_OGAM_RAMA_END_CNTL2_B                                                                 0x0e22
1175 #define regVPMPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                                        0
1176 #define regVPMPCC_OGAM_RAMA_END_CNTL1_G                                                                 0x0e23
1177 #define regVPMPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                                        0
1178 #define regVPMPCC_OGAM_RAMA_END_CNTL2_G                                                                 0x0e24
1179 #define regVPMPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                                        0
1180 #define regVPMPCC_OGAM_RAMA_END_CNTL1_R                                                                 0x0e25
1181 #define regVPMPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                                        0
1182 #define regVPMPCC_OGAM_RAMA_END_CNTL2_R                                                                 0x0e26
1183 #define regVPMPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                                        0
1184 #define regVPMPCC_OGAM_RAMA_OFFSET_B                                                                    0x0e27
1185 #define regVPMPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                           0
1186 #define regVPMPCC_OGAM_RAMA_OFFSET_G                                                                    0x0e28
1187 #define regVPMPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                           0
1188 #define regVPMPCC_OGAM_RAMA_OFFSET_R                                                                    0x0e29
1189 #define regVPMPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                           0
1190 #define regVPMPCC_OGAM_RAMA_REGION_0_1                                                                  0x0e2a
1191 #define regVPMPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                         0
1192 #define regVPMPCC_OGAM_RAMA_REGION_2_3                                                                  0x0e2b
1193 #define regVPMPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                         0
1194 #define regVPMPCC_OGAM_RAMA_REGION_4_5                                                                  0x0e2c
1195 #define regVPMPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                         0
1196 #define regVPMPCC_OGAM_RAMA_REGION_6_7                                                                  0x0e2d
1197 #define regVPMPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                         0
1198 #define regVPMPCC_OGAM_RAMA_REGION_8_9                                                                  0x0e2e
1199 #define regVPMPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                         0
1200 #define regVPMPCC_OGAM_RAMA_REGION_10_11                                                                0x0e2f
1201 #define regVPMPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                                       0
1202 #define regVPMPCC_OGAM_RAMA_REGION_12_13                                                                0x0e30
1203 #define regVPMPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                                       0
1204 #define regVPMPCC_OGAM_RAMA_REGION_14_15                                                                0x0e31
1205 #define regVPMPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                                       0
1206 #define regVPMPCC_OGAM_RAMA_REGION_16_17                                                                0x0e32
1207 #define regVPMPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                                       0
1208 #define regVPMPCC_OGAM_RAMA_REGION_18_19                                                                0x0e33
1209 #define regVPMPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                                       0
1210 #define regVPMPCC_OGAM_RAMA_REGION_20_21                                                                0x0e34
1211 #define regVPMPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                                       0
1212 #define regVPMPCC_OGAM_RAMA_REGION_22_23                                                                0x0e35
1213 #define regVPMPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                                       0
1214 #define regVPMPCC_OGAM_RAMA_REGION_24_25                                                                0x0e36
1215 #define regVPMPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                                       0
1216 #define regVPMPCC_OGAM_RAMA_REGION_26_27                                                                0x0e37
1217 #define regVPMPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                                       0
1218 #define regVPMPCC_OGAM_RAMA_REGION_28_29                                                                0x0e38
1219 #define regVPMPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                                       0
1220 #define regVPMPCC_OGAM_RAMA_REGION_30_31                                                                0x0e39
1221 #define regVPMPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                                       0
1222 #define regVPMPCC_OGAM_RAMA_REGION_32_33                                                                0x0e3a
1223 #define regVPMPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                                       0
1224 #define regVPMPCC_GAMUT_REMAP_COEF_FORMAT                                                               0x0e3b
1225 #define regVPMPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                                      0
1226 #define regVPMPCC_GAMUT_REMAP_MODE                                                                      0x0e3c
1227 #define regVPMPCC_GAMUT_REMAP_MODE_BASE_IDX                                                             0
1228 #define regVPMPC_GAMUT_REMAP_C11_C12_A                                                                  0x0e3d
1229 #define regVPMPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                         0
1230 #define regVPMPC_GAMUT_REMAP_C13_C14_A                                                                  0x0e3e
1231 #define regVPMPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                         0
1232 #define regVPMPC_GAMUT_REMAP_C21_C22_A                                                                  0x0e3f
1233 #define regVPMPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                         0
1234 #define regVPMPC_GAMUT_REMAP_C23_C24_A                                                                  0x0e40
1235 #define regVPMPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                         0
1236 #define regVPMPC_GAMUT_REMAP_C31_C32_A                                                                  0x0e41
1237 #define regVPMPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                         0
1238 #define regVPMPC_GAMUT_REMAP_C33_C34_A                                                                  0x0e42
1239 #define regVPMPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                         0
1240 
1241 
1242 // addressBlock: vpe_vpep_vpmpc_vpmpcc_mcm0_dispdec
1243 // base address: 0x0
1244 #define regVPMPCC_MCM_SHAPER_CONTROL                                                                    0x1059
1245 #define regVPMPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                           0
1246 #define regVPMPCC_MCM_SHAPER_OFFSET_R                                                                   0x105a
1247 #define regVPMPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                          0
1248 #define regVPMPCC_MCM_SHAPER_OFFSET_G                                                                   0x105b
1249 #define regVPMPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                          0
1250 #define regVPMPCC_MCM_SHAPER_OFFSET_B                                                                   0x105c
1251 #define regVPMPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                          0
1252 #define regVPMPCC_MCM_SHAPER_SCALE_R                                                                    0x105d
1253 #define regVPMPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                           0
1254 #define regVPMPCC_MCM_SHAPER_SCALE_G_B                                                                  0x105e
1255 #define regVPMPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                         0
1256 #define regVPMPCC_MCM_SHAPER_LUT_INDEX                                                                  0x105f
1257 #define regVPMPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                         0
1258 #define regVPMPCC_MCM_SHAPER_LUT_DATA                                                                   0x1060
1259 #define regVPMPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                          0
1260 #define regVPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                          0x1061
1261 #define regVPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                 0
1262 #define regVPMPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                          0x1062
1263 #define regVPMPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                 0
1264 #define regVPMPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                          0x1063
1265 #define regVPMPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                 0
1266 #define regVPMPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                          0x1064
1267 #define regVPMPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                 0
1268 #define regVPMPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                            0x1065
1269 #define regVPMPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                   0
1270 #define regVPMPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                            0x1066
1271 #define regVPMPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                   0
1272 #define regVPMPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                            0x1067
1273 #define regVPMPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                   0
1274 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_0_1                                                            0x1068
1275 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                   0
1276 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_2_3                                                            0x1069
1277 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                   0
1278 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_4_5                                                            0x106a
1279 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                   0
1280 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_6_7                                                            0x106b
1281 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                   0
1282 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_8_9                                                            0x106c
1283 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                   0
1284 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_10_11                                                          0x106d
1285 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                 0
1286 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_12_13                                                          0x106e
1287 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                 0
1288 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_14_15                                                          0x106f
1289 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                 0
1290 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_16_17                                                          0x1070
1291 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                 0
1292 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_18_19                                                          0x1071
1293 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                 0
1294 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_20_21                                                          0x1072
1295 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                 0
1296 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_22_23                                                          0x1073
1297 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                 0
1298 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_24_25                                                          0x1074
1299 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                 0
1300 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_26_27                                                          0x1075
1301 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                 0
1302 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_28_29                                                          0x1076
1303 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                 0
1304 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_30_31                                                          0x1077
1305 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                 0
1306 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_32_33                                                          0x1078
1307 #define regVPMPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                 0
1308 #define regVPMPCC_MCM_3DLUT_MODE                                                                        0x1079
1309 #define regVPMPCC_MCM_3DLUT_MODE_BASE_IDX                                                               0
1310 #define regVPMPCC_MCM_3DLUT_INDEX                                                                       0x107a
1311 #define regVPMPCC_MCM_3DLUT_INDEX_BASE_IDX                                                              0
1312 #define regVPMPCC_MCM_3DLUT_DATA                                                                        0x107b
1313 #define regVPMPCC_MCM_3DLUT_DATA_BASE_IDX                                                               0
1314 #define regVPMPCC_MCM_3DLUT_DATA_30BIT                                                                  0x107c
1315 #define regVPMPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                         0
1316 #define regVPMPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                          0x107d
1317 #define regVPMPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                 0
1318 #define regVPMPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                             0x107e
1319 #define regVPMPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                    0
1320 #define regVPMPCC_MCM_3DLUT_OUT_OFFSET_R                                                                0x107f
1321 #define regVPMPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                       0
1322 #define regVPMPCC_MCM_3DLUT_OUT_OFFSET_G                                                                0x1080
1323 #define regVPMPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                       0
1324 #define regVPMPCC_MCM_3DLUT_OUT_OFFSET_B                                                                0x1081
1325 #define regVPMPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                       0
1326 #define regVPMPCC_MCM_1DLUT_CONTROL                                                                     0x1082
1327 #define regVPMPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                            0
1328 #define regVPMPCC_MCM_1DLUT_LUT_INDEX                                                                   0x1083
1329 #define regVPMPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                          0
1330 #define regVPMPCC_MCM_1DLUT_LUT_DATA                                                                    0x1084
1331 #define regVPMPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                           0
1332 #define regVPMPCC_MCM_1DLUT_LUT_CONTROL                                                                 0x1085
1333 #define regVPMPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                        0
1334 #define regVPMPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                           0x1086
1335 #define regVPMPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                                  0
1336 #define regVPMPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                           0x1087
1337 #define regVPMPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                                  0
1338 #define regVPMPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                           0x1088
1339 #define regVPMPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                                  0
1340 #define regVPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                                     0x1089
1341 #define regVPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                            0
1342 #define regVPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                                     0x108a
1343 #define regVPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                            0
1344 #define regVPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                                     0x108b
1345 #define regVPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                            0
1346 #define regVPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                                      0x108c
1347 #define regVPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                             0
1348 #define regVPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                                      0x108d
1349 #define regVPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                             0
1350 #define regVPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                                      0x108e
1351 #define regVPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                             0
1352 #define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                            0x108f
1353 #define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                                   0
1354 #define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                            0x1090
1355 #define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                                   0
1356 #define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                            0x1091
1357 #define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                                   0
1358 #define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                            0x1092
1359 #define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                                   0
1360 #define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                            0x1093
1361 #define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                                   0
1362 #define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                            0x1094
1363 #define regVPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                                   0
1364 #define regVPMPCC_MCM_1DLUT_RAMA_OFFSET_B                                                               0x1095
1365 #define regVPMPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                                      0
1366 #define regVPMPCC_MCM_1DLUT_RAMA_OFFSET_G                                                               0x1096
1367 #define regVPMPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                                      0
1368 #define regVPMPCC_MCM_1DLUT_RAMA_OFFSET_R                                                               0x1097
1369 #define regVPMPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                                      0
1370 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_0_1                                                             0x1098
1371 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                                    0
1372 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_2_3                                                             0x1099
1373 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                                    0
1374 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_4_5                                                             0x109a
1375 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                                    0
1376 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_6_7                                                             0x109b
1377 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                                    0
1378 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_8_9                                                             0x109c
1379 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                                    0
1380 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_10_11                                                           0x109d
1381 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                                  0
1382 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_12_13                                                           0x109e
1383 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                                  0
1384 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_14_15                                                           0x109f
1385 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                                  0
1386 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_16_17                                                           0x10a0
1387 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                                  0
1388 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_18_19                                                           0x10a1
1389 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                                  0
1390 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_20_21                                                           0x10a2
1391 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                                  0
1392 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_22_23                                                           0x10a3
1393 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                                  0
1394 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_24_25                                                           0x10a4
1395 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                                  0
1396 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_26_27                                                           0x10a5
1397 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                                  0
1398 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_28_29                                                           0x10a6
1399 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                                  0
1400 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_30_31                                                           0x10a7
1401 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                                  0
1402 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_32_33                                                           0x10a8
1403 #define regVPMPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                                  0
1404 #define regVPMPCC_MCM_MEM_PWR_CTRL                                                                      0x10a9
1405 #define regVPMPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                             0
1406 #define regVPMPCC_MCM_TEST_DEBUG_INDEX                                                                  0x10ab
1407 #define regVPMPCC_MCM_TEST_DEBUG_INDEX_BASE_IDX                                                         0
1408 #define regVPMPCC_MCM_TEST_DEBUG_DATA                                                                   0x10ac
1409 #define regVPMPCC_MCM_TEST_DEBUG_DATA_BASE_IDX                                                          0
1410 
1411 
1412 // addressBlock: vpe_vpep_vpmpc_vpmpc_ocsc_dispdec
1413 // base address: 0x0
1414 #define regVPMPC_OUT0_MUX                                                                               0x0fcc
1415 #define regVPMPC_OUT0_MUX_BASE_IDX                                                                      0
1416 #define regVPMPC_OUT0_FLOAT_CONTROL                                                                     0x0fcd
1417 #define regVPMPC_OUT0_FLOAT_CONTROL_BASE_IDX                                                            0
1418 #define regVPMPC_OUT0_DENORM_CONTROL                                                                    0x0fce
1419 #define regVPMPC_OUT0_DENORM_CONTROL_BASE_IDX                                                           0
1420 #define regVPMPC_OUT0_DENORM_CLAMP_G_Y                                                                  0x0fcf
1421 #define regVPMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX                                                         0
1422 #define regVPMPC_OUT0_DENORM_CLAMP_B_CB                                                                 0x0fd0
1423 #define regVPMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX                                                        0
1424 #define regVPMPC_OUT_CSC_COEF_FORMAT                                                                    0x0fe4
1425 #define regVPMPC_OUT_CSC_COEF_FORMAT_BASE_IDX                                                           0
1426 #define regVPMPC_OUT0_CSC_MODE                                                                          0x0fe5
1427 #define regVPMPC_OUT0_CSC_MODE_BASE_IDX                                                                 0
1428 #define regVPMPC_OUT0_CSC_C11_C12_A                                                                     0x0fe6
1429 #define regVPMPC_OUT0_CSC_C11_C12_A_BASE_IDX                                                            0
1430 #define regVPMPC_OUT0_CSC_C13_C14_A                                                                     0x0fe7
1431 #define regVPMPC_OUT0_CSC_C13_C14_A_BASE_IDX                                                            0
1432 #define regVPMPC_OUT0_CSC_C21_C22_A                                                                     0x0fe8
1433 #define regVPMPC_OUT0_CSC_C21_C22_A_BASE_IDX                                                            0
1434 #define regVPMPC_OUT0_CSC_C23_C24_A                                                                     0x0fe9
1435 #define regVPMPC_OUT0_CSC_C23_C24_A_BASE_IDX                                                            0
1436 #define regVPMPC_OUT0_CSC_C31_C32_A                                                                     0x0fea
1437 #define regVPMPC_OUT0_CSC_C31_C32_A_BASE_IDX                                                            0
1438 #define regVPMPC_OUT0_CSC_C33_C34_A                                                                     0x0feb
1439 #define regVPMPC_OUT0_CSC_C33_C34_A_BASE_IDX                                                            0
1440 
1441 
1442 // addressBlock: vpe_vpep_vpopp_vpfmt0_dispdec
1443 // base address: 0x0
1444 #define regVPFMT_CLAMP_COMPONENT_R                                                                      0x12b0
1445 #define regVPFMT_CLAMP_COMPONENT_R_BASE_IDX                                                             0
1446 #define regVPFMT_CLAMP_COMPONENT_G                                                                      0x12b1
1447 #define regVPFMT_CLAMP_COMPONENT_G_BASE_IDX                                                             0
1448 #define regVPFMT_CLAMP_COMPONENT_B                                                                      0x12b2
1449 #define regVPFMT_CLAMP_COMPONENT_B_BASE_IDX                                                             0
1450 #define regVPFMT_DYNAMIC_EXP_CNTL                                                                       0x12b3
1451 #define regVPFMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                              0
1452 #define regVPFMT_CONTROL                                                                                0x12b4
1453 #define regVPFMT_CONTROL_BASE_IDX                                                                       0
1454 #define regVPFMT_BIT_DEPTH_CONTROL                                                                      0x12b5
1455 #define regVPFMT_BIT_DEPTH_CONTROL_BASE_IDX                                                             0
1456 #define regVPFMT_DITHER_RAND_R_SEED                                                                     0x12b6
1457 #define regVPFMT_DITHER_RAND_R_SEED_BASE_IDX                                                            0
1458 #define regVPFMT_DITHER_RAND_G_SEED                                                                     0x12b7
1459 #define regVPFMT_DITHER_RAND_G_SEED_BASE_IDX                                                            0
1460 #define regVPFMT_DITHER_RAND_B_SEED                                                                     0x12b8
1461 #define regVPFMT_DITHER_RAND_B_SEED_BASE_IDX                                                            0
1462 #define regVPFMT_CLAMP_CNTL                                                                             0x12b9
1463 #define regVPFMT_CLAMP_CNTL_BASE_IDX                                                                    0
1464 
1465 
1466 // addressBlock: vpe_vpep_vpopp_vpopp_pipe0_dispdec
1467 // base address: 0x0
1468 #define regVPOPP_PIPE_CONTROL                                                                           0x12e8
1469 #define regVPOPP_PIPE_CONTROL_BASE_IDX                                                                  0
1470 
1471 
1472 // addressBlock: vpe_vpep_vpopp_vpopp_pipe_crc0_dispdec
1473 // base address: 0x0
1474 #define regVPOPP_PIPE_CRC_CONTROL                                                                       0x12ee
1475 #define regVPOPP_PIPE_CRC_CONTROL_BASE_IDX                                                              0
1476 #define regVPOPP_PIPE_CRC_MASK                                                                          0x12ef
1477 #define regVPOPP_PIPE_CRC_MASK_BASE_IDX                                                                 0
1478 #define regVPOPP_PIPE_CRC_RESULT0                                                                       0x12f0
1479 #define regVPOPP_PIPE_CRC_RESULT0_BASE_IDX                                                              0
1480 #define regVPOPP_PIPE_CRC_RESULT1                                                                       0x12f1
1481 #define regVPOPP_PIPE_CRC_RESULT1_BASE_IDX                                                              0
1482 #define regVPOPP_PIPE_CRC_RESULT2                                                                       0x12f2
1483 #define regVPOPP_PIPE_CRC_RESULT2_BASE_IDX                                                              0
1484 
1485 
1486 // addressBlock: vpe_vpep_vpopp_vpopp_top_dispdec
1487 // base address: 0x0
1488 #define regVPOPP_TOP_CLK_CONTROL                                                                        0x13c2
1489 #define regVPOPP_TOP_CLK_CONTROL_BASE_IDX                                                               0
1490 
1491 
1492 // addressBlock: vpe_vpep_vpcdc_cdc_dispdec
1493 // base address: 0x0
1494 #define regVPEP_MGCG_CNTL                                                                               0x0600
1495 #define regVPEP_MGCG_CNTL_BASE_IDX                                                                      0
1496 #define regVPCDC_SOFT_RESET                                                                             0x0601
1497 #define regVPCDC_SOFT_RESET_BASE_IDX                                                                    0
1498 #define regVPCDC_FE0_SURFACE_CONFIG                                                                     0x0602
1499 #define regVPCDC_FE0_SURFACE_CONFIG_BASE_IDX                                                            0
1500 #define regVPCDC_FE0_CROSSBAR_CONFIG                                                                    0x0603
1501 #define regVPCDC_FE0_CROSSBAR_CONFIG_BASE_IDX                                                           0
1502 #define regVPCDC_FE0_VIEWPORT_START_CONFIG                                                              0x0604
1503 #define regVPCDC_FE0_VIEWPORT_START_CONFIG_BASE_IDX                                                     0
1504 #define regVPCDC_FE0_VIEWPORT_DIMENSION_CONFIG                                                          0x0605
1505 #define regVPCDC_FE0_VIEWPORT_DIMENSION_CONFIG_BASE_IDX                                                 0
1506 #define regVPCDC_FE0_VIEWPORT_START_C_CONFIG                                                            0x0606
1507 #define regVPCDC_FE0_VIEWPORT_START_C_CONFIG_BASE_IDX                                                   0
1508 #define regVPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG                                                        0x0607
1509 #define regVPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG_BASE_IDX                                               0
1510 #define regVPCDC_BE0_P2B_CONFIG                                                                         0x0608
1511 #define regVPCDC_BE0_P2B_CONFIG_BASE_IDX                                                                0
1512 #define regVPCDC_BE0_GLOBAL_SYNC_CONFIG                                                                 0x0609
1513 #define regVPCDC_BE0_GLOBAL_SYNC_CONFIG_BASE_IDX                                                        0
1514 #define regVPCDC_GLOBAL_SYNC_TRIGGER                                                                    0x060a
1515 #define regVPCDC_GLOBAL_SYNC_TRIGGER_BASE_IDX                                                           0
1516 #define regVPCDC_VREADY_STATUS                                                                          0x060b
1517 #define regVPCDC_VREADY_STATUS_BASE_IDX                                                                 0
1518 #define regVPEP_MEM_GLOBAL_PWR_REQ_CNTL                                                                 0x060c
1519 #define regVPEP_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                        0
1520 #define regVPFE_MEM_PWR_CNTL                                                                            0x060d
1521 #define regVPFE_MEM_PWR_CNTL_BASE_IDX                                                                   0
1522 #define regVPBE_MEM_PWR_CNTL                                                                            0x060e
1523 #define regVPBE_MEM_PWR_CNTL_BASE_IDX                                                                   0
1524 #define regVPEP_RBBMIF_TIMEOUT                                                                          0x060f
1525 #define regVPEP_RBBMIF_TIMEOUT_BASE_IDX                                                                 0
1526 #define regVPEP_RBBMIF_STATUS                                                                           0x0610
1527 #define regVPEP_RBBMIF_STATUS_BASE_IDX                                                                  0
1528 #define regVPEP_RBBMIF_TIMEOUT_DIS                                                                      0x0611
1529 #define regVPEP_RBBMIF_TIMEOUT_DIS_BASE_IDX                                                             0
1530 
1531 
1532 // addressBlock: vpe_vpep_vpcdc_vpcdc_dcperfmon_dc_perfmon_dispdec
1533 // base address: 0x3a708
1534 #define regPERFCOUNTER_CNTL                                                                             0x0682
1535 #define regPERFCOUNTER_CNTL_BASE_IDX                                                                    0
1536 #define regPERFCOUNTER_CNTL2                                                                            0x0683
1537 #define regPERFCOUNTER_CNTL2_BASE_IDX                                                                   0
1538 #define regPERFCOUNTER_STATE                                                                            0x0684
1539 #define regPERFCOUNTER_STATE_BASE_IDX                                                                   0
1540 #define regPERFMON_CNTL                                                                                 0x0685
1541 #define regPERFMON_CNTL_BASE_IDX                                                                        0
1542 #define regPERFMON_CNTL2                                                                                0x0686
1543 #define regPERFMON_CNTL2_BASE_IDX                                                                       0
1544 #define regPERFMON_CVALUE_INT_MISC                                                                      0x0687
1545 #define regPERFMON_CVALUE_INT_MISC_BASE_IDX                                                             0
1546 #define regPERFMON_CVALUE_LOW                                                                           0x0688
1547 #define regPERFMON_CVALUE_LOW_BASE_IDX                                                                  0
1548 #define regPERFMON_HI                                                                                   0x0689
1549 #define regPERFMON_HI_BASE_IDX                                                                          0
1550 #define regPERFMON_LOW                                                                                  0x068a
1551 #define regPERFMON_LOW_BASE_IDX                                                                         0
1552 
1553 #endif
1554