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Searched refs:regUVD_VCPU_CNTL (Results 1 – 9 of 9) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dvcn_v5_0_0.c685 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v5_0_0_start_dpg_mode()
708 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v5_0_0_start_dpg_mode()
788 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), in vcn_v5_0_0_start()
823 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, in vcn_v5_0_0_start()
851 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), in vcn_v5_0_0_start()
855 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, in vcn_v5_0_0_start()
990 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), in vcn_v5_0_0_stop()
995 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, in vcn_v5_0_0_stop()
Dvcn_v4_0_5.c899 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v4_0_5_start_dpg_mode()
946 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v4_0_5_start_dpg_mode()
1030 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), in vcn_v4_0_5_start()
1091 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, in vcn_v4_0_5_start()
1119 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), in vcn_v4_0_5_start()
1123 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, in vcn_v4_0_5_start()
1256 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), in vcn_v4_0_5_stop()
1261 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, in vcn_v4_0_5_stop()
Dvcn_v4_0_3.c798 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
845 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
1115 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), in vcn_v4_0_3_start()
1179 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, in vcn_v4_0_3_start()
1199 regUVD_VCPU_CNTL), in vcn_v4_0_3_start()
1204 regUVD_VCPU_CNTL), in vcn_v4_0_3_start()
1346 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), in vcn_v4_0_3_stop()
1351 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, in vcn_v4_0_3_stop()
Dvcn_v4_0.c984 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v4_0_start_dpg_mode()
1031 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v4_0_start_dpg_mode()
1118 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), in vcn_v4_0_start()
1179 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, in vcn_v4_0_start()
1206 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), in vcn_v4_0_start()
1210 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, in vcn_v4_0_start()
1593 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), in vcn_v4_0_stop()
1598 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, in vcn_v4_0_stop()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_2_6_0_offset.h74 #define regUVD_VCPU_CNTL … macro
Dvcn_5_0_0_offset.h412 #define regUVD_VCPU_CNTL … macro
Dvcn_4_0_5_offset.h405 #define regUVD_VCPU_CNTL … macro
Dvcn_4_0_0_offset.h422 #define regUVD_VCPU_CNTL … macro
Dvcn_4_0_3_offset.h424 #define regUVD_VCPU_CNTL … macro