Home
last modified time | relevance | path

Searched refs:regUVD_VCPU_CACHE_SIZE0_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_2_6_0_offset.h33 #define regUVD_VCPU_CACHE_SIZE0_BASE_IDX … macro
Dvcn_5_0_0_offset.h371 #define regUVD_VCPU_CACHE_SIZE0_BASE_IDX … macro
Dvcn_4_0_5_offset.h364 #define regUVD_VCPU_CACHE_SIZE0_BASE_IDX … macro
Dvcn_4_0_0_offset.h381 #define regUVD_VCPU_CACHE_SIZE0_BASE_IDX … macro
Dvcn_4_0_3_offset.h383 #define regUVD_VCPU_CACHE_SIZE0_BASE_IDX … macro