Searched refs:regUVD_MPC_CNTL (Results 1 – 7 of 7) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | vcn_v4_0_5.c | 918 VCN, inst_idx, regUVD_MPC_CNTL), in vcn_v4_0_5_start_dpg_mode()
1055 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL); in vcn_v4_0_5_start()
1058 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp); in vcn_v4_0_5_start()
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| D | vcn_v4_0_3.c | 817 VCN, 0, regUVD_MPC_CNTL), in vcn_v4_0_3_start_dpg_mode()
1141 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL); in vcn_v4_0_3_start()
1144 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp); in vcn_v4_0_3_start()
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| D | vcn_v4_0.c | 1003 VCN, inst_idx, regUVD_MPC_CNTL), in vcn_v4_0_start_dpg_mode()
1143 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL); in vcn_v4_0_start()
1146 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp); in vcn_v4_0_start()
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_2_6_0_offset.h | 1038 #define regUVD_MPC_CNTL … macro
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| D | vcn_4_0_5_offset.h | 437 #define regUVD_MPC_CNTL … macro
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| D | vcn_4_0_0_offset.h | 454 #define regUVD_MPC_CNTL … macro
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| D | vcn_4_0_3_offset.h | 456 #define regUVD_MPC_CNTL … macro
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