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Searched refs:regUVD_CGC_CTRL (Results 1 – 8 of 8) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dvcn_v4_0_5.c653 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_disable_clock_gating()
657 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_5_disable_clock_gating()
684 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_disable_clock_gating()
705 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_5_disable_clock_gating()
790 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v4_0_5_disable_clock_gating_dpg_mode()
821 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_enable_clock_gating()
825 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_5_enable_clock_gating()
827 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_enable_clock_gating()
848 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_5_enable_clock_gating()
Dvcn_v4_0_3.c576 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); in vcn_v4_0_3_disable_clock_gating()
580 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); in vcn_v4_0_3_disable_clock_gating()
599 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); in vcn_v4_0_3_disable_clock_gating()
612 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); in vcn_v4_0_3_disable_clock_gating()
686 VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v4_0_3_disable_clock_gating_dpg_mode()
720 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); in vcn_v4_0_3_enable_clock_gating()
724 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); in vcn_v4_0_3_enable_clock_gating()
726 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); in vcn_v4_0_3_enable_clock_gating()
738 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); in vcn_v4_0_3_enable_clock_gating()
Dvcn_v4_0.c717 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_disable_clock_gating()
721 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_disable_clock_gating()
748 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_disable_clock_gating()
769 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_disable_clock_gating()
854 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v4_0_disable_clock_gating_dpg_mode()
885 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_enable_clock_gating()
889 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_enable_clock_gating()
891 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_enable_clock_gating()
912 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_enable_clock_gating()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_2_6_0_offset.h1248 #define regUVD_CGC_CTRL … macro
Dvcn_5_0_0_offset.h34 #define regUVD_CGC_CTRL … macro
Dvcn_4_0_5_offset.h33 #define regUVD_CGC_CTRL … macro
Dvcn_4_0_0_offset.h34 #define regUVD_CGC_CTRL … macro
Dvcn_4_0_3_offset.h34 #define regUVD_CGC_CTRL … macro