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Searched refs:regSQ_IND_DATA (Results 1 – 10 of 10) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_4_2.c1811 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_ind()
Dgfx_v9_4_3.c726 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); in wave_read_ind()
741 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); in wave_read_regs()
Dgfx_v12_0.c781 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_ind()
794 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_regs()
Dgfx_v11_0.c955 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_ind()
968 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_regs()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_2_offset.h6188 #define regSQ_IND_DATA macro
Dgc_9_4_3_offset.h498 #define regSQ_IND_DATA macro
Dgc_11_5_0_offset.h1259 #define regSQ_IND_DATA macro
Dgc_12_0_0_offset.h7313 #define regSQ_IND_DATA macro
Dgc_11_0_0_offset.h2168 #define regSQ_IND_DATA macro
Dgc_11_0_3_offset.h2234 #define regSQ_IND_DATA macro