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Searched refs:regSPI_WCL_PIPE_PERCENT_CS1 (Results 1 – 7 of 7) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_2_offset.h5992 #define regSPI_WCL_PIPE_PERCENT_CS1 … macro
Dgc_9_4_3_offset.h3166 #define regSPI_WCL_PIPE_PERCENT_CS1 … macro
Dgc_11_5_0_offset.h3541 #define regSPI_WCL_PIPE_PERCENT_CS1 … macro
Dgc_12_0_0_offset.h8009 #define regSPI_WCL_PIPE_PERCENT_CS1 … macro
Dgc_11_0_0_offset.h4568 #define regSPI_WCL_PIPE_PERCENT_CS1 … macro
Dgc_11_0_3_offset.h4792 #define regSPI_WCL_PIPE_PERCENT_CS1 … macro
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_4_3.c3433 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); in gfx_v9_4_3_emit_wave_limit_cs()