Home
last modified time | relevance | path

Searched refs:regSPI_INTERP_CONTROL_0_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_2_offset.h2105 #define regSPI_INTERP_CONTROL_0_BASE_IDX … macro
Dgc_9_4_3_offset.h4345 #define regSPI_INTERP_CONTROL_0_BASE_IDX … macro
Dgc_11_5_0_offset.h4574 #define regSPI_INTERP_CONTROL_0_BASE_IDX … macro
Dgc_12_0_0_offset.h8714 #define regSPI_INTERP_CONTROL_0_BASE_IDX … macro
Dgc_11_0_0_offset.h5763 #define regSPI_INTERP_CONTROL_0_BASE_IDX … macro
Dgc_11_0_3_offset.h6043 #define regSPI_INTERP_CONTROL_0_BASE_IDX … macro