Home
last modified time | relevance | path

Searched refs:regSDMA1_QUEUE1_MIDCMD_DATA0 (Results 1 – 3 of 3) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_12_0_0_offset.h1318 #define regSDMA1_QUEUE1_MIDCMD_DATA0 … macro
Dgc_11_0_0_offset.h1190 #define regSDMA1_QUEUE1_MIDCMD_DATA0 … macro
Dgc_11_0_3_offset.h1202 #define regSDMA1_QUEUE1_MIDCMD_DATA0 … macro