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Searched refs:regSDMA0_QUEUE4_MIDCMD_DATA3 (Results 1 – 4 of 4) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_11_5_0_offset.h607 #define regSDMA0_QUEUE4_MIDCMD_DATA3 … macro
Dgc_12_0_0_offset.h624 #define regSDMA0_QUEUE4_MIDCMD_DATA3 … macro
Dgc_11_0_0_offset.h602 #define regSDMA0_QUEUE4_MIDCMD_DATA3 … macro
Dgc_11_0_3_offset.h608 #define regSDMA0_QUEUE4_MIDCMD_DATA3 … macro