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Searched refs:regSDMA0_QUEUE3_MIDCMD_DATA5 (Results 1 – 4 of 4) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_11_5_0_offset.h525 #define regSDMA0_QUEUE3_MIDCMD_DATA5 … macro
Dgc_12_0_0_offset.h534 #define regSDMA0_QUEUE3_MIDCMD_DATA5 … macro
Dgc_11_0_0_offset.h520 #define regSDMA0_QUEUE3_MIDCMD_DATA5 … macro
Dgc_11_0_3_offset.h526 #define regSDMA0_QUEUE3_MIDCMD_DATA5 … macro