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Searched refs:regSDMA0_QUEUE0_RB_RPTR (Results 1 – 7 of 7) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Damdgpu_amdkfd_gfx_v11.c379 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_RPTR, in hqd_sdma_load_v11()
567 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_RPTR); in hqd_sdma_destroy_v11()
Dsdma_v7_0.c78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR),
530 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); in sdma_v7_0_gfx_resume()
Dsdma_v6_0.c78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR),
509 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); in sdma_v6_0_gfx_resume()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_11_5_0_offset.h201 #define regSDMA0_QUEUE0_RB_RPTR macro
Dgc_12_0_0_offset.h188 #define regSDMA0_QUEUE0_RB_RPTR macro
Dgc_11_0_0_offset.h196 #define regSDMA0_QUEUE0_RB_RPTR macro
Dgc_11_0_3_offset.h202 #define regSDMA0_QUEUE0_RB_RPTR macro