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Searched refs:regRLC_CP_SCHEDULERS (Results 1 – 12 of 12) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dmes_v11_0.c1455 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in mes_v11_0_kiq_setting()
1458 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in mes_v11_0_kiq_setting()
1460 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in mes_v11_0_kiq_setting()
1468 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in mes_v11_0_kiq_clear()
1470 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in mes_v11_0_kiq_clear()
Damdgpu_amdkfd_gfx_v11.c187 value = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_CP_SCHEDULERS)); in hqd_load_v11()
190 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_CP_SCHEDULERS), value); in hqd_load_v11()
Dmes_v12_0.c1444 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in mes_v12_0_kiq_setting()
1447 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in mes_v12_0_kiq_setting()
1449 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in mes_v12_0_kiq_setting()
Dgfx_v12_0.c2814 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in gfx_v12_0_kiq_setting()
2817 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in gfx_v12_0_kiq_setting()
2819 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in gfx_v12_0_kiq_setting()
3630 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in gfx_v12_0_hw_fini()
3632 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in gfx_v12_0_hw_fini()
Dgfx_v9_4_3.c1773 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); in gfx_v9_4_3_xcc_kiq_setting()
1776 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); in gfx_v9_4_3_xcc_kiq_setting()
1778 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); in gfx_v9_4_3_xcc_kiq_setting()
Dgfx_v11_0.c3863 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in gfx_v11_0_kiq_setting()
3866 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in gfx_v11_0_kiq_setting()
3868 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in gfx_v11_0_kiq_setting()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_2_offset.h5128 #define regRLC_CP_SCHEDULERS … macro
Dgc_9_4_3_offset.h6646 #define regRLC_CP_SCHEDULERS … macro
Dgc_11_5_0_offset.h9025 #define regRLC_CP_SCHEDULERS … macro
Dgc_12_0_0_offset.h7035 #define regRLC_CP_SCHEDULERS … macro
Dgc_11_0_0_offset.h10594 #define regRLC_CP_SCHEDULERS … macro
Dgc_11_0_3_offset.h11214 #define regRLC_CP_SCHEDULERS … macro