Searched refs:regRLC_CNTL (Results 1 – 9 of 9) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v12_0.c | 1275 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); in gfx_v12_0_rlc_backdoor_autoload_enable()
1779 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); in gfx_v12_0_rlc_stop()
1782 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); in gfx_v12_0_rlc_stop()
3745 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); in gfx_v12_0_is_rlc_enabled()
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| D | gfx_v11_0.c | 2066 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); in gfx_v11_0_rlc_stop()
2069 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); in gfx_v11_0_rlc_stop()
5045 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); in gfx_v11_0_is_rlc_enabled()
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| D | gfx_v9_4_3.c | 1369 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); in gfx_v9_4_3_is_rlc_enabled()
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_4_2_offset.h | 4888 #define regRLC_CNTL … macro
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| D | gc_9_4_3_offset.h | 6392 #define regRLC_CNTL … macro
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| D | gc_11_5_0_offset.h | 8471 #define regRLC_CNTL … macro
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| D | gc_12_0_0_offset.h | 6298 #define regRLC_CNTL … macro
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| D | gc_11_0_0_offset.h | 9800 #define regRLC_CNTL … macro
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| D | gc_11_0_3_offset.h | 10402 #define regRLC_CNTL … macro
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