1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _nbif_6_3_1_OFFSET_HEADER 24 #define _nbif_6_3_1_OFFSET_HEADER 25 26 27 // addressBlock: nbif_bif_cfg_dev0_rc_bifcfgdecp 28 // base address: 0x0 29 #define cfgIRQ_BRIDGE_CNTL 0x003e 30 31 32 // addressBlock: nbif_bif_cfg_dev0_epf0_bifcfgdecp 33 // base address: 0x0 34 #define cfgBIF_CFG_DEV0_EPF0_VENDOR_ID 0x0000 35 #define cfgBIF_CFG_DEV0_EPF0_DEVICE_ID 0x0002 36 #define cfgBIF_CFG_DEV0_EPF0_COMMAND 0x0004 37 #define cfgBIF_CFG_DEV0_EPF0_STATUS 0x0006 38 #define cfgBIF_CFG_DEV0_EPF0_REVISION_ID 0x0008 39 #define cfgBIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x0009 40 #define cfgBIF_CFG_DEV0_EPF0_SUB_CLASS 0x000a 41 #define cfgBIF_CFG_DEV0_EPF0_BASE_CLASS 0x000b 42 #define cfgBIF_CFG_DEV0_EPF0_CACHE_LINE 0x000c 43 #define cfgBIF_CFG_DEV0_EPF0_LATENCY 0x000d 44 #define cfgBIF_CFG_DEV0_EPF0_HEADER 0x000e 45 #define cfgBIF_CFG_DEV0_EPF0_BIST 0x000f 46 #define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_1 0x0010 47 #define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_2 0x0014 48 #define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_3 0x0018 49 #define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_4 0x001c 50 #define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_5 0x0020 51 #define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_6 0x0024 52 #define cfgBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR 0x0028 53 #define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID 0x002c 54 #define cfgBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR 0x0030 55 #define cfgBIF_CFG_DEV0_EPF0_CAP_PTR 0x0034 56 #define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_LINE 0x003c 57 #define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_PIN 0x003d 58 #define cfgBIF_CFG_DEV0_EPF0_MIN_GRANT 0x003e 59 #define cfgBIF_CFG_DEV0_EPF0_MAX_LATENCY 0x003f 60 #define cfgBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST 0x0048 61 #define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID_W 0x004c 62 #define cfgBIF_CFG_DEV0_EPF0_PMI_CAP_LIST 0x0050 63 #define cfgBIF_CFG_DEV0_EPF0_PMI_CAP 0x0052 64 #define cfgBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL 0x0054 65 #define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST 0x0064 66 #define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP 0x0066 67 #define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP 0x0068 68 #define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL 0x006c 69 #define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS 0x006e 70 #define cfgBIF_CFG_DEV0_EPF0_LINK_CAP 0x0070 71 #define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL 0x0074 72 #define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS 0x0076 73 #define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP2 0x0088 74 #define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x008c 75 #define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS2 0x008e 76 #define cfgBIF_CFG_DEV0_EPF0_LINK_CAP2 0x0090 77 #define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL2 0x0094 78 #define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS2 0x0096 79 #define cfgBIF_CFG_DEV0_EPF0_MSI_CAP_LIST 0x00a0 80 #define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL 0x00a2 81 #define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO 0x00a4 82 #define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI 0x00a8 83 #define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA 0x00a8 84 #define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA 0x00aa 85 #define cfgBIF_CFG_DEV0_EPF0_MSI_MASK 0x00ac 86 #define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 0x00ac 87 #define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 0x00ae 88 #define cfgBIF_CFG_DEV0_EPF0_MSI_MASK_64 0x00b0 89 #define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING 0x00b0 90 #define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING_64 0x00b4 91 #define cfgBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST 0x00c0 92 #define cfgBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL 0x00c2 93 #define cfgBIF_CFG_DEV0_EPF0_MSIX_TABLE 0x00c4 94 #define cfgBIF_CFG_DEV0_EPF0_MSIX_PBA 0x00c8 95 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 96 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 97 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 0x0108 98 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 0x010c 99 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST 0x0110 100 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 0x0114 101 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 0x0118 102 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL 0x011c 103 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS 0x011e 104 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP 0x0120 105 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL 0x0124 106 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS 0x012a 107 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP 0x012c 108 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL 0x0130 109 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS 0x0136 110 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 111 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 112 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 113 #define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 114 #define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS 0x0154 115 #define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK 0x0158 116 #define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY 0x015c 117 #define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS 0x0160 118 #define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK 0x0164 119 #define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL 0x0168 120 #define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 0x016c 121 #define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 0x0170 122 #define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 0x0174 123 #define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 0x0178 124 #define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 0x0188 125 #define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 0x018c 126 #define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 0x0190 127 #define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 0x0194 128 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST 0x0200 129 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP 0x0204 130 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL 0x0208 131 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP 0x020c 132 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL 0x0210 133 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP 0x0214 134 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL 0x0218 135 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP 0x021c 136 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL 0x0220 137 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP 0x0224 138 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL 0x0228 139 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP 0x022c 140 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL 0x0230 141 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 142 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 143 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA 0x0248 144 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP 0x024c 145 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST 0x0250 146 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP 0x0254 147 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR 0x0258 148 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS 0x025c 149 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL 0x025e 150 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 151 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 152 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 153 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 154 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 155 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 156 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 157 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 158 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 159 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 0x0274 160 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS 0x0278 161 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 162 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 163 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 164 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 165 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 166 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 167 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 168 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 169 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 170 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 171 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 172 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 173 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 174 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 175 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 176 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 177 #define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST 0x02a0 178 #define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP 0x02a4 179 #define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL 0x02a6 180 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST 0x02d0 181 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP 0x02d4 182 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL 0x02d6 183 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST 0x0320 184 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x0324 185 #define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST 0x0328 186 #define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP 0x032c 187 #define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL 0x032e 188 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 189 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP 0x0334 190 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL 0x0338 191 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS 0x033a 192 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS 0x033c 193 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS 0x033e 194 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS 0x0340 195 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 196 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 197 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE 0x0346 198 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID 0x034a 199 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c 200 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 201 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 202 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 203 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c 204 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 205 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 206 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 207 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c 208 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST 0x0400 209 #define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP 0x0404 210 #define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS 0x0408 211 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 212 #define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_16GT 0x0414 213 #define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT 0x0418 214 #define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT 0x041c 215 #define cfgBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 216 #define cfgBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 217 #define cfgBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 218 #define cfgBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 219 #define cfgBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 220 #define cfgBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 221 #define cfgBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 222 #define cfgBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 223 #define cfgBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 224 #define cfgBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 225 #define cfgBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 226 #define cfgBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 227 #define cfgBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 228 #define cfgBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a 229 #define cfgBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b 230 #define cfgBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c 231 #define cfgBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d 232 #define cfgBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e 233 #define cfgBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f 234 #define cfgBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST 0x0450 235 #define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP 0x0454 236 #define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS 0x0456 237 #define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL 0x0458 238 #define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS 0x045a 239 #define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL 0x045c 240 #define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS 0x045e 241 #define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL 0x0460 242 #define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS 0x0462 243 #define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL 0x0464 244 #define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS 0x0466 245 #define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL 0x0468 246 #define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS 0x046a 247 #define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL 0x046c 248 #define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS 0x046e 249 #define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL 0x0470 250 #define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS 0x0472 251 #define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL 0x0474 252 #define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS 0x0476 253 #define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL 0x0478 254 #define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS 0x047a 255 #define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL 0x047c 256 #define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS 0x047e 257 #define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL 0x0480 258 #define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS 0x0482 259 #define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL 0x0484 260 #define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS 0x0486 261 #define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL 0x0488 262 #define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS 0x048a 263 #define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL 0x048c 264 #define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS 0x048e 265 #define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL 0x0490 266 #define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS 0x0492 267 #define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL 0x0494 268 #define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS 0x0496 269 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0 270 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP 0x04c4 271 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8 272 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP 0x04cc 273 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0 274 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP 0x04d4 275 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8 276 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP 0x04dc 277 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0 278 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP 0x04e4 279 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8 280 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP 0x04ec 281 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0 282 #define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_32GT 0x0504 283 #define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT 0x0508 284 #define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT 0x050c 285 286 287 // addressBlock: nbif_bif_cfg_dev0_epf0_vf0_bifcfgdecp 288 // base address: 0x0 289 #define cfgBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID 0x0000 290 #define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID 0x0002 291 #define cfgBIF_CFG_DEV0_EPF0_VF0_COMMAND 0x0004 292 #define cfgBIF_CFG_DEV0_EPF0_VF0_STATUS 0x0006 293 #define cfgBIF_CFG_DEV0_EPF0_VF0_REVISION_ID 0x0008 294 #define cfgBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE 0x0009 295 #define cfgBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS 0x000a 296 #define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS 0x000b 297 #define cfgBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE 0x000c 298 #define cfgBIF_CFG_DEV0_EPF0_VF0_LATENCY 0x000d 299 #define cfgBIF_CFG_DEV0_EPF0_VF0_HEADER 0x000e 300 #define cfgBIF_CFG_DEV0_EPF0_VF0_BIST 0x000f 301 #define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 0x0010 302 #define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 0x0014 303 #define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 0x0018 304 #define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 0x001c 305 #define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 0x0020 306 #define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 0x0024 307 #define cfgBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR 0x0028 308 #define cfgBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID 0x002c 309 #define cfgBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR 0x0030 310 #define cfgBIF_CFG_DEV0_EPF0_VF0_CAP_PTR 0x0034 311 #define cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE 0x003c 312 #define cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN 0x003d 313 #define cfgBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT 0x003e 314 #define cfgBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY 0x003f 315 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST 0x0064 316 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP 0x0066 317 #define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP 0x0068 318 #define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL 0x006c 319 #define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS 0x006e 320 #define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP 0x0070 321 #define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL 0x0074 322 #define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS 0x0076 323 #define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 0x0088 324 #define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 0x008c 325 #define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 0x008e 326 #define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 0x0090 327 #define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 0x0094 328 #define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 0x0096 329 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST 0x00a0 330 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL 0x00a2 331 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO 0x00a4 332 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI 0x00a8 333 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA 0x00a8 334 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA 0x00aa 335 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK 0x00ac 336 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 0x00ac 337 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 0x00ae 338 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 0x00b0 339 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING 0x00b0 340 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 0x00b4 341 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST 0x00c0 342 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL 0x00c2 343 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE 0x00c4 344 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA 0x00c8 345 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 346 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 347 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 0x0108 348 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 0x010c 349 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 350 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS 0x0154 351 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK 0x0158 352 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY 0x015c 353 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS 0x0160 354 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK 0x0164 355 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL 0x0168 356 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 0x016c 357 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 0x0170 358 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 0x0174 359 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 0x0178 360 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 0x0188 361 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 0x018c 362 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 0x0190 363 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 0x0194 364 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST 0x0328 365 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP 0x032c 366 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL 0x032e 367 368 369 // addressBlock: nbif_bif_cfg_dev0_epf0_vf1_bifcfgdecp 370 // base address: 0x0 371 #define cfgBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID 0x0000 372 #define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID 0x0002 373 #define cfgBIF_CFG_DEV0_EPF0_VF1_COMMAND 0x0004 374 #define cfgBIF_CFG_DEV0_EPF0_VF1_STATUS 0x0006 375 #define cfgBIF_CFG_DEV0_EPF0_VF1_REVISION_ID 0x0008 376 #define cfgBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE 0x0009 377 #define cfgBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS 0x000a 378 #define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS 0x000b 379 #define cfgBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE 0x000c 380 #define cfgBIF_CFG_DEV0_EPF0_VF1_LATENCY 0x000d 381 #define cfgBIF_CFG_DEV0_EPF0_VF1_HEADER 0x000e 382 #define cfgBIF_CFG_DEV0_EPF0_VF1_BIST 0x000f 383 #define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 0x0010 384 #define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 0x0014 385 #define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 0x0018 386 #define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 0x001c 387 #define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 0x0020 388 #define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 0x0024 389 #define cfgBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR 0x0028 390 #define cfgBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID 0x002c 391 #define cfgBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR 0x0030 392 #define cfgBIF_CFG_DEV0_EPF0_VF1_CAP_PTR 0x0034 393 #define cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE 0x003c 394 #define cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN 0x003d 395 #define cfgBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT 0x003e 396 #define cfgBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY 0x003f 397 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST 0x0064 398 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP 0x0066 399 #define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP 0x0068 400 #define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL 0x006c 401 #define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS 0x006e 402 #define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP 0x0070 403 #define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL 0x0074 404 #define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS 0x0076 405 #define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 0x0088 406 #define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 0x008c 407 #define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 0x008e 408 #define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 0x0090 409 #define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 0x0094 410 #define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 0x0096 411 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST 0x00a0 412 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL 0x00a2 413 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO 0x00a4 414 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI 0x00a8 415 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA 0x00a8 416 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA 0x00aa 417 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK 0x00ac 418 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 0x00ac 419 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 0x00ae 420 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 0x00b0 421 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING 0x00b0 422 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 0x00b4 423 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST 0x00c0 424 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL 0x00c2 425 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE 0x00c4 426 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA 0x00c8 427 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 428 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 429 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 0x0108 430 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 0x010c 431 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 432 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS 0x0154 433 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK 0x0158 434 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY 0x015c 435 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS 0x0160 436 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK 0x0164 437 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL 0x0168 438 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 0x016c 439 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 0x0170 440 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 0x0174 441 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 0x0178 442 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 0x0188 443 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 0x018c 444 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 0x0190 445 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 0x0194 446 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST 0x0328 447 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP 0x032c 448 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL 0x032e 449 450 451 // addressBlock: nbif_bif_cfg_dev0_epf0_vf2_bifcfgdecp 452 // base address: 0x0 453 #define cfgBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID 0x0000 454 #define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID 0x0002 455 #define cfgBIF_CFG_DEV0_EPF0_VF2_COMMAND 0x0004 456 #define cfgBIF_CFG_DEV0_EPF0_VF2_STATUS 0x0006 457 #define cfgBIF_CFG_DEV0_EPF0_VF2_REVISION_ID 0x0008 458 #define cfgBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE 0x0009 459 #define cfgBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS 0x000a 460 #define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS 0x000b 461 #define cfgBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE 0x000c 462 #define cfgBIF_CFG_DEV0_EPF0_VF2_LATENCY 0x000d 463 #define cfgBIF_CFG_DEV0_EPF0_VF2_HEADER 0x000e 464 #define cfgBIF_CFG_DEV0_EPF0_VF2_BIST 0x000f 465 #define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 0x0010 466 #define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 0x0014 467 #define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 0x0018 468 #define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 0x001c 469 #define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 0x0020 470 #define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 0x0024 471 #define cfgBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR 0x0028 472 #define cfgBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID 0x002c 473 #define cfgBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR 0x0030 474 #define cfgBIF_CFG_DEV0_EPF0_VF2_CAP_PTR 0x0034 475 #define cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE 0x003c 476 #define cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN 0x003d 477 #define cfgBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT 0x003e 478 #define cfgBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY 0x003f 479 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST 0x0064 480 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP 0x0066 481 #define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP 0x0068 482 #define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL 0x006c 483 #define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS 0x006e 484 #define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP 0x0070 485 #define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL 0x0074 486 #define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS 0x0076 487 #define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 0x0088 488 #define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 0x008c 489 #define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 0x008e 490 #define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 0x0090 491 #define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 0x0094 492 #define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 0x0096 493 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST 0x00a0 494 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL 0x00a2 495 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO 0x00a4 496 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI 0x00a8 497 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA 0x00a8 498 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA 0x00aa 499 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK 0x00ac 500 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 0x00ac 501 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 0x00ae 502 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 0x00b0 503 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING 0x00b0 504 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 0x00b4 505 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST 0x00c0 506 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL 0x00c2 507 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE 0x00c4 508 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA 0x00c8 509 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 510 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR 0x0104 511 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 0x0108 512 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 0x010c 513 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 514 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS 0x0154 515 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK 0x0158 516 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY 0x015c 517 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS 0x0160 518 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK 0x0164 519 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL 0x0168 520 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 0x016c 521 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 0x0170 522 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 0x0174 523 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 0x0178 524 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 0x0188 525 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 0x018c 526 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 0x0190 527 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 0x0194 528 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST 0x0328 529 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP 0x032c 530 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL 0x032e 531 532 533 // addressBlock: nbif_bif_cfg_dev0_epf0_vf3_bifcfgdecp 534 // base address: 0x0 535 #define cfgBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID 0x0000 536 #define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID 0x0002 537 #define cfgBIF_CFG_DEV0_EPF0_VF3_COMMAND 0x0004 538 #define cfgBIF_CFG_DEV0_EPF0_VF3_STATUS 0x0006 539 #define cfgBIF_CFG_DEV0_EPF0_VF3_REVISION_ID 0x0008 540 #define cfgBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE 0x0009 541 #define cfgBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS 0x000a 542 #define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS 0x000b 543 #define cfgBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE 0x000c 544 #define cfgBIF_CFG_DEV0_EPF0_VF3_LATENCY 0x000d 545 #define cfgBIF_CFG_DEV0_EPF0_VF3_HEADER 0x000e 546 #define cfgBIF_CFG_DEV0_EPF0_VF3_BIST 0x000f 547 #define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 0x0010 548 #define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 0x0014 549 #define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 0x0018 550 #define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 0x001c 551 #define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 0x0020 552 #define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 0x0024 553 #define cfgBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR 0x0028 554 #define cfgBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID 0x002c 555 #define cfgBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR 0x0030 556 #define cfgBIF_CFG_DEV0_EPF0_VF3_CAP_PTR 0x0034 557 #define cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE 0x003c 558 #define cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN 0x003d 559 #define cfgBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT 0x003e 560 #define cfgBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY 0x003f 561 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST 0x0064 562 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP 0x0066 563 #define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP 0x0068 564 #define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL 0x006c 565 #define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS 0x006e 566 #define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP 0x0070 567 #define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL 0x0074 568 #define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS 0x0076 569 #define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 0x0088 570 #define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 0x008c 571 #define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 0x008e 572 #define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 0x0090 573 #define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 0x0094 574 #define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 0x0096 575 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST 0x00a0 576 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL 0x00a2 577 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO 0x00a4 578 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI 0x00a8 579 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA 0x00a8 580 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA 0x00aa 581 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK 0x00ac 582 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 0x00ac 583 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 0x00ae 584 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 0x00b0 585 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING 0x00b0 586 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 0x00b4 587 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST 0x00c0 588 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL 0x00c2 589 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE 0x00c4 590 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA 0x00c8 591 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 592 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR 0x0104 593 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 0x0108 594 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 0x010c 595 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 596 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS 0x0154 597 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK 0x0158 598 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY 0x015c 599 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS 0x0160 600 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK 0x0164 601 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL 0x0168 602 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 0x016c 603 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 0x0170 604 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 0x0174 605 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 0x0178 606 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 0x0188 607 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 0x018c 608 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 0x0190 609 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 0x0194 610 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST 0x0328 611 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP 0x032c 612 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL 0x032e 613 614 615 // addressBlock: nbif_bif_cfg_dev0_epf0_vf4_bifcfgdecp 616 // base address: 0x0 617 #define cfgBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID 0x0000 618 #define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID 0x0002 619 #define cfgBIF_CFG_DEV0_EPF0_VF4_COMMAND 0x0004 620 #define cfgBIF_CFG_DEV0_EPF0_VF4_STATUS 0x0006 621 #define cfgBIF_CFG_DEV0_EPF0_VF4_REVISION_ID 0x0008 622 #define cfgBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE 0x0009 623 #define cfgBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS 0x000a 624 #define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS 0x000b 625 #define cfgBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE 0x000c 626 #define cfgBIF_CFG_DEV0_EPF0_VF4_LATENCY 0x000d 627 #define cfgBIF_CFG_DEV0_EPF0_VF4_HEADER 0x000e 628 #define cfgBIF_CFG_DEV0_EPF0_VF4_BIST 0x000f 629 #define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 0x0010 630 #define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 0x0014 631 #define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 0x0018 632 #define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 0x001c 633 #define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 0x0020 634 #define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 0x0024 635 #define cfgBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR 0x0028 636 #define cfgBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID 0x002c 637 #define cfgBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR 0x0030 638 #define cfgBIF_CFG_DEV0_EPF0_VF4_CAP_PTR 0x0034 639 #define cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE 0x003c 640 #define cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN 0x003d 641 #define cfgBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT 0x003e 642 #define cfgBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY 0x003f 643 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST 0x0064 644 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP 0x0066 645 #define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP 0x0068 646 #define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL 0x006c 647 #define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS 0x006e 648 #define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP 0x0070 649 #define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL 0x0074 650 #define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS 0x0076 651 #define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 0x0088 652 #define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 0x008c 653 #define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 0x008e 654 #define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 0x0090 655 #define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 0x0094 656 #define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 0x0096 657 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST 0x00a0 658 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL 0x00a2 659 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO 0x00a4 660 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI 0x00a8 661 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA 0x00a8 662 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA 0x00aa 663 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK 0x00ac 664 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 0x00ac 665 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 0x00ae 666 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 0x00b0 667 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING 0x00b0 668 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 0x00b4 669 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST 0x00c0 670 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL 0x00c2 671 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE 0x00c4 672 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA 0x00c8 673 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 674 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR 0x0104 675 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 0x0108 676 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 0x010c 677 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 678 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS 0x0154 679 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK 0x0158 680 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY 0x015c 681 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS 0x0160 682 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK 0x0164 683 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL 0x0168 684 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 0x016c 685 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 0x0170 686 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 0x0174 687 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 0x0178 688 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 0x0188 689 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 0x018c 690 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 0x0190 691 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 0x0194 692 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST 0x0328 693 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP 0x032c 694 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL 0x032e 695 696 697 // addressBlock: nbif_bif_cfg_dev0_epf0_vf5_bifcfgdecp 698 // base address: 0x0 699 #define cfgBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID 0x0000 700 #define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID 0x0002 701 #define cfgBIF_CFG_DEV0_EPF0_VF5_COMMAND 0x0004 702 #define cfgBIF_CFG_DEV0_EPF0_VF5_STATUS 0x0006 703 #define cfgBIF_CFG_DEV0_EPF0_VF5_REVISION_ID 0x0008 704 #define cfgBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE 0x0009 705 #define cfgBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS 0x000a 706 #define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS 0x000b 707 #define cfgBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE 0x000c 708 #define cfgBIF_CFG_DEV0_EPF0_VF5_LATENCY 0x000d 709 #define cfgBIF_CFG_DEV0_EPF0_VF5_HEADER 0x000e 710 #define cfgBIF_CFG_DEV0_EPF0_VF5_BIST 0x000f 711 #define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 0x0010 712 #define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 0x0014 713 #define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 0x0018 714 #define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 0x001c 715 #define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 0x0020 716 #define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 0x0024 717 #define cfgBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR 0x0028 718 #define cfgBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID 0x002c 719 #define cfgBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR 0x0030 720 #define cfgBIF_CFG_DEV0_EPF0_VF5_CAP_PTR 0x0034 721 #define cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE 0x003c 722 #define cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN 0x003d 723 #define cfgBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT 0x003e 724 #define cfgBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY 0x003f 725 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST 0x0064 726 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP 0x0066 727 #define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP 0x0068 728 #define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL 0x006c 729 #define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS 0x006e 730 #define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP 0x0070 731 #define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL 0x0074 732 #define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS 0x0076 733 #define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 0x0088 734 #define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 0x008c 735 #define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 0x008e 736 #define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 0x0090 737 #define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 0x0094 738 #define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 0x0096 739 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST 0x00a0 740 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL 0x00a2 741 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO 0x00a4 742 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI 0x00a8 743 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA 0x00a8 744 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA 0x00aa 745 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK 0x00ac 746 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 0x00ac 747 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 0x00ae 748 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 0x00b0 749 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING 0x00b0 750 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 0x00b4 751 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST 0x00c0 752 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL 0x00c2 753 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE 0x00c4 754 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA 0x00c8 755 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 756 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR 0x0104 757 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 0x0108 758 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 0x010c 759 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 760 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS 0x0154 761 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK 0x0158 762 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY 0x015c 763 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS 0x0160 764 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK 0x0164 765 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL 0x0168 766 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 0x016c 767 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 0x0170 768 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 0x0174 769 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 0x0178 770 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 0x0188 771 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 0x018c 772 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 0x0190 773 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 0x0194 774 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST 0x0328 775 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP 0x032c 776 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL 0x032e 777 778 779 // addressBlock: nbif_bif_cfg_dev0_epf0_vf6_bifcfgdecp 780 // base address: 0x0 781 #define cfgBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID 0x0000 782 #define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID 0x0002 783 #define cfgBIF_CFG_DEV0_EPF0_VF6_COMMAND 0x0004 784 #define cfgBIF_CFG_DEV0_EPF0_VF6_STATUS 0x0006 785 #define cfgBIF_CFG_DEV0_EPF0_VF6_REVISION_ID 0x0008 786 #define cfgBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE 0x0009 787 #define cfgBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS 0x000a 788 #define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS 0x000b 789 #define cfgBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE 0x000c 790 #define cfgBIF_CFG_DEV0_EPF0_VF6_LATENCY 0x000d 791 #define cfgBIF_CFG_DEV0_EPF0_VF6_HEADER 0x000e 792 #define cfgBIF_CFG_DEV0_EPF0_VF6_BIST 0x000f 793 #define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 0x0010 794 #define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 0x0014 795 #define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 0x0018 796 #define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 0x001c 797 #define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 0x0020 798 #define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 0x0024 799 #define cfgBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR 0x0028 800 #define cfgBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID 0x002c 801 #define cfgBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR 0x0030 802 #define cfgBIF_CFG_DEV0_EPF0_VF6_CAP_PTR 0x0034 803 #define cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE 0x003c 804 #define cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN 0x003d 805 #define cfgBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT 0x003e 806 #define cfgBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY 0x003f 807 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST 0x0064 808 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP 0x0066 809 #define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP 0x0068 810 #define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL 0x006c 811 #define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS 0x006e 812 #define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP 0x0070 813 #define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL 0x0074 814 #define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS 0x0076 815 #define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 0x0088 816 #define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 0x008c 817 #define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 0x008e 818 #define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 0x0090 819 #define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 0x0094 820 #define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 0x0096 821 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST 0x00a0 822 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL 0x00a2 823 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO 0x00a4 824 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI 0x00a8 825 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA 0x00a8 826 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA 0x00aa 827 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK 0x00ac 828 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 0x00ac 829 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 0x00ae 830 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 0x00b0 831 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING 0x00b0 832 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 0x00b4 833 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST 0x00c0 834 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL 0x00c2 835 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE 0x00c4 836 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA 0x00c8 837 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 838 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR 0x0104 839 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 0x0108 840 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 0x010c 841 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 842 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS 0x0154 843 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK 0x0158 844 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY 0x015c 845 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS 0x0160 846 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK 0x0164 847 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL 0x0168 848 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 0x016c 849 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 0x0170 850 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 0x0174 851 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 0x0178 852 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 0x0188 853 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 0x018c 854 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 0x0190 855 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 0x0194 856 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST 0x0328 857 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP 0x032c 858 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL 0x032e 859 860 861 // addressBlock: nbif_bif_cfg_dev0_epf0_vf7_bifcfgdecp 862 // base address: 0x0 863 #define cfgBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID 0x0000 864 #define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID 0x0002 865 #define cfgBIF_CFG_DEV0_EPF0_VF7_COMMAND 0x0004 866 #define cfgBIF_CFG_DEV0_EPF0_VF7_STATUS 0x0006 867 #define cfgBIF_CFG_DEV0_EPF0_VF7_REVISION_ID 0x0008 868 #define cfgBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE 0x0009 869 #define cfgBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS 0x000a 870 #define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS 0x000b 871 #define cfgBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE 0x000c 872 #define cfgBIF_CFG_DEV0_EPF0_VF7_LATENCY 0x000d 873 #define cfgBIF_CFG_DEV0_EPF0_VF7_HEADER 0x000e 874 #define cfgBIF_CFG_DEV0_EPF0_VF7_BIST 0x000f 875 #define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 0x0010 876 #define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 0x0014 877 #define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 0x0018 878 #define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 0x001c 879 #define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 0x0020 880 #define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 0x0024 881 #define cfgBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR 0x0028 882 #define cfgBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID 0x002c 883 #define cfgBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR 0x0030 884 #define cfgBIF_CFG_DEV0_EPF0_VF7_CAP_PTR 0x0034 885 #define cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE 0x003c 886 #define cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN 0x003d 887 #define cfgBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT 0x003e 888 #define cfgBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY 0x003f 889 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST 0x0064 890 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP 0x0066 891 #define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP 0x0068 892 #define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL 0x006c 893 #define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS 0x006e 894 #define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP 0x0070 895 #define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL 0x0074 896 #define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS 0x0076 897 #define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 0x0088 898 #define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 0x008c 899 #define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 0x008e 900 #define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 0x0090 901 #define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 0x0094 902 #define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 0x0096 903 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST 0x00a0 904 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL 0x00a2 905 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO 0x00a4 906 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI 0x00a8 907 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA 0x00a8 908 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA 0x00aa 909 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK 0x00ac 910 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 0x00ac 911 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 0x00ae 912 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 0x00b0 913 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING 0x00b0 914 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 0x00b4 915 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST 0x00c0 916 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL 0x00c2 917 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE 0x00c4 918 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA 0x00c8 919 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 920 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR 0x0104 921 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 0x0108 922 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 0x010c 923 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 924 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS 0x0154 925 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK 0x0158 926 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY 0x015c 927 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS 0x0160 928 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK 0x0164 929 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL 0x0168 930 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 0x016c 931 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 0x0170 932 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 0x0174 933 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 0x0178 934 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 0x0188 935 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 0x018c 936 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 0x0190 937 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 0x0194 938 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST 0x0328 939 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP 0x032c 940 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL 0x032e 941 942 943 // addressBlock: nbif_bif_cfg_dev0_epf1_bifcfgdecp 944 // base address: 0x0 945 #define cfgBIF_CFG_DEV0_EPF1_VENDOR_ID 0x0000 946 #define cfgBIF_CFG_DEV0_EPF1_DEVICE_ID 0x0002 947 #define cfgBIF_CFG_DEV0_EPF1_COMMAND 0x0004 948 #define cfgBIF_CFG_DEV0_EPF1_STATUS 0x0006 949 #define cfgBIF_CFG_DEV0_EPF1_REVISION_ID 0x0008 950 #define cfgBIF_CFG_DEV0_EPF1_PROG_INTERFACE 0x0009 951 #define cfgBIF_CFG_DEV0_EPF1_SUB_CLASS 0x000a 952 #define cfgBIF_CFG_DEV0_EPF1_BASE_CLASS 0x000b 953 #define cfgBIF_CFG_DEV0_EPF1_CACHE_LINE 0x000c 954 #define cfgBIF_CFG_DEV0_EPF1_LATENCY 0x000d 955 #define cfgBIF_CFG_DEV0_EPF1_HEADER 0x000e 956 #define cfgBIF_CFG_DEV0_EPF1_BIST 0x000f 957 #define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_1 0x0010 958 #define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_2 0x0014 959 #define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_3 0x0018 960 #define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_4 0x001c 961 #define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_5 0x0020 962 #define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_6 0x0024 963 #define cfgBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR 0x0028 964 #define cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID 0x002c 965 #define cfgBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR 0x0030 966 #define cfgBIF_CFG_DEV0_EPF1_CAP_PTR 0x0034 967 #define cfgBIF_CFG_DEV0_EPF1_INTERRUPT_LINE 0x003c 968 #define cfgBIF_CFG_DEV0_EPF1_INTERRUPT_PIN 0x003d 969 #define cfgBIF_CFG_DEV0_EPF1_MIN_GRANT 0x003e 970 #define cfgBIF_CFG_DEV0_EPF1_MAX_LATENCY 0x003f 971 #define cfgBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST 0x0048 972 #define cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID_W 0x004c 973 #define cfgBIF_CFG_DEV0_EPF1_PMI_CAP_LIST 0x0050 974 #define cfgBIF_CFG_DEV0_EPF1_PMI_CAP 0x0052 975 #define cfgBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL 0x0054 976 #define cfgBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST 0x0064 977 #define cfgBIF_CFG_DEV0_EPF1_PCIE_CAP 0x0066 978 #define cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP 0x0068 979 #define cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL 0x006c 980 #define cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS 0x006e 981 #define cfgBIF_CFG_DEV0_EPF1_LINK_CAP 0x0070 982 #define cfgBIF_CFG_DEV0_EPF1_LINK_CNTL 0x0074 983 #define cfgBIF_CFG_DEV0_EPF1_LINK_STATUS 0x0076 984 #define cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP2 0x0088 985 #define cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL2 0x008c 986 #define cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS2 0x008e 987 #define cfgBIF_CFG_DEV0_EPF1_LINK_CAP2 0x0090 988 #define cfgBIF_CFG_DEV0_EPF1_LINK_CNTL2 0x0094 989 #define cfgBIF_CFG_DEV0_EPF1_LINK_STATUS2 0x0096 990 #define cfgBIF_CFG_DEV0_EPF1_MSI_CAP_LIST 0x00a0 991 #define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL 0x00a2 992 #define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO 0x00a4 993 #define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI 0x00a8 994 #define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA 0x00a8 995 #define cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA 0x00aa 996 #define cfgBIF_CFG_DEV0_EPF1_MSI_MASK 0x00ac 997 #define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 0x00ac 998 #define cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 0x00ae 999 #define cfgBIF_CFG_DEV0_EPF1_MSI_MASK_64 0x00b0 1000 #define cfgBIF_CFG_DEV0_EPF1_MSI_PENDING 0x00b0 1001 #define cfgBIF_CFG_DEV0_EPF1_MSI_PENDING_64 0x00b4 1002 #define cfgBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST 0x00c0 1003 #define cfgBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL 0x00c2 1004 #define cfgBIF_CFG_DEV0_EPF1_MSIX_TABLE 0x00c4 1005 #define cfgBIF_CFG_DEV0_EPF1_MSIX_PBA 0x00c8 1006 #define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1007 #define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1008 #define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 0x0108 1009 #define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 0x010c 1010 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 1011 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1 0x0144 1012 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2 0x0148 1013 #define cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1014 #define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS 0x0154 1015 #define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK 0x0158 1016 #define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY 0x015c 1017 #define cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS 0x0160 1018 #define cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK 0x0164 1019 #define cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL 0x0168 1020 #define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 0x016c 1021 #define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 0x0170 1022 #define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 0x0174 1023 #define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 0x0178 1024 #define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 0x0188 1025 #define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 0x018c 1026 #define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 0x0190 1027 #define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 0x0194 1028 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST 0x0200 1029 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP 0x0204 1030 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL 0x0208 1031 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP 0x020c 1032 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL 0x0210 1033 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP 0x0214 1034 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL 0x0218 1035 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP 0x021c 1036 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL 0x0220 1037 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP 0x0224 1038 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL 0x0228 1039 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP 0x022c 1040 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL 0x0230 1041 #define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 1042 #define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 1043 #define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA 0x0248 1044 #define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP 0x024c 1045 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST 0x0250 1046 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP 0x0254 1047 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR 0x0258 1048 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS 0x025c 1049 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL 0x025e 1050 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 1051 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 1052 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 1053 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 1054 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 1055 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 1056 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 1057 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 1058 #define cfgBIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 1059 #define cfgBIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3 0x0274 1060 #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS 0x0278 1061 #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 1062 #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 1063 #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 1064 #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 1065 #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 1066 #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 1067 #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 1068 #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 1069 #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 1070 #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 1071 #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 1072 #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 1073 #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 1074 #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 1075 #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 1076 #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 1077 #define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST 0x02a0 1078 #define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP 0x02a4 1079 #define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL 0x02a6 1080 #define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST 0x02d0 1081 #define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP 0x02d4 1082 #define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL 0x02d6 1083 #define cfgBIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST 0x0320 1084 #define cfgBIF_CFG_DEV0_EPF1_PCIE_LTR_CAP 0x0324 1085 #define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST 0x0328 1086 #define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP 0x032c 1087 #define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL 0x032e 1088 #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST 0x0330 1089 #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP 0x0334 1090 #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL 0x0338 1091 #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS 0x033a 1092 #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS 0x033c 1093 #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS 0x033e 1094 #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS 0x0340 1095 #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 1096 #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 1097 #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE 0x0346 1098 #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID 0x034a 1099 #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c 1100 #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 1101 #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 1102 #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 1103 #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c 1104 #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 1105 #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 1106 #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 1107 #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c 1108 #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0 1109 #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP 0x04c4 1110 #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8 1111 #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP 0x04cc 1112 #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0 1113 #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP 0x04d4 1114 #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8 1115 #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP 0x04dc 1116 #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0 1117 #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP 0x04e4 1118 #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8 1119 #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP 0x04ec 1120 #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0 1121 1122 1123 // addressBlock: nbif_bif_bx_pf_SYSPFVFDEC 1124 // base address: 0x0 1125 #define regBIF_BX_PF0_MM_INDEX 0x0000 1126 #define regBIF_BX_PF0_MM_INDEX_BASE_IDX 0 1127 #define regBIF_BX_PF0_MM_DATA 0x0001 1128 #define regBIF_BX_PF0_MM_DATA_BASE_IDX 0 1129 #define regBIF_BX_PF0_MM_INDEX_HI 0x0006 1130 #define regBIF_BX_PF0_MM_INDEX_HI_BASE_IDX 0 1131 #define regBIF_BX_PF0_RSMU_INDEX 0x0000 1132 #define regBIF_BX_PF0_RSMU_INDEX_BASE_IDX 1 1133 #define regBIF_BX_PF0_RSMU_DATA 0x0001 1134 #define regBIF_BX_PF0_RSMU_DATA_BASE_IDX 1 1135 #define regBIF_BX_PF0_RSMU_INDEX_HI 0x0002 1136 #define regBIF_BX_PF0_RSMU_INDEX_HI_BASE_IDX 1 1137 1138 1139 // addressBlock: nbif_bif_bx_SYSDEC 1140 // base address: 0x0 1141 #define regBIF_BX0_PCIE_INDEX 0x000c 1142 #define regBIF_BX0_PCIE_INDEX_BASE_IDX 0 1143 #define regBIF_BX0_PCIE_DATA 0x000d 1144 #define regBIF_BX0_PCIE_DATA_BASE_IDX 0 1145 #define regBIF_BX0_PCIE_INDEX2 0x000e 1146 #define regBIF_BX0_PCIE_INDEX2_BASE_IDX 0 1147 #define regBIF_BX0_PCIE_DATA2 0x000f 1148 #define regBIF_BX0_PCIE_DATA2_BASE_IDX 0 1149 #define regBIF_BX0_PCIE_INDEX_HI 0x0010 1150 #define regBIF_BX0_PCIE_INDEX_HI_BASE_IDX 0 1151 #define regBIF_BX0_PCIE_INDEX2_HI 0x0011 1152 #define regBIF_BX0_PCIE_INDEX2_HI_BASE_IDX 0 1153 #define regBIF_BX0_SBIOS_SCRATCH_0 0x0034 1154 #define regBIF_BX0_SBIOS_SCRATCH_0_BASE_IDX 1 1155 #define regBIF_BX0_SBIOS_SCRATCH_1 0x0035 1156 #define regBIF_BX0_SBIOS_SCRATCH_1_BASE_IDX 1 1157 #define regBIF_BX0_SBIOS_SCRATCH_2 0x0036 1158 #define regBIF_BX0_SBIOS_SCRATCH_2_BASE_IDX 1 1159 #define regBIF_BX0_SBIOS_SCRATCH_3 0x0037 1160 #define regBIF_BX0_SBIOS_SCRATCH_3_BASE_IDX 1 1161 #define regBIF_BX0_BIOS_SCRATCH_0 0x0038 1162 #define regBIF_BX0_BIOS_SCRATCH_0_BASE_IDX 1 1163 #define regBIF_BX0_BIOS_SCRATCH_1 0x0039 1164 #define regBIF_BX0_BIOS_SCRATCH_1_BASE_IDX 1 1165 #define regBIF_BX0_BIOS_SCRATCH_2 0x003a 1166 #define regBIF_BX0_BIOS_SCRATCH_2_BASE_IDX 1 1167 #define regBIF_BX0_BIOS_SCRATCH_3 0x003b 1168 #define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX 1 1169 #define regBIF_BX0_BIOS_SCRATCH_4 0x003c 1170 #define regBIF_BX0_BIOS_SCRATCH_4_BASE_IDX 1 1171 #define regBIF_BX0_BIOS_SCRATCH_5 0x003d 1172 #define regBIF_BX0_BIOS_SCRATCH_5_BASE_IDX 1 1173 #define regBIF_BX0_BIOS_SCRATCH_6 0x003e 1174 #define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX 1 1175 #define regBIF_BX0_BIOS_SCRATCH_7 0x003f 1176 #define regBIF_BX0_BIOS_SCRATCH_7_BASE_IDX 1 1177 #define regBIF_BX0_BIOS_SCRATCH_8 0x0040 1178 #define regBIF_BX0_BIOS_SCRATCH_8_BASE_IDX 1 1179 #define regBIF_BX0_BIOS_SCRATCH_9 0x0041 1180 #define regBIF_BX0_BIOS_SCRATCH_9_BASE_IDX 1 1181 #define regBIF_BX0_BIOS_SCRATCH_10 0x0042 1182 #define regBIF_BX0_BIOS_SCRATCH_10_BASE_IDX 1 1183 #define regBIF_BX0_BIOS_SCRATCH_11 0x0043 1184 #define regBIF_BX0_BIOS_SCRATCH_11_BASE_IDX 1 1185 #define regBIF_BX0_BIOS_SCRATCH_12 0x0044 1186 #define regBIF_BX0_BIOS_SCRATCH_12_BASE_IDX 1 1187 #define regBIF_BX0_BIOS_SCRATCH_13 0x0045 1188 #define regBIF_BX0_BIOS_SCRATCH_13_BASE_IDX 1 1189 #define regBIF_BX0_BIOS_SCRATCH_14 0x0046 1190 #define regBIF_BX0_BIOS_SCRATCH_14_BASE_IDX 1 1191 #define regBIF_BX0_BIOS_SCRATCH_15 0x0047 1192 #define regBIF_BX0_BIOS_SCRATCH_15_BASE_IDX 1 1193 #define regBIF_BX0_BIF_RLC_INTR_CNTL 0x004c 1194 #define regBIF_BX0_BIF_RLC_INTR_CNTL_BASE_IDX 1 1195 #define regBIF_BX0_BIF_VCE_INTR_CNTL 0x004d 1196 #define regBIF_BX0_BIF_VCE_INTR_CNTL_BASE_IDX 1 1197 #define regBIF_BX0_BIF_UVD_INTR_CNTL 0x004e 1198 #define regBIF_BX0_BIF_UVD_INTR_CNTL_BASE_IDX 1 1199 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0 0x006c 1200 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 1 1201 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 0x006d 1202 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1 1203 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1 0x006e 1204 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 1 1205 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 0x006f 1206 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1 1207 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2 0x0070 1208 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 1 1209 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 0x0071 1210 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1 1211 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3 0x0072 1212 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 1 1213 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 0x0073 1214 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1 1215 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4 0x0074 1216 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 1 1217 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 0x0075 1218 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1 1219 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5 0x0076 1220 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 1 1221 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 0x0077 1222 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1 1223 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6 0x0078 1224 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 1 1225 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 0x0079 1226 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1 1227 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7 0x007a 1228 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 1 1229 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 0x007b 1230 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1 1231 #define regBIF_BX0_GFX_MMIOREG_CAM_CNTL 0x007c 1232 #define regBIF_BX0_GFX_MMIOREG_CAM_CNTL_BASE_IDX 1 1233 #define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL 0x007d 1234 #define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1 1235 #define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL 0x007e 1236 #define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1 1237 #define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f 1238 #define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1 1239 #define regBIF_BX0_DRIVER_SCRATCH_0 0x0080 1240 #define regBIF_BX0_DRIVER_SCRATCH_0_BASE_IDX 1 1241 #define regBIF_BX0_DRIVER_SCRATCH_1 0x0081 1242 #define regBIF_BX0_DRIVER_SCRATCH_1_BASE_IDX 1 1243 #define regBIF_BX0_DRIVER_SCRATCH_2 0x0082 1244 #define regBIF_BX0_DRIVER_SCRATCH_2_BASE_IDX 1 1245 #define regBIF_BX0_DRIVER_SCRATCH_3 0x0083 1246 #define regBIF_BX0_DRIVER_SCRATCH_3_BASE_IDX 1 1247 #define regBIF_BX0_DRIVER_SCRATCH_4 0x0084 1248 #define regBIF_BX0_DRIVER_SCRATCH_4_BASE_IDX 1 1249 #define regBIF_BX0_DRIVER_SCRATCH_5 0x0085 1250 #define regBIF_BX0_DRIVER_SCRATCH_5_BASE_IDX 1 1251 #define regBIF_BX0_DRIVER_SCRATCH_6 0x0086 1252 #define regBIF_BX0_DRIVER_SCRATCH_6_BASE_IDX 1 1253 #define regBIF_BX0_DRIVER_SCRATCH_7 0x0087 1254 #define regBIF_BX0_DRIVER_SCRATCH_7_BASE_IDX 1 1255 #define regBIF_BX0_DRIVER_SCRATCH_8 0x0088 1256 #define regBIF_BX0_DRIVER_SCRATCH_8_BASE_IDX 1 1257 #define regBIF_BX0_DRIVER_SCRATCH_9 0x0089 1258 #define regBIF_BX0_DRIVER_SCRATCH_9_BASE_IDX 1 1259 #define regBIF_BX0_DRIVER_SCRATCH_10 0x008a 1260 #define regBIF_BX0_DRIVER_SCRATCH_10_BASE_IDX 1 1261 #define regBIF_BX0_DRIVER_SCRATCH_11 0x008b 1262 #define regBIF_BX0_DRIVER_SCRATCH_11_BASE_IDX 1 1263 #define regBIF_BX0_DRIVER_SCRATCH_12 0x008c 1264 #define regBIF_BX0_DRIVER_SCRATCH_12_BASE_IDX 1 1265 #define regBIF_BX0_DRIVER_SCRATCH_13 0x008d 1266 #define regBIF_BX0_DRIVER_SCRATCH_13_BASE_IDX 1 1267 #define regBIF_BX0_DRIVER_SCRATCH_14 0x008e 1268 #define regBIF_BX0_DRIVER_SCRATCH_14_BASE_IDX 1 1269 #define regBIF_BX0_DRIVER_SCRATCH_15 0x008f 1270 #define regBIF_BX0_DRIVER_SCRATCH_15_BASE_IDX 1 1271 #define regBIF_BX0_FW_SCRATCH_0 0x0090 1272 #define regBIF_BX0_FW_SCRATCH_0_BASE_IDX 1 1273 #define regBIF_BX0_FW_SCRATCH_1 0x0091 1274 #define regBIF_BX0_FW_SCRATCH_1_BASE_IDX 1 1275 #define regBIF_BX0_FW_SCRATCH_2 0x0092 1276 #define regBIF_BX0_FW_SCRATCH_2_BASE_IDX 1 1277 #define regBIF_BX0_FW_SCRATCH_3 0x0093 1278 #define regBIF_BX0_FW_SCRATCH_3_BASE_IDX 1 1279 #define regBIF_BX0_FW_SCRATCH_4 0x0094 1280 #define regBIF_BX0_FW_SCRATCH_4_BASE_IDX 1 1281 #define regBIF_BX0_FW_SCRATCH_5 0x0095 1282 #define regBIF_BX0_FW_SCRATCH_5_BASE_IDX 1 1283 #define regBIF_BX0_FW_SCRATCH_6 0x0096 1284 #define regBIF_BX0_FW_SCRATCH_6_BASE_IDX 1 1285 #define regBIF_BX0_FW_SCRATCH_7 0x0097 1286 #define regBIF_BX0_FW_SCRATCH_7_BASE_IDX 1 1287 #define regBIF_BX0_FW_SCRATCH_8 0x0098 1288 #define regBIF_BX0_FW_SCRATCH_8_BASE_IDX 1 1289 #define regBIF_BX0_FW_SCRATCH_9 0x0099 1290 #define regBIF_BX0_FW_SCRATCH_9_BASE_IDX 1 1291 #define regBIF_BX0_FW_SCRATCH_10 0x009a 1292 #define regBIF_BX0_FW_SCRATCH_10_BASE_IDX 1 1293 #define regBIF_BX0_FW_SCRATCH_11 0x009b 1294 #define regBIF_BX0_FW_SCRATCH_11_BASE_IDX 1 1295 #define regBIF_BX0_FW_SCRATCH_12 0x009c 1296 #define regBIF_BX0_FW_SCRATCH_12_BASE_IDX 1 1297 #define regBIF_BX0_FW_SCRATCH_13 0x009d 1298 #define regBIF_BX0_FW_SCRATCH_13_BASE_IDX 1 1299 #define regBIF_BX0_FW_SCRATCH_14 0x009e 1300 #define regBIF_BX0_FW_SCRATCH_14_BASE_IDX 1 1301 #define regBIF_BX0_FW_SCRATCH_15 0x009f 1302 #define regBIF_BX0_FW_SCRATCH_15_BASE_IDX 1 1303 #define regBIF_BX0_SBIOS_SCRATCH_4 0x00a0 1304 #define regBIF_BX0_SBIOS_SCRATCH_4_BASE_IDX 1 1305 #define regBIF_BX0_SBIOS_SCRATCH_5 0x00a1 1306 #define regBIF_BX0_SBIOS_SCRATCH_5_BASE_IDX 1 1307 #define regBIF_BX0_SBIOS_SCRATCH_6 0x00a2 1308 #define regBIF_BX0_SBIOS_SCRATCH_6_BASE_IDX 1 1309 #define regBIF_BX0_SBIOS_SCRATCH_7 0x00a3 1310 #define regBIF_BX0_SBIOS_SCRATCH_7_BASE_IDX 1 1311 #define regBIF_BX0_SBIOS_SCRATCH_8 0x00a4 1312 #define regBIF_BX0_SBIOS_SCRATCH_8_BASE_IDX 1 1313 #define regBIF_BX0_SBIOS_SCRATCH_9 0x00a5 1314 #define regBIF_BX0_SBIOS_SCRATCH_9_BASE_IDX 1 1315 #define regBIF_BX0_SBIOS_SCRATCH_10 0x00a6 1316 #define regBIF_BX0_SBIOS_SCRATCH_10_BASE_IDX 1 1317 #define regBIF_BX0_SBIOS_SCRATCH_11 0x00a7 1318 #define regBIF_BX0_SBIOS_SCRATCH_11_BASE_IDX 1 1319 #define regBIF_BX0_SBIOS_SCRATCH_12 0x00a8 1320 #define regBIF_BX0_SBIOS_SCRATCH_12_BASE_IDX 1 1321 #define regBIF_BX0_SBIOS_SCRATCH_13 0x00a9 1322 #define regBIF_BX0_SBIOS_SCRATCH_13_BASE_IDX 1 1323 #define regBIF_BX0_SBIOS_SCRATCH_14 0x00aa 1324 #define regBIF_BX0_SBIOS_SCRATCH_14_BASE_IDX 1 1325 #define regBIF_BX0_SBIOS_SCRATCH_15 0x00ab 1326 #define regBIF_BX0_SBIOS_SCRATCH_15_BASE_IDX 1 1327 1328 1329 // addressBlock: nbif_rcc_dwn_dev0_BIFDEC1 1330 // base address: 0x0 1331 #define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED 0x0060 1332 #define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED_BASE_IDX 2 1333 #define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH 0x0061 1334 #define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_BASE_IDX 2 1335 #define regRCC_DWN_DEV0_0_DN_PCIE_CNTL 0x0063 1336 #define regRCC_DWN_DEV0_0_DN_PCIE_CNTL_BASE_IDX 2 1337 #define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL 0x0064 1338 #define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_BASE_IDX 2 1339 #define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 0x0065 1340 #define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_BASE_IDX 2 1341 #define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL 0x0066 1342 #define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_BASE_IDX 2 1343 #define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL 0x0067 1344 #define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_BASE_IDX 2 1345 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 0x0068 1346 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_BASE_IDX 2 1347 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC 0x0069 1348 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_BASE_IDX 2 1349 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 0x006a 1350 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_BASE_IDX 2 1351 1352 1353 // addressBlock: nbif_rcc_dwnp_dev0_BIFDEC1 1354 // base address: 0x0 1355 #define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL 0x006c 1356 #define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_BASE_IDX 2 1357 #define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL 0x006d 1358 #define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL_BASE_IDX 2 1359 #define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL 0x006e 1360 #define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_BASE_IDX 2 1361 #define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2 0x006f 1362 #define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_BASE_IDX 2 1363 #define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC 0x0070 1364 #define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_BASE_IDX 2 1365 #define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP 0x0071 1366 #define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_BASE_IDX 2 1367 1368 1369 // addressBlock: nbif_rcc_ep_dev0_BIFDEC1 1370 // base address: 0x0 1371 #define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH 0x0041 1372 #define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH_BASE_IDX 2 1373 #define regRCC_EP_DEV0_0_EP_PCIE_CNTL 0x0043 1374 #define regRCC_EP_DEV0_0_EP_PCIE_CNTL_BASE_IDX 2 1375 #define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL 0x0044 1376 #define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_BASE_IDX 2 1377 #define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS 0x0045 1378 #define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_BASE_IDX 2 1379 #define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 0x0046 1380 #define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_BASE_IDX 2 1381 #define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL 0x0047 1382 #define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_BASE_IDX 2 1383 #define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL 0x0048 1384 #define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_BASE_IDX 2 1385 #define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x004a 1386 #define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_BASE_IDX 2 1387 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x004b 1388 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 1389 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x004b 1390 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 1391 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x004b 1392 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 1393 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x004b 1394 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 1395 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x004c 1396 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 1397 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x004c 1398 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 1399 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x004c 1400 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 1401 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x004c 1402 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 1403 #define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC 0x004d 1404 #define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_BASE_IDX 2 1405 #define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 0x004e 1406 #define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_BASE_IDX 2 1407 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP 0x0050 1408 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_BASE_IDX 2 1409 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0051 1410 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2 1411 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL 0x0051 1412 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_BASE_IDX 2 1413 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0051 1414 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 1415 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0052 1416 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 1417 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0052 1418 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 1419 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0052 1420 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 1421 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0052 1422 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 1423 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0053 1424 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 1425 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0053 1426 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 1427 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0053 1428 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 1429 #define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL 0x0053 1430 #define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_BASE_IDX 2 1431 #define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED 0x0054 1432 #define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED_BASE_IDX 2 1433 #define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL 0x0056 1434 #define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_BASE_IDX 2 1435 #define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID 0x0057 1436 #define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 2 1437 #define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL 0x0058 1438 #define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_BASE_IDX 2 1439 #define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL 0x0059 1440 #define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_BASE_IDX 2 1441 #define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL 0x005a 1442 #define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 2 1443 1444 1445 // addressBlock: nbif_bif_bx_BIFDEC1 1446 // base address: 0x0 1447 #define regBIF_BX0_CC_BIF_BX_STRAP0 0x00e2 1448 #define regBIF_BX0_CC_BIF_BX_STRAP0_BASE_IDX 2 1449 #define regBIF_BX0_CC_BIF_BX_PINSTRAP0 0x00e4 1450 #define regBIF_BX0_CC_BIF_BX_PINSTRAP0_BASE_IDX 2 1451 #define regBIF_BX0_BIF_MM_INDACCESS_CNTL 0x00e6 1452 #define regBIF_BX0_BIF_MM_INDACCESS_CNTL_BASE_IDX 2 1453 #define regBIF_BX0_BUS_CNTL 0x00e7 1454 #define regBIF_BX0_BUS_CNTL_BASE_IDX 2 1455 #define regBIF_BX0_BIF_SCRATCH0 0x00e8 1456 #define regBIF_BX0_BIF_SCRATCH0_BASE_IDX 2 1457 #define regBIF_BX0_BIF_SCRATCH1 0x00e9 1458 #define regBIF_BX0_BIF_SCRATCH1_BASE_IDX 2 1459 #define regBIF_BX0_BX_RESET_EN 0x00ed 1460 #define regBIF_BX0_BX_RESET_EN_BASE_IDX 2 1461 #define regBIF_BX0_MM_CFGREGS_CNTL 0x00ee 1462 #define regBIF_BX0_MM_CFGREGS_CNTL_BASE_IDX 2 1463 #define regBIF_BX0_BX_RESET_CNTL 0x00f0 1464 #define regBIF_BX0_BX_RESET_CNTL_BASE_IDX 2 1465 #define regBIF_BX0_INTERRUPT_CNTL 0x00f1 1466 #define regBIF_BX0_INTERRUPT_CNTL_BASE_IDX 2 1467 #define regBIF_BX0_INTERRUPT_CNTL2 0x00f2 1468 #define regBIF_BX0_INTERRUPT_CNTL2_BASE_IDX 2 1469 #define regBIF_BX0_CLKREQB_PAD_CNTL 0x00f8 1470 #define regBIF_BX0_CLKREQB_PAD_CNTL_BASE_IDX 2 1471 #define regBIF_BX0_BIF_FEATURES_CONTROL_MISC 0x00fb 1472 #define regBIF_BX0_BIF_FEATURES_CONTROL_MISC_BASE_IDX 2 1473 #define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC 0x00fc 1474 #define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 2 1475 #define regBIF_BX0_BIF_DOORBELL_CNTL 0x00fd 1476 #define regBIF_BX0_BIF_DOORBELL_CNTL_BASE_IDX 2 1477 #define regBIF_BX0_BIF_DOORBELL_INT_CNTL 0x00fe 1478 #define regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX 2 1479 #define regBIF_BX0_BIF_FB_EN 0x0100 1480 #define regBIF_BX0_BIF_FB_EN_BASE_IDX 2 1481 #define regBIF_BX0_BIF_INTR_CNTL 0x0101 1482 #define regBIF_BX0_BIF_INTR_CNTL_BASE_IDX 2 1483 #define regBIF_BX0_BIF_MST_TRANS_PENDING_VF 0x0109 1484 #define regBIF_BX0_BIF_MST_TRANS_PENDING_VF_BASE_IDX 2 1485 #define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF 0x010a 1486 #define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 2 1487 #define regBIF_BX0_BACO_CNTL 0x010b 1488 #define regBIF_BX0_BACO_CNTL_BASE_IDX 2 1489 #define regBIF_BX0_BIF_BACO_EXIT_TIME0 0x010c 1490 #define regBIF_BX0_BIF_BACO_EXIT_TIME0_BASE_IDX 2 1491 #define regBIF_BX0_BIF_BACO_EXIT_TIMER1 0x010d 1492 #define regBIF_BX0_BIF_BACO_EXIT_TIMER1_BASE_IDX 2 1493 #define regBIF_BX0_BIF_BACO_EXIT_TIMER2 0x010e 1494 #define regBIF_BX0_BIF_BACO_EXIT_TIMER2_BASE_IDX 2 1495 #define regBIF_BX0_BIF_BACO_EXIT_TIMER3 0x010f 1496 #define regBIF_BX0_BIF_BACO_EXIT_TIMER3_BASE_IDX 2 1497 #define regBIF_BX0_BIF_BACO_EXIT_TIMER4 0x0110 1498 #define regBIF_BX0_BIF_BACO_EXIT_TIMER4_BASE_IDX 2 1499 #define regBIF_BX0_MEM_TYPE_CNTL 0x0111 1500 #define regBIF_BX0_MEM_TYPE_CNTL_BASE_IDX 2 1501 #define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL 0x012d 1502 #define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2 1503 #define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL 0x012e 1504 #define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2 1505 #define regBIF_BX0_BIF_RB_CNTL 0x012f 1506 #define regBIF_BX0_BIF_RB_CNTL_BASE_IDX 2 1507 #define regBIF_BX0_BIF_RB_BASE 0x0130 1508 #define regBIF_BX0_BIF_RB_BASE_BASE_IDX 2 1509 #define regBIF_BX0_BIF_RB_RPTR 0x0131 1510 #define regBIF_BX0_BIF_RB_RPTR_BASE_IDX 2 1511 #define regBIF_BX0_BIF_RB_WPTR 0x0132 1512 #define regBIF_BX0_BIF_RB_WPTR_BASE_IDX 2 1513 #define regBIF_BX0_BIF_RB_WPTR_ADDR_HI 0x0133 1514 #define regBIF_BX0_BIF_RB_WPTR_ADDR_HI_BASE_IDX 2 1515 #define regBIF_BX0_BIF_RB_WPTR_ADDR_LO 0x0134 1516 #define regBIF_BX0_BIF_RB_WPTR_ADDR_LO_BASE_IDX 2 1517 #define regBIF_BX0_MAILBOX_INDEX 0x0135 1518 #define regBIF_BX0_MAILBOX_INDEX_BASE_IDX 2 1519 #define regBIF_BX0_BIF_MP1_INTR_CTRL 0x0142 1520 #define regBIF_BX0_BIF_MP1_INTR_CTRL_BASE_IDX 2 1521 #define regBIF_BX0_BIF_PERSTB_PAD_CNTL 0x0145 1522 #define regBIF_BX0_BIF_PERSTB_PAD_CNTL_BASE_IDX 2 1523 #define regBIF_BX0_BIF_PX_EN_PAD_CNTL 0x0146 1524 #define regBIF_BX0_BIF_PX_EN_PAD_CNTL_BASE_IDX 2 1525 #define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL 0x0147 1526 #define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 2 1527 #define regBIF_BX0_BIF_CLKREQB_PAD_CNTL 0x0148 1528 #define regBIF_BX0_BIF_CLKREQB_PAD_CNTL_BASE_IDX 2 1529 #define regBIF_BX0_BIF_PWRBRK_PAD_CNTL 0x0149 1530 #define regBIF_BX0_BIF_PWRBRK_PAD_CNTL_BASE_IDX 2 1531 1532 1533 // addressBlock: nbif_rcc_dev0_BIFDEC1 1534 // base address: 0x0 1535 #define regRCC_DEV0_0_RCC_ERR_INT_CNTL 0x0086 1536 #define regRCC_DEV0_0_RCC_ERR_INT_CNTL_BASE_IDX 2 1537 #define regRCC_DEV0_0_RCC_BACO_CNTL_MISC 0x0087 1538 #define regRCC_DEV0_0_RCC_BACO_CNTL_MISC_BASE_IDX 2 1539 #define regRCC_DEV0_0_RCC_RESET_EN 0x0088 1540 #define regRCC_DEV0_0_RCC_RESET_EN_BASE_IDX 2 1541 #define regRCC_DEV0_0_RCC_VDM_SUPPORT 0x0089 1542 #define regRCC_DEV0_0_RCC_VDM_SUPPORT_BASE_IDX 2 1543 #define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 0x008a 1544 #define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 2 1545 #define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 0x008b 1546 #define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 2 1547 #define regRCC_DEV0_0_RCC_GPUIOV_REGION 0x008c 1548 #define regRCC_DEV0_0_RCC_GPUIOV_REGION_BASE_IDX 2 1549 #define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN 0x008d 1550 #define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN_BASE_IDX 2 1551 #define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL 0x008e 1552 #define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 2 1553 #define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x008f 1554 #define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 2 1555 #define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE 0x008f 1556 #define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 2 1557 #define regRCC_DEV0_0_RCC_PEER_REG_RANGE0 0x00be 1558 #define regRCC_DEV0_0_RCC_PEER_REG_RANGE0_BASE_IDX 2 1559 #define regRCC_DEV0_0_RCC_PEER_REG_RANGE1 0x00bf 1560 #define regRCC_DEV0_0_RCC_PEER_REG_RANGE1_BASE_IDX 2 1561 #define regRCC_DEV0_0_RCC_BUS_CNTL 0x00c1 1562 #define regRCC_DEV0_0_RCC_BUS_CNTL_BASE_IDX 2 1563 #define regRCC_DEV0_0_RCC_CONFIG_CNTL 0x00c2 1564 #define regRCC_DEV0_0_RCC_CONFIG_CNTL_BASE_IDX 2 1565 #define regRCC_DEV0_0_RCC_CONFIG_F0_BASE 0x00c6 1566 #define regRCC_DEV0_0_RCC_CONFIG_F0_BASE_BASE_IDX 2 1567 #define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE 0x00c7 1568 #define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE_BASE_IDX 2 1569 #define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE 0x00c8 1570 #define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 2 1571 #define regRCC_DEV0_0_RCC_XDMA_LO 0x00c9 1572 #define regRCC_DEV0_0_RCC_XDMA_LO_BASE_IDX 2 1573 #define regRCC_DEV0_0_RCC_XDMA_HI 0x00ca 1574 #define regRCC_DEV0_0_RCC_XDMA_HI_BASE_IDX 2 1575 #define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC 0x00cb 1576 #define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_BASE_IDX 2 1577 #define regRCC_DEV0_0_RCC_BUSNUM_CNTL1 0x00cc 1578 #define regRCC_DEV0_0_RCC_BUSNUM_CNTL1_BASE_IDX 2 1579 #define regRCC_DEV0_0_RCC_BUSNUM_LIST0 0x00cd 1580 #define regRCC_DEV0_0_RCC_BUSNUM_LIST0_BASE_IDX 2 1581 #define regRCC_DEV0_0_RCC_BUSNUM_LIST1 0x00ce 1582 #define regRCC_DEV0_0_RCC_BUSNUM_LIST1_BASE_IDX 2 1583 #define regRCC_DEV0_0_RCC_BUSNUM_CNTL2 0x00cf 1584 #define regRCC_DEV0_0_RCC_BUSNUM_CNTL2_BASE_IDX 2 1585 #define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM 0x00d0 1586 #define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2 1587 #define regRCC_DEV0_0_RCC_HOST_BUSNUM 0x00d1 1588 #define regRCC_DEV0_0_RCC_HOST_BUSNUM_BASE_IDX 2 1589 #define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI 0x00d2 1590 #define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 2 1591 #define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO 0x00d3 1592 #define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 2 1593 #define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI 0x00d4 1594 #define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 2 1595 #define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO 0x00d5 1596 #define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 2 1597 #define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI 0x00d6 1598 #define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 2 1599 #define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO 0x00d7 1600 #define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 2 1601 #define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI 0x00d8 1602 #define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 2 1603 #define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO 0x00d9 1604 #define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 2 1605 #define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0 0x00da 1606 #define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0_BASE_IDX 2 1607 #define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1 0x00db 1608 #define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1_BASE_IDX 2 1609 #define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL 0x00dd 1610 #define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL_BASE_IDX 2 1611 #define regRCC_DEV0_0_RCC_CMN_LINK_CNTL 0x00de 1612 #define regRCC_DEV0_0_RCC_CMN_LINK_CNTL_BASE_IDX 2 1613 #define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE 0x00df 1614 #define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 2 1615 #define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL 0x00e0 1616 #define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_BASE_IDX 2 1617 #define regRCC_DEV0_0_RCC_MH_ARB_CNTL 0x00e1 1618 #define regRCC_DEV0_0_RCC_MH_ARB_CNTL_BASE_IDX 2 1619 1620 1621 // addressBlock: nbif_rcc_dev0_epf0_BIFDEC2 1622 // base address: 0x0 1623 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO 0x0400 1624 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 1625 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI 0x0401 1626 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 1627 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA 0x0402 1628 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 1629 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL 0x0403 1630 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 1631 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO 0x0404 1632 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 1633 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI 0x0405 1634 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 1635 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA 0x0406 1636 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 1637 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL 0x0407 1638 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 1639 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO 0x0408 1640 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 1641 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI 0x0409 1642 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 1643 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA 0x040a 1644 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 1645 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL 0x040b 1646 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 1647 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO 0x040c 1648 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 1649 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI 0x040d 1650 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 1651 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA 0x040e 1652 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 1653 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL 0x040f 1654 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 1655 #define regRCC_DEV0_EPF0_GFXMSIX_PBA 0x0800 1656 #define regRCC_DEV0_EPF0_GFXMSIX_PBA_BASE_IDX 3 1657 1658 1659 // addressBlock: nbif_rcc_strap_BIFDEC1 1660 // base address: 0x0 1661 #define regRCC_STRAP0_RCC_BIF_STRAP0 0x0000 1662 #define regRCC_STRAP0_RCC_BIF_STRAP0_BASE_IDX 2 1663 #define regRCC_STRAP0_RCC_BIF_STRAP1 0x0001 1664 #define regRCC_STRAP0_RCC_BIF_STRAP1_BASE_IDX 2 1665 #define regRCC_STRAP0_RCC_BIF_STRAP2 0x0005 1666 #define regRCC_STRAP0_RCC_BIF_STRAP2_BASE_IDX 2 1667 #define regRCC_STRAP0_RCC_BIF_STRAP3 0x0006 1668 #define regRCC_STRAP0_RCC_BIF_STRAP3_BASE_IDX 2 1669 #define regRCC_STRAP0_RCC_BIF_STRAP4 0x0007 1670 #define regRCC_STRAP0_RCC_BIF_STRAP4_BASE_IDX 2 1671 #define regRCC_STRAP0_RCC_BIF_STRAP5 0x0008 1672 #define regRCC_STRAP0_RCC_BIF_STRAP5_BASE_IDX 2 1673 #define regRCC_STRAP0_RCC_BIF_STRAP6 0x0009 1674 #define regRCC_STRAP0_RCC_BIF_STRAP6_BASE_IDX 2 1675 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0 0x000d 1676 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0_BASE_IDX 2 1677 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1 0x000e 1678 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1_BASE_IDX 2 1679 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10 0x000f 1680 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10_BASE_IDX 2 1681 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11 0x0010 1682 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11_BASE_IDX 2 1683 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12 0x0011 1684 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12_BASE_IDX 2 1685 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13 0x0012 1686 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13_BASE_IDX 2 1687 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14 0x0013 1688 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14_BASE_IDX 2 1689 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2 0x0014 1690 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2_BASE_IDX 2 1691 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3 0x0015 1692 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3_BASE_IDX 2 1693 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4 0x0016 1694 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4_BASE_IDX 2 1695 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5 0x0017 1696 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5_BASE_IDX 2 1697 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6 0x0018 1698 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6_BASE_IDX 2 1699 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7 0x0019 1700 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7_BASE_IDX 2 1701 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8 0x001a 1702 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8_BASE_IDX 2 1703 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9 0x001b 1704 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9_BASE_IDX 2 1705 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0 0x001c 1706 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_BASE_IDX 2 1707 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1 0x001d 1708 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_BASE_IDX 2 1709 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13 0x001e 1710 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_BASE_IDX 2 1711 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14 0x001f 1712 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14_BASE_IDX 2 1713 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15 0x0020 1714 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15_BASE_IDX 2 1715 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16 0x0021 1716 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16_BASE_IDX 2 1717 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17 0x0022 1718 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17_BASE_IDX 2 1719 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18 0x0023 1720 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18_BASE_IDX 2 1721 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2 0x0024 1722 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_BASE_IDX 2 1723 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3 0x0026 1724 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_BASE_IDX 2 1725 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4 0x0027 1726 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_BASE_IDX 2 1727 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5 0x0028 1728 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_BASE_IDX 2 1729 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8 0x0029 1730 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_BASE_IDX 2 1731 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9 0x002a 1732 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_BASE_IDX 2 1733 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0 0x002b 1734 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_BASE_IDX 2 1735 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2 0x0036 1736 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_BASE_IDX 2 1737 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20 0x0037 1738 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20_BASE_IDX 2 1739 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21 0x0038 1740 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21_BASE_IDX 2 1741 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3 0x0039 1742 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_BASE_IDX 2 1743 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4 0x003a 1744 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_BASE_IDX 2 1745 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5 0x003b 1746 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_BASE_IDX 2 1747 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6 0x003c 1748 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_BASE_IDX 2 1749 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7 0x003d 1750 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_BASE_IDX 2 1751 1752 1753 // addressBlock: nbif_bif_bx_pf_BIFPFVFDEC1 1754 // base address: 0x0 1755 #define regBIF_BX_PF0_BIF_BME_STATUS 0x00eb 1756 #define regBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX 2 1757 #define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG 0x00ec 1758 #define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 1759 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 1760 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 1761 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 1762 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 1763 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 1764 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 1765 #define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 1766 #define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 1767 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 1768 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 1769 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 1770 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 1771 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 1772 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 1773 #define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ 0x0106 1774 #define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 1775 #define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE 0x0107 1776 #define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 1777 #define regBIF_BX_PF0_BIF_TRANS_PENDING 0x0108 1778 #define regBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX 2 1779 #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 1780 #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 1781 #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 1782 #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 1783 #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 1784 #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 1785 #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 1786 #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 1787 #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 0x013a 1788 #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 1789 #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 0x013b 1790 #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 1791 #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 0x013c 1792 #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 1793 #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 0x013d 1794 #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 1795 #define regBIF_BX_PF0_MAILBOX_CONTROL 0x013e 1796 #define regBIF_BX_PF0_MAILBOX_CONTROL_BASE_IDX 2 1797 #define regBIF_BX_PF0_MAILBOX_INT_CNTL 0x013f 1798 #define regBIF_BX_PF0_MAILBOX_INT_CNTL_BASE_IDX 2 1799 #define regBIF_BX_PF0_BIF_VMHV_MAILBOX 0x0140 1800 #define regBIF_BX_PF0_BIF_VMHV_MAILBOX_BASE_IDX 2 1801 1802 1803 // addressBlock: nbif_rcc_dev0_epf0_BIFPFVFDEC1 1804 // base address: 0x0 1805 #define regRCC_DEV0_EPF0_RCC_ERR_LOG 0x0085 1806 #define regRCC_DEV0_EPF0_RCC_ERR_LOG_BASE_IDX 2 1807 #define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x00c0 1808 #define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 1809 #define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE 0x00c3 1810 #define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 1811 #define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED 0x00c4 1812 #define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_BASE_IDX 2 1813 #define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 1814 #define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 1815 1816 1817 // addressBlock: nbif_gdc_GDCDEC 1818 // base address: 0x0 1819 #define regGDC0_SHUB_REGS_IF_CTL 0x0181 1820 #define regGDC0_SHUB_REGS_IF_CTL_BASE_IDX 2 1821 #define regGDC0_A2S_QUEUE_FIFO_ARB_CNTL 0x0182 1822 #define regGDC0_A2S_QUEUE_FIFO_ARB_CNTL_BASE_IDX 2 1823 #define regGDC0_NGDC_MGCG_CTRL 0x0187 1824 #define regGDC0_NGDC_MGCG_CTRL_BASE_IDX 2 1825 #define regGDC0_S2A_MISC_CNTL 0x0188 1826 #define regGDC0_S2A_MISC_CNTL_BASE_IDX 2 1827 #define regGDC0_NGDC_PG_MISC_CTRL 0x0190 1828 #define regGDC0_NGDC_PG_MISC_CTRL_BASE_IDX 2 1829 #define regGDC0_NGDC_PGMST_CTRL 0x0191 1830 #define regGDC0_NGDC_PGMST_CTRL_BASE_IDX 2 1831 #define regGDC0_NGDC_PGSLV_CTRL 0x0192 1832 #define regGDC0_NGDC_PGSLV_CTRL_BASE_IDX 2 1833 #define regGDC0_ATDMA_MISC_CNTL 0x01e1 1834 #define regGDC0_ATDMA_MISC_CNTL_BASE_IDX 2 1835 1836 1837 // addressBlock: nbif_gdc_s2a_GDCS2A_DEC 1838 // base address: 0x0 1839 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL 0x01cb 1840 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX 2 1841 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL 0x01cc 1842 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX 2 1843 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL 0x01cd 1844 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX 2 1845 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL 0x01ce 1846 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX 2 1847 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL 0x01cf 1848 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX 2 1849 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL 0x01d0 1850 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX 2 1851 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL 0x01d1 1852 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX 2 1853 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL 0x01d2 1854 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX 2 1855 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL 0x01d3 1856 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX 2 1857 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL 0x01d4 1858 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX 2 1859 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL 0x01d5 1860 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX 2 1861 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL 0x01d6 1862 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX 2 1863 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL 0x01d7 1864 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX 2 1865 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL 0x01d8 1866 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX 2 1867 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL 0x01d9 1868 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX 2 1869 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL 0x01da 1870 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX 2 1871 #define regGDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG 0x01db 1872 #define regGDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX 2 1873 #define regGDC_S2A0_NBIF_GFX_DOORBELL_STATUS 0x01dc 1874 #define regGDC_S2A0_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 2 1875 1876 1877 // addressBlock: nbif_bif_cfg_dev0_rc_bifcfgdecp 1878 // base address: 0x10100000 1879 #define regIRQ_BRIDGE_CNTL 0x000f 1880 #define regIRQ_BRIDGE_CNTL_BASE_IDX 5 1881 1882 1883 // addressBlock: nbif_bif_cfg_dev0_epf0_bifcfgdecp 1884 // base address: 0x10140000 1885 #define regBIF_CFG_DEV0_EPF0_VENDOR_ID 0x10000 1886 #define regBIF_CFG_DEV0_EPF0_VENDOR_ID_BASE_IDX 5 1887 #define regBIF_CFG_DEV0_EPF0_DEVICE_ID 0x10000 1888 #define regBIF_CFG_DEV0_EPF0_DEVICE_ID_BASE_IDX 5 1889 #define regBIF_CFG_DEV0_EPF0_COMMAND 0x10001 1890 #define regBIF_CFG_DEV0_EPF0_COMMAND_BASE_IDX 5 1891 #define regBIF_CFG_DEV0_EPF0_STATUS 0x10001 1892 #define regBIF_CFG_DEV0_EPF0_STATUS_BASE_IDX 5 1893 #define regBIF_CFG_DEV0_EPF0_REVISION_ID 0x10002 1894 #define regBIF_CFG_DEV0_EPF0_REVISION_ID_BASE_IDX 5 1895 #define regBIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x10002 1896 #define regBIF_CFG_DEV0_EPF0_PROG_INTERFACE_BASE_IDX 5 1897 #define regBIF_CFG_DEV0_EPF0_SUB_CLASS 0x10002 1898 #define regBIF_CFG_DEV0_EPF0_SUB_CLASS_BASE_IDX 5 1899 #define regBIF_CFG_DEV0_EPF0_BASE_CLASS 0x10002 1900 #define regBIF_CFG_DEV0_EPF0_BASE_CLASS_BASE_IDX 5 1901 #define regBIF_CFG_DEV0_EPF0_CACHE_LINE 0x10003 1902 #define regBIF_CFG_DEV0_EPF0_CACHE_LINE_BASE_IDX 5 1903 #define regBIF_CFG_DEV0_EPF0_LATENCY 0x10003 1904 #define regBIF_CFG_DEV0_EPF0_LATENCY_BASE_IDX 5 1905 #define regBIF_CFG_DEV0_EPF0_HEADER 0x10003 1906 #define regBIF_CFG_DEV0_EPF0_HEADER_BASE_IDX 5 1907 #define regBIF_CFG_DEV0_EPF0_BIST 0x10003 1908 #define regBIF_CFG_DEV0_EPF0_BIST_BASE_IDX 5 1909 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_1 0x10004 1910 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_1_BASE_IDX 5 1911 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_2 0x10005 1912 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_2_BASE_IDX 5 1913 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_3 0x10006 1914 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_3_BASE_IDX 5 1915 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_4 0x10007 1916 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_4_BASE_IDX 5 1917 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_5 0x10008 1918 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_5_BASE_IDX 5 1919 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_6 0x10009 1920 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_6_BASE_IDX 5 1921 #define regBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR 0x1000a 1922 #define regBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR_BASE_IDX 5 1923 #define regBIF_CFG_DEV0_EPF0_ADAPTER_ID 0x1000b 1924 #define regBIF_CFG_DEV0_EPF0_ADAPTER_ID_BASE_IDX 5 1925 #define regBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR 0x1000c 1926 #define regBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR_BASE_IDX 5 1927 #define regBIF_CFG_DEV0_EPF0_CAP_PTR 0x1000d 1928 #define regBIF_CFG_DEV0_EPF0_CAP_PTR_BASE_IDX 5 1929 #define regBIF_CFG_DEV0_EPF0_INTERRUPT_LINE 0x1000f 1930 #define regBIF_CFG_DEV0_EPF0_INTERRUPT_LINE_BASE_IDX 5 1931 #define regBIF_CFG_DEV0_EPF0_INTERRUPT_PIN 0x1000f 1932 #define regBIF_CFG_DEV0_EPF0_INTERRUPT_PIN_BASE_IDX 5 1933 #define regBIF_CFG_DEV0_EPF0_MIN_GRANT 0x1000f 1934 #define regBIF_CFG_DEV0_EPF0_MIN_GRANT_BASE_IDX 5 1935 #define regBIF_CFG_DEV0_EPF0_MAX_LATENCY 0x1000f 1936 #define regBIF_CFG_DEV0_EPF0_MAX_LATENCY_BASE_IDX 5 1937 #define regBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST 0x10012 1938 #define regBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST_BASE_IDX 5 1939 #define regBIF_CFG_DEV0_EPF0_ADAPTER_ID_W 0x10013 1940 #define regBIF_CFG_DEV0_EPF0_ADAPTER_ID_W_BASE_IDX 5 1941 #define regBIF_CFG_DEV0_EPF0_PMI_CAP_LIST 0x10014 1942 #define regBIF_CFG_DEV0_EPF0_PMI_CAP_LIST_BASE_IDX 5 1943 #define regBIF_CFG_DEV0_EPF0_PMI_CAP 0x10014 1944 #define regBIF_CFG_DEV0_EPF0_PMI_CAP_BASE_IDX 5 1945 #define regBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL 0x10015 1946 #define regBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL_BASE_IDX 5 1947 #define regBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST 0x10019 1948 #define regBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST_BASE_IDX 5 1949 #define regBIF_CFG_DEV0_EPF0_PCIE_CAP 0x10019 1950 #define regBIF_CFG_DEV0_EPF0_PCIE_CAP_BASE_IDX 5 1951 #define regBIF_CFG_DEV0_EPF0_DEVICE_CAP 0x1001a 1952 #define regBIF_CFG_DEV0_EPF0_DEVICE_CAP_BASE_IDX 5 1953 #define regBIF_CFG_DEV0_EPF0_DEVICE_CNTL 0x1001b 1954 #define regBIF_CFG_DEV0_EPF0_DEVICE_CNTL_BASE_IDX 5 1955 #define regBIF_CFG_DEV0_EPF0_DEVICE_STATUS 0x1001b 1956 #define regBIF_CFG_DEV0_EPF0_DEVICE_STATUS_BASE_IDX 5 1957 #define regBIF_CFG_DEV0_EPF0_LINK_CAP 0x1001c 1958 #define regBIF_CFG_DEV0_EPF0_LINK_CAP_BASE_IDX 5 1959 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL 0x1001d 1960 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL_BASE_IDX 5 1961 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS 0x1001d 1962 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS_BASE_IDX 5 1963 #define regBIF_CFG_DEV0_EPF0_DEVICE_CAP2 0x10022 1964 #define regBIF_CFG_DEV0_EPF0_DEVICE_CAP2_BASE_IDX 5 1965 #define regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x10023 1966 #define regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2_BASE_IDX 5 1967 #define regBIF_CFG_DEV0_EPF0_DEVICE_STATUS2 0x10023 1968 #define regBIF_CFG_DEV0_EPF0_DEVICE_STATUS2_BASE_IDX 5 1969 #define regBIF_CFG_DEV0_EPF0_LINK_CAP2 0x10024 1970 #define regBIF_CFG_DEV0_EPF0_LINK_CAP2_BASE_IDX 5 1971 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL2 0x10025 1972 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL2_BASE_IDX 5 1973 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS2 0x10025 1974 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS2_BASE_IDX 5 1975 #define regBIF_CFG_DEV0_EPF0_MSI_CAP_LIST 0x10028 1976 #define regBIF_CFG_DEV0_EPF0_MSI_CAP_LIST_BASE_IDX 5 1977 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL 0x10028 1978 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL_BASE_IDX 5 1979 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO 0x10029 1980 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO_BASE_IDX 5 1981 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI 0x1002a 1982 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI_BASE_IDX 5 1983 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA 0x1002a 1984 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_BASE_IDX 5 1985 #define regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA 0x1002a 1986 #define regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_BASE_IDX 5 1987 #define regBIF_CFG_DEV0_EPF0_MSI_MASK 0x1002b 1988 #define regBIF_CFG_DEV0_EPF0_MSI_MASK_BASE_IDX 5 1989 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 0x1002b 1990 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64_BASE_IDX 5 1991 #define regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 0x1002b 1992 #define regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 1993 #define regBIF_CFG_DEV0_EPF0_MSI_MASK_64 0x1002c 1994 #define regBIF_CFG_DEV0_EPF0_MSI_MASK_64_BASE_IDX 5 1995 #define regBIF_CFG_DEV0_EPF0_MSI_PENDING 0x1002c 1996 #define regBIF_CFG_DEV0_EPF0_MSI_PENDING_BASE_IDX 5 1997 #define regBIF_CFG_DEV0_EPF0_MSI_PENDING_64 0x1002d 1998 #define regBIF_CFG_DEV0_EPF0_MSI_PENDING_64_BASE_IDX 5 1999 #define regBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST 0x10030 2000 #define regBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST_BASE_IDX 5 2001 #define regBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL 0x10030 2002 #define regBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL_BASE_IDX 5 2003 #define regBIF_CFG_DEV0_EPF0_MSIX_TABLE 0x10031 2004 #define regBIF_CFG_DEV0_EPF0_MSIX_TABLE_BASE_IDX 5 2005 #define regBIF_CFG_DEV0_EPF0_MSIX_PBA 0x10032 2006 #define regBIF_CFG_DEV0_EPF0_MSIX_PBA_BASE_IDX 5 2007 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 2008 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 2009 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR 0x10041 2010 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 2011 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 0x10042 2012 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 2013 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 0x10043 2014 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 2015 #define regBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST 0x10044 2016 #define regBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 2017 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 0x10045 2018 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 2019 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 0x10046 2020 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 2021 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL 0x10047 2022 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL_BASE_IDX 5 2023 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS 0x10047 2024 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS_BASE_IDX 5 2025 #define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP 0x10048 2026 #define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 2027 #define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL 0x10049 2028 #define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 2029 #define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS 0x1004a 2030 #define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 2031 #define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP 0x1004b 2032 #define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 2033 #define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL 0x1004c 2034 #define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 2035 #define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS 0x1004d 2036 #define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 2037 #define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x10050 2038 #define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 2039 #define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 0x10051 2040 #define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 2041 #define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 0x10052 2042 #define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 2043 #define regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10054 2044 #define regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 2045 #define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS 0x10055 2046 #define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 2047 #define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK 0x10056 2048 #define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 2049 #define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY 0x10057 2050 #define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 2051 #define regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS 0x10058 2052 #define regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 2053 #define regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK 0x10059 2054 #define regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK_BASE_IDX 5 2055 #define regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL 0x1005a 2056 #define regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 2057 #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 0x1005b 2058 #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0_BASE_IDX 5 2059 #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 0x1005c 2060 #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1_BASE_IDX 5 2061 #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 0x1005d 2062 #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2_BASE_IDX 5 2063 #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 0x1005e 2064 #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3_BASE_IDX 5 2065 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 0x10062 2066 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 2067 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 0x10063 2068 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 2069 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 0x10064 2070 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 2071 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 0x10065 2072 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 2073 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST 0x10080 2074 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 2075 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP 0x10081 2076 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP_BASE_IDX 5 2077 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL 0x10082 2078 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL_BASE_IDX 5 2079 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP 0x10083 2080 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP_BASE_IDX 5 2081 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL 0x10084 2082 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL_BASE_IDX 5 2083 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP 0x10085 2084 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP_BASE_IDX 5 2085 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL 0x10086 2086 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL_BASE_IDX 5 2087 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP 0x10087 2088 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP_BASE_IDX 5 2089 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL 0x10088 2090 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL_BASE_IDX 5 2091 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP 0x10089 2092 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP_BASE_IDX 5 2093 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL 0x1008a 2094 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL_BASE_IDX 5 2095 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP 0x1008b 2096 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP_BASE_IDX 5 2097 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL 0x1008c 2098 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL_BASE_IDX 5 2099 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10090 2100 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 2101 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT 0x10091 2102 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 2103 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA 0x10092 2104 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 2105 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP 0x10093 2106 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 2107 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST 0x10094 2108 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 2109 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP 0x10095 2110 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP_BASE_IDX 5 2111 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR 0x10096 2112 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 2113 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS 0x10097 2114 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS_BASE_IDX 5 2115 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL 0x10097 2116 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL_BASE_IDX 5 2117 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10098 2118 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 2119 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10098 2120 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 2121 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10098 2122 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 2123 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10098 2124 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 2125 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10099 2126 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 2127 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10099 2128 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 2129 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10099 2130 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 2131 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10099 2132 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 2133 #define regBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST 0x1009c 2134 #define regBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 2135 #define regBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 0x1009d 2136 #define regBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3_BASE_IDX 5 2137 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS 0x1009e 2138 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 2139 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL 0x1009f 2140 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 2141 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL 0x1009f 2142 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 2143 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL 0x100a0 2144 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 2145 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL 0x100a0 2146 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 2147 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL 0x100a1 2148 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 2149 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL 0x100a1 2150 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 2151 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL 0x100a2 2152 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 2153 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL 0x100a2 2154 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 2155 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL 0x100a3 2156 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 2157 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL 0x100a3 2158 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 2159 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL 0x100a4 2160 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 2161 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL 0x100a4 2162 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 2163 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL 0x100a5 2164 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 2165 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL 0x100a5 2166 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 2167 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL 0x100a6 2168 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 2169 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL 0x100a6 2170 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 2171 #define regBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST 0x100a8 2172 #define regBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 2173 #define regBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP 0x100a9 2174 #define regBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP_BASE_IDX 5 2175 #define regBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL 0x100a9 2176 #define regBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL_BASE_IDX 5 2177 #define regBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST 0x100b4 2178 #define regBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 2179 #define regBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP 0x100b5 2180 #define regBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP_BASE_IDX 5 2181 #define regBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL 0x100b5 2182 #define regBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL_BASE_IDX 5 2183 #define regBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST 0x100c8 2184 #define regBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 5 2185 #define regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x100c9 2186 #define regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP_BASE_IDX 5 2187 #define regBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST 0x100ca 2188 #define regBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 2189 #define regBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP 0x100cb 2190 #define regBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP_BASE_IDX 5 2191 #define regBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL 0x100cb 2192 #define regBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL_BASE_IDX 5 2193 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST 0x100cc 2194 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 5 2195 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP 0x100cd 2196 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP_BASE_IDX 5 2197 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL 0x100ce 2198 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL_BASE_IDX 5 2199 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS 0x100ce 2200 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS_BASE_IDX 5 2201 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS 0x100cf 2202 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 5 2203 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS 0x100cf 2204 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 5 2205 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS 0x100d0 2206 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS_BASE_IDX 5 2207 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK 0x100d0 2208 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 5 2209 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET 0x100d1 2210 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 5 2211 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE 0x100d1 2212 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE_BASE_IDX 5 2213 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID 0x100d2 2214 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 5 2215 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x100d3 2216 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 5 2217 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x100d4 2218 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 5 2219 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0 0x100d5 2220 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 5 2221 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1 0x100d6 2222 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 5 2223 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2 0x100d7 2224 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 5 2225 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3 0x100d8 2226 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 5 2227 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4 0x100d9 2228 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 5 2229 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5 0x100da 2230 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 5 2231 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x100db 2232 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 5 2233 #define regBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST 0x10100 2234 #define regBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 2235 #define regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP 0x10101 2236 #define regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP_BASE_IDX 5 2237 #define regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS 0x10102 2238 #define regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 2239 #define regBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST 0x10104 2240 #define regBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 2241 #define regBIF_CFG_DEV0_EPF0_LINK_CAP_16GT 0x10105 2242 #define regBIF_CFG_DEV0_EPF0_LINK_CAP_16GT_BASE_IDX 5 2243 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT 0x10106 2244 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT_BASE_IDX 5 2245 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT 0x10107 2246 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT_BASE_IDX 5 2247 #define regBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x10108 2248 #define regBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 2249 #define regBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x10109 2250 #define regBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 2251 #define regBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x1010a 2252 #define regBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 2253 #define regBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT 0x1010c 2254 #define regBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 2255 #define regBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT 0x1010c 2256 #define regBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 2257 #define regBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT 0x1010c 2258 #define regBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 2259 #define regBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT 0x1010c 2260 #define regBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 2261 #define regBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT 0x1010d 2262 #define regBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 2263 #define regBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT 0x1010d 2264 #define regBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 2265 #define regBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT 0x1010d 2266 #define regBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 2267 #define regBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT 0x1010d 2268 #define regBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 2269 #define regBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT 0x1010e 2270 #define regBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 2271 #define regBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT 0x1010e 2272 #define regBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 2273 #define regBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT 0x1010e 2274 #define regBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 2275 #define regBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT 0x1010e 2276 #define regBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 2277 #define regBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT 0x1010f 2278 #define regBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 2279 #define regBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT 0x1010f 2280 #define regBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 2281 #define regBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT 0x1010f 2282 #define regBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 2283 #define regBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT 0x1010f 2284 #define regBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 2285 #define regBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST 0x10114 2286 #define regBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 2287 #define regBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP 0x10115 2288 #define regBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP_BASE_IDX 5 2289 #define regBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS 0x10115 2290 #define regBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS_BASE_IDX 5 2291 #define regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL 0x10116 2292 #define regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 2293 #define regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS 0x10116 2294 #define regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 2295 #define regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL 0x10117 2296 #define regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 2297 #define regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS 0x10117 2298 #define regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 2299 #define regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL 0x10118 2300 #define regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 2301 #define regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS 0x10118 2302 #define regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 2303 #define regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL 0x10119 2304 #define regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 2305 #define regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS 0x10119 2306 #define regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 2307 #define regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL 0x1011a 2308 #define regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 2309 #define regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS 0x1011a 2310 #define regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 2311 #define regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL 0x1011b 2312 #define regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 2313 #define regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS 0x1011b 2314 #define regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 2315 #define regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL 0x1011c 2316 #define regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 2317 #define regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS 0x1011c 2318 #define regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 2319 #define regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL 0x1011d 2320 #define regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 2321 #define regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS 0x1011d 2322 #define regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 2323 #define regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL 0x1011e 2324 #define regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 2325 #define regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS 0x1011e 2326 #define regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 2327 #define regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL 0x1011f 2328 #define regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 2329 #define regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS 0x1011f 2330 #define regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 2331 #define regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL 0x10120 2332 #define regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 2333 #define regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS 0x10120 2334 #define regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 2335 #define regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL 0x10121 2336 #define regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 2337 #define regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS 0x10121 2338 #define regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 2339 #define regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL 0x10122 2340 #define regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 2341 #define regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS 0x10122 2342 #define regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 2343 #define regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL 0x10123 2344 #define regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 2345 #define regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS 0x10123 2346 #define regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 2347 #define regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL 0x10124 2348 #define regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 2349 #define regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS 0x10124 2350 #define regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 2351 #define regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL 0x10125 2352 #define regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 2353 #define regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS 0x10125 2354 #define regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 2355 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x10130 2356 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX 5 2357 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP 0x10131 2358 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX 5 2359 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL 0x10132 2360 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX 5 2361 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP 0x10133 2362 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX 5 2363 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL 0x10134 2364 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX 5 2365 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP 0x10135 2366 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX 5 2367 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL 0x10136 2368 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX 5 2369 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP 0x10137 2370 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX 5 2371 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL 0x10138 2372 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX 5 2373 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP 0x10139 2374 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX 5 2375 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL 0x1013a 2376 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX 5 2377 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP 0x1013b 2378 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX 5 2379 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL 0x1013c 2380 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX 5 2381 #define regBIF_CFG_DEV0_EPF0_LINK_CAP_32GT 0x10141 2382 #define regBIF_CFG_DEV0_EPF0_LINK_CAP_32GT_BASE_IDX 5 2383 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT 0x10142 2384 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT_BASE_IDX 5 2385 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT 0x10143 2386 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT_BASE_IDX 5 2387 2388 2389 // addressBlock: nbif_bif_cfg_dev0_epf0_vf0_bifcfgdecp 2390 // base address: 0x10160000 2391 #define regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID 0x18000 2392 #define regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID_BASE_IDX 5 2393 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID 0x18000 2394 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID_BASE_IDX 5 2395 #define regBIF_CFG_DEV0_EPF0_VF0_COMMAND 0x18001 2396 #define regBIF_CFG_DEV0_EPF0_VF0_COMMAND_BASE_IDX 5 2397 #define regBIF_CFG_DEV0_EPF0_VF0_STATUS 0x18001 2398 #define regBIF_CFG_DEV0_EPF0_VF0_STATUS_BASE_IDX 5 2399 #define regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID 0x18002 2400 #define regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID_BASE_IDX 5 2401 #define regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE 0x18002 2402 #define regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE_BASE_IDX 5 2403 #define regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS 0x18002 2404 #define regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS_BASE_IDX 5 2405 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS 0x18002 2406 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS_BASE_IDX 5 2407 #define regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE 0x18003 2408 #define regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE_BASE_IDX 5 2409 #define regBIF_CFG_DEV0_EPF0_VF0_LATENCY 0x18003 2410 #define regBIF_CFG_DEV0_EPF0_VF0_LATENCY_BASE_IDX 5 2411 #define regBIF_CFG_DEV0_EPF0_VF0_HEADER 0x18003 2412 #define regBIF_CFG_DEV0_EPF0_VF0_HEADER_BASE_IDX 5 2413 #define regBIF_CFG_DEV0_EPF0_VF0_BIST 0x18003 2414 #define regBIF_CFG_DEV0_EPF0_VF0_BIST_BASE_IDX 5 2415 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 0x18004 2416 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1_BASE_IDX 5 2417 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 0x18005 2418 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2_BASE_IDX 5 2419 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 0x18006 2420 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3_BASE_IDX 5 2421 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 0x18007 2422 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4_BASE_IDX 5 2423 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 0x18008 2424 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5_BASE_IDX 5 2425 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 0x18009 2426 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6_BASE_IDX 5 2427 #define regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR 0x1800a 2428 #define regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR_BASE_IDX 5 2429 #define regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID 0x1800b 2430 #define regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID_BASE_IDX 5 2431 #define regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR 0x1800c 2432 #define regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR_BASE_IDX 5 2433 #define regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR 0x1800d 2434 #define regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR_BASE_IDX 5 2435 #define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE 0x1800f 2436 #define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE_BASE_IDX 5 2437 #define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN 0x1800f 2438 #define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN_BASE_IDX 5 2439 #define regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT 0x1800f 2440 #define regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT_BASE_IDX 5 2441 #define regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY 0x1800f 2442 #define regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY_BASE_IDX 5 2443 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST 0x18019 2444 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST_BASE_IDX 5 2445 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP 0x18019 2446 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_BASE_IDX 5 2447 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP 0x1801a 2448 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP_BASE_IDX 5 2449 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL 0x1801b 2450 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL_BASE_IDX 5 2451 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS 0x1801b 2452 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS_BASE_IDX 5 2453 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP 0x1801c 2454 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP_BASE_IDX 5 2455 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL 0x1801d 2456 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL_BASE_IDX 5 2457 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS 0x1801d 2458 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS_BASE_IDX 5 2459 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 0x18022 2460 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2_BASE_IDX 5 2461 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 0x18023 2462 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2_BASE_IDX 5 2463 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 0x18023 2464 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2_BASE_IDX 5 2465 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 0x18024 2466 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2_BASE_IDX 5 2467 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 0x18025 2468 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2_BASE_IDX 5 2469 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 0x18025 2470 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2_BASE_IDX 5 2471 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST 0x18028 2472 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST_BASE_IDX 5 2473 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL 0x18028 2474 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL_BASE_IDX 5 2475 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO 0x18029 2476 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO_BASE_IDX 5 2477 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI 0x1802a 2478 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI_BASE_IDX 5 2479 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA 0x1802a 2480 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_BASE_IDX 5 2481 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA 0x1802a 2482 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_BASE_IDX 5 2483 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK 0x1802b 2484 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_BASE_IDX 5 2485 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 0x1802b 2486 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64_BASE_IDX 5 2487 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 0x1802b 2488 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 2489 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 0x1802c 2490 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64_BASE_IDX 5 2491 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING 0x1802c 2492 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_BASE_IDX 5 2493 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 0x1802d 2494 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64_BASE_IDX 5 2495 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST 0x18030 2496 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST_BASE_IDX 5 2497 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL 0x18030 2498 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL_BASE_IDX 5 2499 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE 0x18031 2500 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE_BASE_IDX 5 2501 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA 0x18032 2502 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA_BASE_IDX 5 2503 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x18040 2504 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 2505 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x18041 2506 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 2507 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 0x18042 2508 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 2509 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 0x18043 2510 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 2511 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x18054 2512 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 2513 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS 0x18055 2514 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 2515 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK 0x18056 2516 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 2517 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY 0x18057 2518 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 2519 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS 0x18058 2520 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 2521 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK 0x18059 2522 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK_BASE_IDX 5 2523 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL 0x1805a 2524 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 2525 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 0x1805b 2526 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0_BASE_IDX 5 2527 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 0x1805c 2528 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1_BASE_IDX 5 2529 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 0x1805d 2530 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2_BASE_IDX 5 2531 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 0x1805e 2532 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3_BASE_IDX 5 2533 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 0x18062 2534 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 2535 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 0x18063 2536 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 2537 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 0x18064 2538 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 2539 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 0x18065 2540 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 2541 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST 0x180ca 2542 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 2543 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP 0x180cb 2544 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP_BASE_IDX 5 2545 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL 0x180cb 2546 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL_BASE_IDX 5 2547 2548 2549 // addressBlock: nbif_bif_cfg_dev0_epf0_vf1_bifcfgdecp 2550 // base address: 0x10161000 2551 #define regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID 0x18400 2552 #define regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID_BASE_IDX 5 2553 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID 0x18400 2554 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID_BASE_IDX 5 2555 #define regBIF_CFG_DEV0_EPF0_VF1_COMMAND 0x18401 2556 #define regBIF_CFG_DEV0_EPF0_VF1_COMMAND_BASE_IDX 5 2557 #define regBIF_CFG_DEV0_EPF0_VF1_STATUS 0x18401 2558 #define regBIF_CFG_DEV0_EPF0_VF1_STATUS_BASE_IDX 5 2559 #define regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID 0x18402 2560 #define regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID_BASE_IDX 5 2561 #define regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE 0x18402 2562 #define regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE_BASE_IDX 5 2563 #define regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS 0x18402 2564 #define regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS_BASE_IDX 5 2565 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS 0x18402 2566 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS_BASE_IDX 5 2567 #define regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE 0x18403 2568 #define regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE_BASE_IDX 5 2569 #define regBIF_CFG_DEV0_EPF0_VF1_LATENCY 0x18403 2570 #define regBIF_CFG_DEV0_EPF0_VF1_LATENCY_BASE_IDX 5 2571 #define regBIF_CFG_DEV0_EPF0_VF1_HEADER 0x18403 2572 #define regBIF_CFG_DEV0_EPF0_VF1_HEADER_BASE_IDX 5 2573 #define regBIF_CFG_DEV0_EPF0_VF1_BIST 0x18403 2574 #define regBIF_CFG_DEV0_EPF0_VF1_BIST_BASE_IDX 5 2575 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 0x18404 2576 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1_BASE_IDX 5 2577 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 0x18405 2578 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2_BASE_IDX 5 2579 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 0x18406 2580 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3_BASE_IDX 5 2581 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 0x18407 2582 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4_BASE_IDX 5 2583 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 0x18408 2584 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5_BASE_IDX 5 2585 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 0x18409 2586 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6_BASE_IDX 5 2587 #define regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR 0x1840a 2588 #define regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR_BASE_IDX 5 2589 #define regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID 0x1840b 2590 #define regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID_BASE_IDX 5 2591 #define regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR 0x1840c 2592 #define regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR_BASE_IDX 5 2593 #define regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR 0x1840d 2594 #define regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR_BASE_IDX 5 2595 #define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE 0x1840f 2596 #define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE_BASE_IDX 5 2597 #define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN 0x1840f 2598 #define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN_BASE_IDX 5 2599 #define regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT 0x1840f 2600 #define regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT_BASE_IDX 5 2601 #define regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY 0x1840f 2602 #define regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY_BASE_IDX 5 2603 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST 0x18419 2604 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST_BASE_IDX 5 2605 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP 0x18419 2606 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_BASE_IDX 5 2607 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP 0x1841a 2608 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP_BASE_IDX 5 2609 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL 0x1841b 2610 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL_BASE_IDX 5 2611 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS 0x1841b 2612 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS_BASE_IDX 5 2613 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP 0x1841c 2614 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP_BASE_IDX 5 2615 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL 0x1841d 2616 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL_BASE_IDX 5 2617 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS 0x1841d 2618 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS_BASE_IDX 5 2619 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 0x18422 2620 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2_BASE_IDX 5 2621 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 0x18423 2622 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2_BASE_IDX 5 2623 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 0x18423 2624 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2_BASE_IDX 5 2625 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 0x18424 2626 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2_BASE_IDX 5 2627 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 0x18425 2628 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2_BASE_IDX 5 2629 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 0x18425 2630 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2_BASE_IDX 5 2631 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST 0x18428 2632 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST_BASE_IDX 5 2633 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL 0x18428 2634 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL_BASE_IDX 5 2635 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO 0x18429 2636 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO_BASE_IDX 5 2637 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI 0x1842a 2638 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI_BASE_IDX 5 2639 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA 0x1842a 2640 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_BASE_IDX 5 2641 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA 0x1842a 2642 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_BASE_IDX 5 2643 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK 0x1842b 2644 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_BASE_IDX 5 2645 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 0x1842b 2646 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64_BASE_IDX 5 2647 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 0x1842b 2648 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 2649 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 0x1842c 2650 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64_BASE_IDX 5 2651 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING 0x1842c 2652 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_BASE_IDX 5 2653 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 0x1842d 2654 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64_BASE_IDX 5 2655 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST 0x18430 2656 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST_BASE_IDX 5 2657 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL 0x18430 2658 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL_BASE_IDX 5 2659 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE 0x18431 2660 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE_BASE_IDX 5 2661 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA 0x18432 2662 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA_BASE_IDX 5 2663 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x18440 2664 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 2665 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR 0x18441 2666 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 2667 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 0x18442 2668 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 2669 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 0x18443 2670 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 2671 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x18454 2672 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 2673 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS 0x18455 2674 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 2675 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK 0x18456 2676 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 2677 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY 0x18457 2678 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 2679 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS 0x18458 2680 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 2681 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK 0x18459 2682 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK_BASE_IDX 5 2683 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL 0x1845a 2684 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 2685 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 0x1845b 2686 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0_BASE_IDX 5 2687 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 0x1845c 2688 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1_BASE_IDX 5 2689 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 0x1845d 2690 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2_BASE_IDX 5 2691 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 0x1845e 2692 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3_BASE_IDX 5 2693 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 0x18462 2694 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 2695 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 0x18463 2696 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 2697 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 0x18464 2698 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 2699 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 0x18465 2700 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 2701 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST 0x184ca 2702 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 2703 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP 0x184cb 2704 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP_BASE_IDX 5 2705 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL 0x184cb 2706 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL_BASE_IDX 5 2707 2708 2709 // addressBlock: nbif_bif_cfg_dev0_epf0_vf2_bifcfgdecp 2710 // base address: 0x10162000 2711 #define regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID 0x18800 2712 #define regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID_BASE_IDX 5 2713 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID 0x18800 2714 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID_BASE_IDX 5 2715 #define regBIF_CFG_DEV0_EPF0_VF2_COMMAND 0x18801 2716 #define regBIF_CFG_DEV0_EPF0_VF2_COMMAND_BASE_IDX 5 2717 #define regBIF_CFG_DEV0_EPF0_VF2_STATUS 0x18801 2718 #define regBIF_CFG_DEV0_EPF0_VF2_STATUS_BASE_IDX 5 2719 #define regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID 0x18802 2720 #define regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID_BASE_IDX 5 2721 #define regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE 0x18802 2722 #define regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE_BASE_IDX 5 2723 #define regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS 0x18802 2724 #define regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS_BASE_IDX 5 2725 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS 0x18802 2726 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS_BASE_IDX 5 2727 #define regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE 0x18803 2728 #define regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE_BASE_IDX 5 2729 #define regBIF_CFG_DEV0_EPF0_VF2_LATENCY 0x18803 2730 #define regBIF_CFG_DEV0_EPF0_VF2_LATENCY_BASE_IDX 5 2731 #define regBIF_CFG_DEV0_EPF0_VF2_HEADER 0x18803 2732 #define regBIF_CFG_DEV0_EPF0_VF2_HEADER_BASE_IDX 5 2733 #define regBIF_CFG_DEV0_EPF0_VF2_BIST 0x18803 2734 #define regBIF_CFG_DEV0_EPF0_VF2_BIST_BASE_IDX 5 2735 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 0x18804 2736 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1_BASE_IDX 5 2737 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 0x18805 2738 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2_BASE_IDX 5 2739 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 0x18806 2740 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3_BASE_IDX 5 2741 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 0x18807 2742 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4_BASE_IDX 5 2743 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 0x18808 2744 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5_BASE_IDX 5 2745 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 0x18809 2746 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6_BASE_IDX 5 2747 #define regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR 0x1880a 2748 #define regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR_BASE_IDX 5 2749 #define regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID 0x1880b 2750 #define regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID_BASE_IDX 5 2751 #define regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR 0x1880c 2752 #define regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR_BASE_IDX 5 2753 #define regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR 0x1880d 2754 #define regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR_BASE_IDX 5 2755 #define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE 0x1880f 2756 #define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE_BASE_IDX 5 2757 #define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN 0x1880f 2758 #define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN_BASE_IDX 5 2759 #define regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT 0x1880f 2760 #define regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT_BASE_IDX 5 2761 #define regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY 0x1880f 2762 #define regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY_BASE_IDX 5 2763 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST 0x18819 2764 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST_BASE_IDX 5 2765 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP 0x18819 2766 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_BASE_IDX 5 2767 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP 0x1881a 2768 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP_BASE_IDX 5 2769 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL 0x1881b 2770 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL_BASE_IDX 5 2771 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS 0x1881b 2772 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS_BASE_IDX 5 2773 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP 0x1881c 2774 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP_BASE_IDX 5 2775 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL 0x1881d 2776 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL_BASE_IDX 5 2777 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS 0x1881d 2778 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS_BASE_IDX 5 2779 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 0x18822 2780 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2_BASE_IDX 5 2781 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 0x18823 2782 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2_BASE_IDX 5 2783 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 0x18823 2784 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2_BASE_IDX 5 2785 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 0x18824 2786 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2_BASE_IDX 5 2787 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 0x18825 2788 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2_BASE_IDX 5 2789 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 0x18825 2790 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2_BASE_IDX 5 2791 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST 0x18828 2792 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST_BASE_IDX 5 2793 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL 0x18828 2794 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL_BASE_IDX 5 2795 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO 0x18829 2796 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO_BASE_IDX 5 2797 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI 0x1882a 2798 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI_BASE_IDX 5 2799 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA 0x1882a 2800 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_BASE_IDX 5 2801 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA 0x1882a 2802 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_BASE_IDX 5 2803 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK 0x1882b 2804 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_BASE_IDX 5 2805 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 0x1882b 2806 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64_BASE_IDX 5 2807 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 0x1882b 2808 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64_BASE_IDX 5 2809 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 0x1882c 2810 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64_BASE_IDX 5 2811 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING 0x1882c 2812 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_BASE_IDX 5 2813 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 0x1882d 2814 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64_BASE_IDX 5 2815 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST 0x18830 2816 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST_BASE_IDX 5 2817 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL 0x18830 2818 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL_BASE_IDX 5 2819 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE 0x18831 2820 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE_BASE_IDX 5 2821 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA 0x18832 2822 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA_BASE_IDX 5 2823 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x18840 2824 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 2825 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR 0x18841 2826 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 2827 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 0x18842 2828 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 2829 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 0x18843 2830 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 2831 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x18854 2832 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 2833 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS 0x18855 2834 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 2835 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK 0x18856 2836 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 2837 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY 0x18857 2838 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 2839 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS 0x18858 2840 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS_BASE_IDX 5 2841 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK 0x18859 2842 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK_BASE_IDX 5 2843 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL 0x1885a 2844 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 2845 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 0x1885b 2846 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0_BASE_IDX 5 2847 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 0x1885c 2848 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1_BASE_IDX 5 2849 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 0x1885d 2850 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2_BASE_IDX 5 2851 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 0x1885e 2852 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3_BASE_IDX 5 2853 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 0x18862 2854 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 2855 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 0x18863 2856 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 2857 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 0x18864 2858 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 2859 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 0x18865 2860 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 2861 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST 0x188ca 2862 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 2863 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP 0x188cb 2864 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP_BASE_IDX 5 2865 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL 0x188cb 2866 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL_BASE_IDX 5 2867 2868 2869 // addressBlock: nbif_bif_cfg_dev0_epf0_vf3_bifcfgdecp 2870 // base address: 0x10163000 2871 #define regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID 0x18c00 2872 #define regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID_BASE_IDX 5 2873 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID 0x18c00 2874 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID_BASE_IDX 5 2875 #define regBIF_CFG_DEV0_EPF0_VF3_COMMAND 0x18c01 2876 #define regBIF_CFG_DEV0_EPF0_VF3_COMMAND_BASE_IDX 5 2877 #define regBIF_CFG_DEV0_EPF0_VF3_STATUS 0x18c01 2878 #define regBIF_CFG_DEV0_EPF0_VF3_STATUS_BASE_IDX 5 2879 #define regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID 0x18c02 2880 #define regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID_BASE_IDX 5 2881 #define regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE 0x18c02 2882 #define regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE_BASE_IDX 5 2883 #define regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS 0x18c02 2884 #define regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS_BASE_IDX 5 2885 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS 0x18c02 2886 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS_BASE_IDX 5 2887 #define regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE 0x18c03 2888 #define regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE_BASE_IDX 5 2889 #define regBIF_CFG_DEV0_EPF0_VF3_LATENCY 0x18c03 2890 #define regBIF_CFG_DEV0_EPF0_VF3_LATENCY_BASE_IDX 5 2891 #define regBIF_CFG_DEV0_EPF0_VF3_HEADER 0x18c03 2892 #define regBIF_CFG_DEV0_EPF0_VF3_HEADER_BASE_IDX 5 2893 #define regBIF_CFG_DEV0_EPF0_VF3_BIST 0x18c03 2894 #define regBIF_CFG_DEV0_EPF0_VF3_BIST_BASE_IDX 5 2895 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 0x18c04 2896 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1_BASE_IDX 5 2897 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 0x18c05 2898 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2_BASE_IDX 5 2899 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 0x18c06 2900 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3_BASE_IDX 5 2901 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 0x18c07 2902 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4_BASE_IDX 5 2903 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 0x18c08 2904 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5_BASE_IDX 5 2905 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 0x18c09 2906 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6_BASE_IDX 5 2907 #define regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR 0x18c0a 2908 #define regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR_BASE_IDX 5 2909 #define regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID 0x18c0b 2910 #define regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID_BASE_IDX 5 2911 #define regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR 0x18c0c 2912 #define regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR_BASE_IDX 5 2913 #define regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR 0x18c0d 2914 #define regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR_BASE_IDX 5 2915 #define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE 0x18c0f 2916 #define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE_BASE_IDX 5 2917 #define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN 0x18c0f 2918 #define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN_BASE_IDX 5 2919 #define regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT 0x18c0f 2920 #define regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT_BASE_IDX 5 2921 #define regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY 0x18c0f 2922 #define regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY_BASE_IDX 5 2923 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST 0x18c19 2924 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST_BASE_IDX 5 2925 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP 0x18c19 2926 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_BASE_IDX 5 2927 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP 0x18c1a 2928 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP_BASE_IDX 5 2929 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL 0x18c1b 2930 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL_BASE_IDX 5 2931 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS 0x18c1b 2932 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS_BASE_IDX 5 2933 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP 0x18c1c 2934 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP_BASE_IDX 5 2935 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL 0x18c1d 2936 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL_BASE_IDX 5 2937 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS 0x18c1d 2938 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS_BASE_IDX 5 2939 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 0x18c22 2940 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2_BASE_IDX 5 2941 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 0x18c23 2942 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2_BASE_IDX 5 2943 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 0x18c23 2944 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2_BASE_IDX 5 2945 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 0x18c24 2946 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2_BASE_IDX 5 2947 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 0x18c25 2948 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2_BASE_IDX 5 2949 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 0x18c25 2950 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2_BASE_IDX 5 2951 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST 0x18c28 2952 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST_BASE_IDX 5 2953 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL 0x18c28 2954 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL_BASE_IDX 5 2955 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO 0x18c29 2956 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO_BASE_IDX 5 2957 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI 0x18c2a 2958 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI_BASE_IDX 5 2959 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA 0x18c2a 2960 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_BASE_IDX 5 2961 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA 0x18c2a 2962 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_BASE_IDX 5 2963 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK 0x18c2b 2964 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_BASE_IDX 5 2965 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 0x18c2b 2966 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64_BASE_IDX 5 2967 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 0x18c2b 2968 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64_BASE_IDX 5 2969 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 0x18c2c 2970 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64_BASE_IDX 5 2971 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING 0x18c2c 2972 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_BASE_IDX 5 2973 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 0x18c2d 2974 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64_BASE_IDX 5 2975 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST 0x18c30 2976 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST_BASE_IDX 5 2977 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL 0x18c30 2978 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL_BASE_IDX 5 2979 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE 0x18c31 2980 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE_BASE_IDX 5 2981 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA 0x18c32 2982 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA_BASE_IDX 5 2983 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x18c40 2984 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 2985 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR 0x18c41 2986 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 2987 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 0x18c42 2988 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 2989 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 0x18c43 2990 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 2991 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x18c54 2992 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 2993 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS 0x18c55 2994 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 2995 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK 0x18c56 2996 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 2997 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY 0x18c57 2998 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 2999 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS 0x18c58 3000 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS_BASE_IDX 5 3001 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK 0x18c59 3002 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK_BASE_IDX 5 3003 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL 0x18c5a 3004 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 3005 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 0x18c5b 3006 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0_BASE_IDX 5 3007 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 0x18c5c 3008 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1_BASE_IDX 5 3009 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 0x18c5d 3010 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2_BASE_IDX 5 3011 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 0x18c5e 3012 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3_BASE_IDX 5 3013 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 0x18c62 3014 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 3015 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 0x18c63 3016 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 3017 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 0x18c64 3018 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 3019 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 0x18c65 3020 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 3021 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST 0x18cca 3022 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 3023 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP 0x18ccb 3024 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP_BASE_IDX 5 3025 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL 0x18ccb 3026 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL_BASE_IDX 5 3027 3028 3029 // addressBlock: nbif_bif_cfg_dev0_epf0_vf4_bifcfgdecp 3030 // base address: 0x10164000 3031 #define regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID 0x19000 3032 #define regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID_BASE_IDX 5 3033 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID 0x19000 3034 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID_BASE_IDX 5 3035 #define regBIF_CFG_DEV0_EPF0_VF4_COMMAND 0x19001 3036 #define regBIF_CFG_DEV0_EPF0_VF4_COMMAND_BASE_IDX 5 3037 #define regBIF_CFG_DEV0_EPF0_VF4_STATUS 0x19001 3038 #define regBIF_CFG_DEV0_EPF0_VF4_STATUS_BASE_IDX 5 3039 #define regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID 0x19002 3040 #define regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID_BASE_IDX 5 3041 #define regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE 0x19002 3042 #define regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE_BASE_IDX 5 3043 #define regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS 0x19002 3044 #define regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS_BASE_IDX 5 3045 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS 0x19002 3046 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS_BASE_IDX 5 3047 #define regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE 0x19003 3048 #define regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE_BASE_IDX 5 3049 #define regBIF_CFG_DEV0_EPF0_VF4_LATENCY 0x19003 3050 #define regBIF_CFG_DEV0_EPF0_VF4_LATENCY_BASE_IDX 5 3051 #define regBIF_CFG_DEV0_EPF0_VF4_HEADER 0x19003 3052 #define regBIF_CFG_DEV0_EPF0_VF4_HEADER_BASE_IDX 5 3053 #define regBIF_CFG_DEV0_EPF0_VF4_BIST 0x19003 3054 #define regBIF_CFG_DEV0_EPF0_VF4_BIST_BASE_IDX 5 3055 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 0x19004 3056 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1_BASE_IDX 5 3057 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 0x19005 3058 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2_BASE_IDX 5 3059 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 0x19006 3060 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3_BASE_IDX 5 3061 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 0x19007 3062 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4_BASE_IDX 5 3063 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 0x19008 3064 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5_BASE_IDX 5 3065 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 0x19009 3066 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6_BASE_IDX 5 3067 #define regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR 0x1900a 3068 #define regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR_BASE_IDX 5 3069 #define regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID 0x1900b 3070 #define regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID_BASE_IDX 5 3071 #define regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR 0x1900c 3072 #define regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR_BASE_IDX 5 3073 #define regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR 0x1900d 3074 #define regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR_BASE_IDX 5 3075 #define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE 0x1900f 3076 #define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE_BASE_IDX 5 3077 #define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN 0x1900f 3078 #define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN_BASE_IDX 5 3079 #define regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT 0x1900f 3080 #define regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT_BASE_IDX 5 3081 #define regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY 0x1900f 3082 #define regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY_BASE_IDX 5 3083 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST 0x19019 3084 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST_BASE_IDX 5 3085 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP 0x19019 3086 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_BASE_IDX 5 3087 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP 0x1901a 3088 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP_BASE_IDX 5 3089 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL 0x1901b 3090 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL_BASE_IDX 5 3091 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS 0x1901b 3092 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS_BASE_IDX 5 3093 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP 0x1901c 3094 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP_BASE_IDX 5 3095 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL 0x1901d 3096 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL_BASE_IDX 5 3097 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS 0x1901d 3098 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS_BASE_IDX 5 3099 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 0x19022 3100 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2_BASE_IDX 5 3101 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 0x19023 3102 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2_BASE_IDX 5 3103 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 0x19023 3104 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2_BASE_IDX 5 3105 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 0x19024 3106 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2_BASE_IDX 5 3107 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 0x19025 3108 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2_BASE_IDX 5 3109 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 0x19025 3110 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2_BASE_IDX 5 3111 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST 0x19028 3112 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST_BASE_IDX 5 3113 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL 0x19028 3114 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL_BASE_IDX 5 3115 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO 0x19029 3116 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO_BASE_IDX 5 3117 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI 0x1902a 3118 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI_BASE_IDX 5 3119 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA 0x1902a 3120 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_BASE_IDX 5 3121 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA 0x1902a 3122 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_BASE_IDX 5 3123 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK 0x1902b 3124 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_BASE_IDX 5 3125 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 0x1902b 3126 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64_BASE_IDX 5 3127 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 0x1902b 3128 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64_BASE_IDX 5 3129 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 0x1902c 3130 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64_BASE_IDX 5 3131 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING 0x1902c 3132 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_BASE_IDX 5 3133 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 0x1902d 3134 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64_BASE_IDX 5 3135 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST 0x19030 3136 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST_BASE_IDX 5 3137 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL 0x19030 3138 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL_BASE_IDX 5 3139 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE 0x19031 3140 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE_BASE_IDX 5 3141 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA 0x19032 3142 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA_BASE_IDX 5 3143 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x19040 3144 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 3145 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR 0x19041 3146 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 3147 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 0x19042 3148 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 3149 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 0x19043 3150 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 3151 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x19054 3152 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 3153 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS 0x19055 3154 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 3155 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK 0x19056 3156 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 3157 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY 0x19057 3158 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 3159 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS 0x19058 3160 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS_BASE_IDX 5 3161 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK 0x19059 3162 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK_BASE_IDX 5 3163 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL 0x1905a 3164 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 3165 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 0x1905b 3166 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0_BASE_IDX 5 3167 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 0x1905c 3168 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1_BASE_IDX 5 3169 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 0x1905d 3170 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2_BASE_IDX 5 3171 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 0x1905e 3172 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3_BASE_IDX 5 3173 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 0x19062 3174 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 3175 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 0x19063 3176 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 3177 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 0x19064 3178 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 3179 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 0x19065 3180 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 3181 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST 0x190ca 3182 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 3183 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP 0x190cb 3184 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP_BASE_IDX 5 3185 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL 0x190cb 3186 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL_BASE_IDX 5 3187 3188 3189 // addressBlock: nbif_bif_cfg_dev0_epf0_vf5_bifcfgdecp 3190 // base address: 0x10165000 3191 #define regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID 0x19400 3192 #define regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID_BASE_IDX 5 3193 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID 0x19400 3194 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID_BASE_IDX 5 3195 #define regBIF_CFG_DEV0_EPF0_VF5_COMMAND 0x19401 3196 #define regBIF_CFG_DEV0_EPF0_VF5_COMMAND_BASE_IDX 5 3197 #define regBIF_CFG_DEV0_EPF0_VF5_STATUS 0x19401 3198 #define regBIF_CFG_DEV0_EPF0_VF5_STATUS_BASE_IDX 5 3199 #define regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID 0x19402 3200 #define regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID_BASE_IDX 5 3201 #define regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE 0x19402 3202 #define regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE_BASE_IDX 5 3203 #define regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS 0x19402 3204 #define regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS_BASE_IDX 5 3205 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS 0x19402 3206 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS_BASE_IDX 5 3207 #define regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE 0x19403 3208 #define regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE_BASE_IDX 5 3209 #define regBIF_CFG_DEV0_EPF0_VF5_LATENCY 0x19403 3210 #define regBIF_CFG_DEV0_EPF0_VF5_LATENCY_BASE_IDX 5 3211 #define regBIF_CFG_DEV0_EPF0_VF5_HEADER 0x19403 3212 #define regBIF_CFG_DEV0_EPF0_VF5_HEADER_BASE_IDX 5 3213 #define regBIF_CFG_DEV0_EPF0_VF5_BIST 0x19403 3214 #define regBIF_CFG_DEV0_EPF0_VF5_BIST_BASE_IDX 5 3215 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 0x19404 3216 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1_BASE_IDX 5 3217 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 0x19405 3218 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2_BASE_IDX 5 3219 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 0x19406 3220 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3_BASE_IDX 5 3221 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 0x19407 3222 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4_BASE_IDX 5 3223 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 0x19408 3224 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5_BASE_IDX 5 3225 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 0x19409 3226 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6_BASE_IDX 5 3227 #define regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR 0x1940a 3228 #define regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR_BASE_IDX 5 3229 #define regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID 0x1940b 3230 #define regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID_BASE_IDX 5 3231 #define regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR 0x1940c 3232 #define regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR_BASE_IDX 5 3233 #define regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR 0x1940d 3234 #define regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR_BASE_IDX 5 3235 #define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE 0x1940f 3236 #define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE_BASE_IDX 5 3237 #define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN 0x1940f 3238 #define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN_BASE_IDX 5 3239 #define regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT 0x1940f 3240 #define regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT_BASE_IDX 5 3241 #define regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY 0x1940f 3242 #define regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY_BASE_IDX 5 3243 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST 0x19419 3244 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST_BASE_IDX 5 3245 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP 0x19419 3246 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_BASE_IDX 5 3247 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP 0x1941a 3248 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP_BASE_IDX 5 3249 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL 0x1941b 3250 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL_BASE_IDX 5 3251 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS 0x1941b 3252 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS_BASE_IDX 5 3253 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP 0x1941c 3254 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP_BASE_IDX 5 3255 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL 0x1941d 3256 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL_BASE_IDX 5 3257 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS 0x1941d 3258 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS_BASE_IDX 5 3259 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 0x19422 3260 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2_BASE_IDX 5 3261 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 0x19423 3262 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2_BASE_IDX 5 3263 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 0x19423 3264 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2_BASE_IDX 5 3265 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 0x19424 3266 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2_BASE_IDX 5 3267 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 0x19425 3268 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2_BASE_IDX 5 3269 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 0x19425 3270 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2_BASE_IDX 5 3271 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST 0x19428 3272 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST_BASE_IDX 5 3273 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL 0x19428 3274 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL_BASE_IDX 5 3275 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO 0x19429 3276 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO_BASE_IDX 5 3277 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI 0x1942a 3278 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI_BASE_IDX 5 3279 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA 0x1942a 3280 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_BASE_IDX 5 3281 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA 0x1942a 3282 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_BASE_IDX 5 3283 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK 0x1942b 3284 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_BASE_IDX 5 3285 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 0x1942b 3286 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64_BASE_IDX 5 3287 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 0x1942b 3288 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64_BASE_IDX 5 3289 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 0x1942c 3290 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64_BASE_IDX 5 3291 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING 0x1942c 3292 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_BASE_IDX 5 3293 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 0x1942d 3294 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64_BASE_IDX 5 3295 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST 0x19430 3296 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST_BASE_IDX 5 3297 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL 0x19430 3298 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL_BASE_IDX 5 3299 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE 0x19431 3300 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE_BASE_IDX 5 3301 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA 0x19432 3302 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA_BASE_IDX 5 3303 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x19440 3304 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 3305 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR 0x19441 3306 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 3307 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 0x19442 3308 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 3309 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 0x19443 3310 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 3311 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x19454 3312 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 3313 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS 0x19455 3314 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 3315 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK 0x19456 3316 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 3317 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY 0x19457 3318 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 3319 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS 0x19458 3320 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS_BASE_IDX 5 3321 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK 0x19459 3322 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK_BASE_IDX 5 3323 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL 0x1945a 3324 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 3325 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 0x1945b 3326 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0_BASE_IDX 5 3327 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 0x1945c 3328 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1_BASE_IDX 5 3329 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 0x1945d 3330 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2_BASE_IDX 5 3331 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 0x1945e 3332 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3_BASE_IDX 5 3333 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 0x19462 3334 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 3335 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 0x19463 3336 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 3337 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 0x19464 3338 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 3339 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 0x19465 3340 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 3341 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST 0x194ca 3342 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 3343 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP 0x194cb 3344 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP_BASE_IDX 5 3345 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL 0x194cb 3346 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL_BASE_IDX 5 3347 3348 3349 // addressBlock: nbif_bif_cfg_dev0_epf0_vf6_bifcfgdecp 3350 // base address: 0x10166000 3351 #define regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID 0x19800 3352 #define regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID_BASE_IDX 5 3353 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID 0x19800 3354 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID_BASE_IDX 5 3355 #define regBIF_CFG_DEV0_EPF0_VF6_COMMAND 0x19801 3356 #define regBIF_CFG_DEV0_EPF0_VF6_COMMAND_BASE_IDX 5 3357 #define regBIF_CFG_DEV0_EPF0_VF6_STATUS 0x19801 3358 #define regBIF_CFG_DEV0_EPF0_VF6_STATUS_BASE_IDX 5 3359 #define regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID 0x19802 3360 #define regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID_BASE_IDX 5 3361 #define regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE 0x19802 3362 #define regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE_BASE_IDX 5 3363 #define regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS 0x19802 3364 #define regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS_BASE_IDX 5 3365 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS 0x19802 3366 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS_BASE_IDX 5 3367 #define regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE 0x19803 3368 #define regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE_BASE_IDX 5 3369 #define regBIF_CFG_DEV0_EPF0_VF6_LATENCY 0x19803 3370 #define regBIF_CFG_DEV0_EPF0_VF6_LATENCY_BASE_IDX 5 3371 #define regBIF_CFG_DEV0_EPF0_VF6_HEADER 0x19803 3372 #define regBIF_CFG_DEV0_EPF0_VF6_HEADER_BASE_IDX 5 3373 #define regBIF_CFG_DEV0_EPF0_VF6_BIST 0x19803 3374 #define regBIF_CFG_DEV0_EPF0_VF6_BIST_BASE_IDX 5 3375 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 0x19804 3376 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1_BASE_IDX 5 3377 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 0x19805 3378 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2_BASE_IDX 5 3379 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 0x19806 3380 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3_BASE_IDX 5 3381 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 0x19807 3382 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4_BASE_IDX 5 3383 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 0x19808 3384 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5_BASE_IDX 5 3385 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 0x19809 3386 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6_BASE_IDX 5 3387 #define regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR 0x1980a 3388 #define regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR_BASE_IDX 5 3389 #define regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID 0x1980b 3390 #define regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID_BASE_IDX 5 3391 #define regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR 0x1980c 3392 #define regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR_BASE_IDX 5 3393 #define regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR 0x1980d 3394 #define regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR_BASE_IDX 5 3395 #define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE 0x1980f 3396 #define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE_BASE_IDX 5 3397 #define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN 0x1980f 3398 #define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN_BASE_IDX 5 3399 #define regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT 0x1980f 3400 #define regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT_BASE_IDX 5 3401 #define regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY 0x1980f 3402 #define regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY_BASE_IDX 5 3403 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST 0x19819 3404 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST_BASE_IDX 5 3405 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP 0x19819 3406 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_BASE_IDX 5 3407 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP 0x1981a 3408 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP_BASE_IDX 5 3409 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL 0x1981b 3410 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL_BASE_IDX 5 3411 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS 0x1981b 3412 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS_BASE_IDX 5 3413 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP 0x1981c 3414 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP_BASE_IDX 5 3415 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL 0x1981d 3416 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL_BASE_IDX 5 3417 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS 0x1981d 3418 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS_BASE_IDX 5 3419 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 0x19822 3420 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2_BASE_IDX 5 3421 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 0x19823 3422 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2_BASE_IDX 5 3423 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 0x19823 3424 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2_BASE_IDX 5 3425 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 0x19824 3426 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2_BASE_IDX 5 3427 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 0x19825 3428 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2_BASE_IDX 5 3429 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 0x19825 3430 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2_BASE_IDX 5 3431 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST 0x19828 3432 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST_BASE_IDX 5 3433 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL 0x19828 3434 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL_BASE_IDX 5 3435 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO 0x19829 3436 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO_BASE_IDX 5 3437 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI 0x1982a 3438 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI_BASE_IDX 5 3439 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA 0x1982a 3440 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_BASE_IDX 5 3441 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA 0x1982a 3442 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_BASE_IDX 5 3443 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK 0x1982b 3444 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_BASE_IDX 5 3445 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 0x1982b 3446 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64_BASE_IDX 5 3447 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 0x1982b 3448 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64_BASE_IDX 5 3449 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 0x1982c 3450 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64_BASE_IDX 5 3451 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING 0x1982c 3452 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_BASE_IDX 5 3453 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 0x1982d 3454 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64_BASE_IDX 5 3455 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST 0x19830 3456 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST_BASE_IDX 5 3457 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL 0x19830 3458 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL_BASE_IDX 5 3459 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE 0x19831 3460 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE_BASE_IDX 5 3461 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA 0x19832 3462 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA_BASE_IDX 5 3463 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x19840 3464 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 3465 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR 0x19841 3466 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 3467 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 0x19842 3468 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 3469 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 0x19843 3470 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 3471 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x19854 3472 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 3473 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS 0x19855 3474 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 3475 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK 0x19856 3476 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 3477 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY 0x19857 3478 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 3479 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS 0x19858 3480 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS_BASE_IDX 5 3481 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK 0x19859 3482 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK_BASE_IDX 5 3483 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL 0x1985a 3484 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 3485 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 0x1985b 3486 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0_BASE_IDX 5 3487 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 0x1985c 3488 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1_BASE_IDX 5 3489 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 0x1985d 3490 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2_BASE_IDX 5 3491 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 0x1985e 3492 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3_BASE_IDX 5 3493 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 0x19862 3494 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 3495 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 0x19863 3496 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 3497 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 0x19864 3498 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 3499 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 0x19865 3500 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 3501 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST 0x198ca 3502 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 3503 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP 0x198cb 3504 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP_BASE_IDX 5 3505 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL 0x198cb 3506 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL_BASE_IDX 5 3507 3508 3509 // addressBlock: nbif_bif_cfg_dev0_epf0_vf7_bifcfgdecp 3510 // base address: 0x10167000 3511 #define regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID 0x19c00 3512 #define regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID_BASE_IDX 5 3513 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID 0x19c00 3514 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID_BASE_IDX 5 3515 #define regBIF_CFG_DEV0_EPF0_VF7_COMMAND 0x19c01 3516 #define regBIF_CFG_DEV0_EPF0_VF7_COMMAND_BASE_IDX 5 3517 #define regBIF_CFG_DEV0_EPF0_VF7_STATUS 0x19c01 3518 #define regBIF_CFG_DEV0_EPF0_VF7_STATUS_BASE_IDX 5 3519 #define regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID 0x19c02 3520 #define regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID_BASE_IDX 5 3521 #define regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE 0x19c02 3522 #define regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE_BASE_IDX 5 3523 #define regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS 0x19c02 3524 #define regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS_BASE_IDX 5 3525 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS 0x19c02 3526 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS_BASE_IDX 5 3527 #define regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE 0x19c03 3528 #define regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE_BASE_IDX 5 3529 #define regBIF_CFG_DEV0_EPF0_VF7_LATENCY 0x19c03 3530 #define regBIF_CFG_DEV0_EPF0_VF7_LATENCY_BASE_IDX 5 3531 #define regBIF_CFG_DEV0_EPF0_VF7_HEADER 0x19c03 3532 #define regBIF_CFG_DEV0_EPF0_VF7_HEADER_BASE_IDX 5 3533 #define regBIF_CFG_DEV0_EPF0_VF7_BIST 0x19c03 3534 #define regBIF_CFG_DEV0_EPF0_VF7_BIST_BASE_IDX 5 3535 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 0x19c04 3536 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1_BASE_IDX 5 3537 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 0x19c05 3538 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2_BASE_IDX 5 3539 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 0x19c06 3540 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3_BASE_IDX 5 3541 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 0x19c07 3542 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4_BASE_IDX 5 3543 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 0x19c08 3544 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5_BASE_IDX 5 3545 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 0x19c09 3546 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6_BASE_IDX 5 3547 #define regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR 0x19c0a 3548 #define regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR_BASE_IDX 5 3549 #define regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID 0x19c0b 3550 #define regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID_BASE_IDX 5 3551 #define regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR 0x19c0c 3552 #define regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR_BASE_IDX 5 3553 #define regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR 0x19c0d 3554 #define regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR_BASE_IDX 5 3555 #define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE 0x19c0f 3556 #define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE_BASE_IDX 5 3557 #define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN 0x19c0f 3558 #define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN_BASE_IDX 5 3559 #define regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT 0x19c0f 3560 #define regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT_BASE_IDX 5 3561 #define regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY 0x19c0f 3562 #define regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY_BASE_IDX 5 3563 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST 0x19c19 3564 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST_BASE_IDX 5 3565 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP 0x19c19 3566 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_BASE_IDX 5 3567 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP 0x19c1a 3568 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP_BASE_IDX 5 3569 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL 0x19c1b 3570 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL_BASE_IDX 5 3571 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS 0x19c1b 3572 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS_BASE_IDX 5 3573 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP 0x19c1c 3574 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP_BASE_IDX 5 3575 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL 0x19c1d 3576 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL_BASE_IDX 5 3577 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS 0x19c1d 3578 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS_BASE_IDX 5 3579 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 0x19c22 3580 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2_BASE_IDX 5 3581 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 0x19c23 3582 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2_BASE_IDX 5 3583 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 0x19c23 3584 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2_BASE_IDX 5 3585 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 0x19c24 3586 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2_BASE_IDX 5 3587 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 0x19c25 3588 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2_BASE_IDX 5 3589 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 0x19c25 3590 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2_BASE_IDX 5 3591 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST 0x19c28 3592 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST_BASE_IDX 5 3593 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL 0x19c28 3594 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL_BASE_IDX 5 3595 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO 0x19c29 3596 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO_BASE_IDX 5 3597 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI 0x19c2a 3598 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI_BASE_IDX 5 3599 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA 0x19c2a 3600 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_BASE_IDX 5 3601 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA 0x19c2a 3602 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_BASE_IDX 5 3603 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK 0x19c2b 3604 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_BASE_IDX 5 3605 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 0x19c2b 3606 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64_BASE_IDX 5 3607 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 0x19c2b 3608 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64_BASE_IDX 5 3609 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 0x19c2c 3610 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64_BASE_IDX 5 3611 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING 0x19c2c 3612 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_BASE_IDX 5 3613 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 0x19c2d 3614 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64_BASE_IDX 5 3615 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST 0x19c30 3616 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST_BASE_IDX 5 3617 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL 0x19c30 3618 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL_BASE_IDX 5 3619 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE 0x19c31 3620 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE_BASE_IDX 5 3621 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA 0x19c32 3622 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA_BASE_IDX 5 3623 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x19c40 3624 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 3625 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR 0x19c41 3626 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 3627 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 0x19c42 3628 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 3629 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 0x19c43 3630 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 3631 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x19c54 3632 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 3633 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS 0x19c55 3634 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 3635 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK 0x19c56 3636 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 3637 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY 0x19c57 3638 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 3639 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS 0x19c58 3640 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS_BASE_IDX 5 3641 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK 0x19c59 3642 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK_BASE_IDX 5 3643 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL 0x19c5a 3644 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 3645 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 0x19c5b 3646 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0_BASE_IDX 5 3647 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 0x19c5c 3648 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1_BASE_IDX 5 3649 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 0x19c5d 3650 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2_BASE_IDX 5 3651 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 0x19c5e 3652 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3_BASE_IDX 5 3653 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 0x19c62 3654 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 3655 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 0x19c63 3656 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 3657 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 0x19c64 3658 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 3659 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 0x19c65 3660 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 3661 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST 0x19cca 3662 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 3663 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP 0x19ccb 3664 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP_BASE_IDX 5 3665 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL 0x19ccb 3666 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL_BASE_IDX 5 3667 3668 3669 // addressBlock: nbif_bif_cfg_dev0_epf1_bifcfgdecp 3670 // base address: 0x10141000 3671 #define regBIF_CFG_DEV0_EPF1_VENDOR_ID 0x10400 3672 #define regBIF_CFG_DEV0_EPF1_VENDOR_ID_BASE_IDX 5 3673 #define regBIF_CFG_DEV0_EPF1_DEVICE_ID 0x10400 3674 #define regBIF_CFG_DEV0_EPF1_DEVICE_ID_BASE_IDX 5 3675 #define regBIF_CFG_DEV0_EPF1_COMMAND 0x10401 3676 #define regBIF_CFG_DEV0_EPF1_COMMAND_BASE_IDX 5 3677 #define regBIF_CFG_DEV0_EPF1_STATUS 0x10401 3678 #define regBIF_CFG_DEV0_EPF1_STATUS_BASE_IDX 5 3679 #define regBIF_CFG_DEV0_EPF1_REVISION_ID 0x10402 3680 #define regBIF_CFG_DEV0_EPF1_REVISION_ID_BASE_IDX 5 3681 #define regBIF_CFG_DEV0_EPF1_PROG_INTERFACE 0x10402 3682 #define regBIF_CFG_DEV0_EPF1_PROG_INTERFACE_BASE_IDX 5 3683 #define regBIF_CFG_DEV0_EPF1_SUB_CLASS 0x10402 3684 #define regBIF_CFG_DEV0_EPF1_SUB_CLASS_BASE_IDX 5 3685 #define regBIF_CFG_DEV0_EPF1_BASE_CLASS 0x10402 3686 #define regBIF_CFG_DEV0_EPF1_BASE_CLASS_BASE_IDX 5 3687 #define regBIF_CFG_DEV0_EPF1_CACHE_LINE 0x10403 3688 #define regBIF_CFG_DEV0_EPF1_CACHE_LINE_BASE_IDX 5 3689 #define regBIF_CFG_DEV0_EPF1_LATENCY 0x10403 3690 #define regBIF_CFG_DEV0_EPF1_LATENCY_BASE_IDX 5 3691 #define regBIF_CFG_DEV0_EPF1_HEADER 0x10403 3692 #define regBIF_CFG_DEV0_EPF1_HEADER_BASE_IDX 5 3693 #define regBIF_CFG_DEV0_EPF1_BIST 0x10403 3694 #define regBIF_CFG_DEV0_EPF1_BIST_BASE_IDX 5 3695 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_1 0x10404 3696 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_1_BASE_IDX 5 3697 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_2 0x10405 3698 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_2_BASE_IDX 5 3699 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_3 0x10406 3700 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_3_BASE_IDX 5 3701 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_4 0x10407 3702 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_4_BASE_IDX 5 3703 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_5 0x10408 3704 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_5_BASE_IDX 5 3705 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_6 0x10409 3706 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_6_BASE_IDX 5 3707 #define regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR 0x1040a 3708 #define regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR_BASE_IDX 5 3709 #define regBIF_CFG_DEV0_EPF1_ADAPTER_ID 0x1040b 3710 #define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_BASE_IDX 5 3711 #define regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR 0x1040c 3712 #define regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR_BASE_IDX 5 3713 #define regBIF_CFG_DEV0_EPF1_CAP_PTR 0x1040d 3714 #define regBIF_CFG_DEV0_EPF1_CAP_PTR_BASE_IDX 5 3715 #define regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE 0x1040f 3716 #define regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE_BASE_IDX 5 3717 #define regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN 0x1040f 3718 #define regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN_BASE_IDX 5 3719 #define regBIF_CFG_DEV0_EPF1_MIN_GRANT 0x1040f 3720 #define regBIF_CFG_DEV0_EPF1_MIN_GRANT_BASE_IDX 5 3721 #define regBIF_CFG_DEV0_EPF1_MAX_LATENCY 0x1040f 3722 #define regBIF_CFG_DEV0_EPF1_MAX_LATENCY_BASE_IDX 5 3723 #define regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST 0x10412 3724 #define regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST_BASE_IDX 5 3725 #define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W 0x10413 3726 #define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W_BASE_IDX 5 3727 #define regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST 0x10414 3728 #define regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST_BASE_IDX 5 3729 #define regBIF_CFG_DEV0_EPF1_PMI_CAP 0x10414 3730 #define regBIF_CFG_DEV0_EPF1_PMI_CAP_BASE_IDX 5 3731 #define regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL 0x10415 3732 #define regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL_BASE_IDX 5 3733 #define regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST 0x10419 3734 #define regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST_BASE_IDX 5 3735 #define regBIF_CFG_DEV0_EPF1_PCIE_CAP 0x10419 3736 #define regBIF_CFG_DEV0_EPF1_PCIE_CAP_BASE_IDX 5 3737 #define regBIF_CFG_DEV0_EPF1_DEVICE_CAP 0x1041a 3738 #define regBIF_CFG_DEV0_EPF1_DEVICE_CAP_BASE_IDX 5 3739 #define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL 0x1041b 3740 #define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL_BASE_IDX 5 3741 #define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS 0x1041b 3742 #define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS_BASE_IDX 5 3743 #define regBIF_CFG_DEV0_EPF1_LINK_CAP 0x1041c 3744 #define regBIF_CFG_DEV0_EPF1_LINK_CAP_BASE_IDX 5 3745 #define regBIF_CFG_DEV0_EPF1_LINK_CNTL 0x1041d 3746 #define regBIF_CFG_DEV0_EPF1_LINK_CNTL_BASE_IDX 5 3747 #define regBIF_CFG_DEV0_EPF1_LINK_STATUS 0x1041d 3748 #define regBIF_CFG_DEV0_EPF1_LINK_STATUS_BASE_IDX 5 3749 #define regBIF_CFG_DEV0_EPF1_DEVICE_CAP2 0x10422 3750 #define regBIF_CFG_DEV0_EPF1_DEVICE_CAP2_BASE_IDX 5 3751 #define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2 0x10423 3752 #define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2_BASE_IDX 5 3753 #define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2 0x10423 3754 #define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2_BASE_IDX 5 3755 #define regBIF_CFG_DEV0_EPF1_LINK_CAP2 0x10424 3756 #define regBIF_CFG_DEV0_EPF1_LINK_CAP2_BASE_IDX 5 3757 #define regBIF_CFG_DEV0_EPF1_LINK_CNTL2 0x10425 3758 #define regBIF_CFG_DEV0_EPF1_LINK_CNTL2_BASE_IDX 5 3759 #define regBIF_CFG_DEV0_EPF1_LINK_STATUS2 0x10425 3760 #define regBIF_CFG_DEV0_EPF1_LINK_STATUS2_BASE_IDX 5 3761 #define regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST 0x10428 3762 #define regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST_BASE_IDX 5 3763 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL 0x10428 3764 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL_BASE_IDX 5 3765 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO 0x10429 3766 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO_BASE_IDX 5 3767 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI 0x1042a 3768 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI_BASE_IDX 5 3769 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA 0x1042a 3770 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_BASE_IDX 5 3771 #define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA 0x1042a 3772 #define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_BASE_IDX 5 3773 #define regBIF_CFG_DEV0_EPF1_MSI_MASK 0x1042b 3774 #define regBIF_CFG_DEV0_EPF1_MSI_MASK_BASE_IDX 5 3775 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 0x1042b 3776 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64_BASE_IDX 5 3777 #define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 0x1042b 3778 #define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 3779 #define regBIF_CFG_DEV0_EPF1_MSI_MASK_64 0x1042c 3780 #define regBIF_CFG_DEV0_EPF1_MSI_MASK_64_BASE_IDX 5 3781 #define regBIF_CFG_DEV0_EPF1_MSI_PENDING 0x1042c 3782 #define regBIF_CFG_DEV0_EPF1_MSI_PENDING_BASE_IDX 5 3783 #define regBIF_CFG_DEV0_EPF1_MSI_PENDING_64 0x1042d 3784 #define regBIF_CFG_DEV0_EPF1_MSI_PENDING_64_BASE_IDX 5 3785 #define regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST 0x10430 3786 #define regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST_BASE_IDX 5 3787 #define regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL 0x10430 3788 #define regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL_BASE_IDX 5 3789 #define regBIF_CFG_DEV0_EPF1_MSIX_TABLE 0x10431 3790 #define regBIF_CFG_DEV0_EPF1_MSIX_TABLE_BASE_IDX 5 3791 #define regBIF_CFG_DEV0_EPF1_MSIX_PBA 0x10432 3792 #define regBIF_CFG_DEV0_EPF1_MSIX_PBA_BASE_IDX 5 3793 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10440 3794 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 3795 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR 0x10441 3796 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 3797 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 0x10442 3798 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 3799 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 0x10443 3800 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 3801 #define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x10450 3802 #define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 3803 #define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1 0x10451 3804 #define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 3805 #define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2 0x10452 3806 #define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 3807 #define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10454 3808 #define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 3809 #define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS 0x10455 3810 #define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 3811 #define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK 0x10456 3812 #define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 3813 #define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY 0x10457 3814 #define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 3815 #define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS 0x10458 3816 #define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 3817 #define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK 0x10459 3818 #define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK_BASE_IDX 5 3819 #define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL 0x1045a 3820 #define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 3821 #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 0x1045b 3822 #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0_BASE_IDX 5 3823 #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 0x1045c 3824 #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1_BASE_IDX 5 3825 #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 0x1045d 3826 #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2_BASE_IDX 5 3827 #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 0x1045e 3828 #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3_BASE_IDX 5 3829 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 0x10462 3830 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 3831 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 0x10463 3832 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 3833 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 0x10464 3834 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 3835 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 0x10465 3836 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 3837 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST 0x10480 3838 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 3839 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP 0x10481 3840 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP_BASE_IDX 5 3841 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL 0x10482 3842 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL_BASE_IDX 5 3843 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP 0x10483 3844 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP_BASE_IDX 5 3845 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL 0x10484 3846 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL_BASE_IDX 5 3847 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP 0x10485 3848 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP_BASE_IDX 5 3849 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL 0x10486 3850 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL_BASE_IDX 5 3851 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP 0x10487 3852 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP_BASE_IDX 5 3853 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL 0x10488 3854 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL_BASE_IDX 5 3855 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP 0x10489 3856 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP_BASE_IDX 5 3857 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL 0x1048a 3858 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL_BASE_IDX 5 3859 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP 0x1048b 3860 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP_BASE_IDX 5 3861 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL 0x1048c 3862 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL_BASE_IDX 5 3863 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10490 3864 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 3865 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT 0x10491 3866 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 3867 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA 0x10492 3868 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 3869 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP 0x10493 3870 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 3871 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST 0x10494 3872 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 3873 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP 0x10495 3874 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP_BASE_IDX 5 3875 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR 0x10496 3876 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 3877 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS 0x10497 3878 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS_BASE_IDX 5 3879 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL 0x10497 3880 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL_BASE_IDX 5 3881 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10498 3882 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 3883 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10498 3884 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 3885 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10498 3886 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 3887 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10498 3888 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 3889 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10499 3890 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 3891 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10499 3892 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 3893 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10499 3894 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 3895 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10499 3896 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 3897 #define regBIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST 0x1049c 3898 #define regBIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 3899 #define regBIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3 0x1049d 3900 #define regBIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3_BASE_IDX 5 3901 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS 0x1049e 3902 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 3903 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL 0x1049f 3904 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 3905 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL 0x1049f 3906 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 3907 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL 0x104a0 3908 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 3909 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL 0x104a0 3910 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 3911 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL 0x104a1 3912 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 3913 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL 0x104a1 3914 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 3915 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL 0x104a2 3916 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 3917 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL 0x104a2 3918 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 3919 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL 0x104a3 3920 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 3921 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL 0x104a3 3922 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 3923 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL 0x104a4 3924 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 3925 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL 0x104a4 3926 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 3927 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL 0x104a5 3928 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 3929 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL 0x104a5 3930 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 3931 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL 0x104a6 3932 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 3933 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL 0x104a6 3934 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 3935 #define regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST 0x104a8 3936 #define regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 3937 #define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP 0x104a9 3938 #define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP_BASE_IDX 5 3939 #define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL 0x104a9 3940 #define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL_BASE_IDX 5 3941 #define regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST 0x104b4 3942 #define regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 3943 #define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP 0x104b5 3944 #define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP_BASE_IDX 5 3945 #define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL 0x104b5 3946 #define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL_BASE_IDX 5 3947 #define regBIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST 0x104c8 3948 #define regBIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 5 3949 #define regBIF_CFG_DEV0_EPF1_PCIE_LTR_CAP 0x104c9 3950 #define regBIF_CFG_DEV0_EPF1_PCIE_LTR_CAP_BASE_IDX 5 3951 #define regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST 0x104ca 3952 #define regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 3953 #define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP 0x104cb 3954 #define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP_BASE_IDX 5 3955 #define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL 0x104cb 3956 #define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL_BASE_IDX 5 3957 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST 0x104cc 3958 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 5 3959 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP 0x104cd 3960 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP_BASE_IDX 5 3961 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL 0x104ce 3962 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL_BASE_IDX 5 3963 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS 0x104ce 3964 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS_BASE_IDX 5 3965 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS 0x104cf 3966 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 5 3967 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS 0x104cf 3968 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 5 3969 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS 0x104d0 3970 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS_BASE_IDX 5 3971 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK 0x104d0 3972 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 5 3973 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET 0x104d1 3974 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 5 3975 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE 0x104d1 3976 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE_BASE_IDX 5 3977 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID 0x104d2 3978 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 5 3979 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x104d3 3980 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 5 3981 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x104d4 3982 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 5 3983 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0 0x104d5 3984 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 5 3985 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1 0x104d6 3986 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 5 3987 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2 0x104d7 3988 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 5 3989 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3 0x104d8 3990 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 5 3991 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4 0x104d9 3992 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 5 3993 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5 0x104da 3994 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 5 3995 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x104db 3996 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 5 3997 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x10530 3998 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX 5 3999 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP 0x10531 4000 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX 5 4001 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL 0x10532 4002 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX 5 4003 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP 0x10533 4004 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX 5 4005 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL 0x10534 4006 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX 5 4007 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP 0x10535 4008 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX 5 4009 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL 0x10536 4010 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX 5 4011 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP 0x10537 4012 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX 5 4013 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL 0x10538 4014 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX 5 4015 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP 0x10539 4016 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX 5 4017 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL 0x1053a 4018 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX 5 4019 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP 0x1053b 4020 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX 5 4021 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL 0x1053c 4022 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX 5 4023 4024 4025 // addressBlock: nbif_bif_cfg_dev0_epf2_bifcfgdecp 4026 // base address: 0x10142000 4027 #define regBIF_CFG_DEV0_EPF2_VENDOR_ID 0x10800 4028 #define regBIF_CFG_DEV0_EPF2_VENDOR_ID_BASE_IDX 5 4029 #define regBIF_CFG_DEV0_EPF2_DEVICE_ID 0x10800 4030 #define regBIF_CFG_DEV0_EPF2_DEVICE_ID_BASE_IDX 5 4031 #define regBIF_CFG_DEV0_EPF2_COMMAND 0x10801 4032 #define regBIF_CFG_DEV0_EPF2_COMMAND_BASE_IDX 5 4033 #define regBIF_CFG_DEV0_EPF2_STATUS 0x10801 4034 #define regBIF_CFG_DEV0_EPF2_STATUS_BASE_IDX 5 4035 #define regBIF_CFG_DEV0_EPF2_REVISION_ID 0x10802 4036 #define regBIF_CFG_DEV0_EPF2_REVISION_ID_BASE_IDX 5 4037 #define regBIF_CFG_DEV0_EPF2_PROG_INTERFACE 0x10802 4038 #define regBIF_CFG_DEV0_EPF2_PROG_INTERFACE_BASE_IDX 5 4039 #define regBIF_CFG_DEV0_EPF2_SUB_CLASS 0x10802 4040 #define regBIF_CFG_DEV0_EPF2_SUB_CLASS_BASE_IDX 5 4041 #define regBIF_CFG_DEV0_EPF2_BASE_CLASS 0x10802 4042 #define regBIF_CFG_DEV0_EPF2_BASE_CLASS_BASE_IDX 5 4043 #define regBIF_CFG_DEV0_EPF2_CACHE_LINE 0x10803 4044 #define regBIF_CFG_DEV0_EPF2_CACHE_LINE_BASE_IDX 5 4045 #define regBIF_CFG_DEV0_EPF2_LATENCY 0x10803 4046 #define regBIF_CFG_DEV0_EPF2_LATENCY_BASE_IDX 5 4047 #define regBIF_CFG_DEV0_EPF2_HEADER 0x10803 4048 #define regBIF_CFG_DEV0_EPF2_HEADER_BASE_IDX 5 4049 #define regBIF_CFG_DEV0_EPF2_BIST 0x10803 4050 #define regBIF_CFG_DEV0_EPF2_BIST_BASE_IDX 5 4051 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_1 0x10804 4052 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_1_BASE_IDX 5 4053 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_2 0x10805 4054 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_2_BASE_IDX 5 4055 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_3 0x10806 4056 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_3_BASE_IDX 5 4057 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_4 0x10807 4058 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_4_BASE_IDX 5 4059 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_5 0x10808 4060 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_5_BASE_IDX 5 4061 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_6 0x10809 4062 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_6_BASE_IDX 5 4063 #define regBIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR 0x1080a 4064 #define regBIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR_BASE_IDX 5 4065 #define regBIF_CFG_DEV0_EPF2_ADAPTER_ID 0x1080b 4066 #define regBIF_CFG_DEV0_EPF2_ADAPTER_ID_BASE_IDX 5 4067 #define regBIF_CFG_DEV0_EPF2_ROM_BASE_ADDR 0x1080c 4068 #define regBIF_CFG_DEV0_EPF2_ROM_BASE_ADDR_BASE_IDX 5 4069 #define regBIF_CFG_DEV0_EPF2_CAP_PTR 0x1080d 4070 #define regBIF_CFG_DEV0_EPF2_CAP_PTR_BASE_IDX 5 4071 #define regBIF_CFG_DEV0_EPF2_INTERRUPT_LINE 0x1080f 4072 #define regBIF_CFG_DEV0_EPF2_INTERRUPT_LINE_BASE_IDX 5 4073 #define regBIF_CFG_DEV0_EPF2_INTERRUPT_PIN 0x1080f 4074 #define regBIF_CFG_DEV0_EPF2_INTERRUPT_PIN_BASE_IDX 5 4075 #define regBIF_CFG_DEV0_EPF2_MIN_GRANT 0x1080f 4076 #define regBIF_CFG_DEV0_EPF2_MIN_GRANT_BASE_IDX 5 4077 #define regBIF_CFG_DEV0_EPF2_MAX_LATENCY 0x1080f 4078 #define regBIF_CFG_DEV0_EPF2_MAX_LATENCY_BASE_IDX 5 4079 #define regBIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST 0x10812 4080 #define regBIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST_BASE_IDX 5 4081 #define regBIF_CFG_DEV0_EPF2_ADAPTER_ID_W 0x10813 4082 #define regBIF_CFG_DEV0_EPF2_ADAPTER_ID_W_BASE_IDX 5 4083 #define regBIF_CFG_DEV0_EPF2_PMI_CAP_LIST 0x10814 4084 #define regBIF_CFG_DEV0_EPF2_PMI_CAP_LIST_BASE_IDX 5 4085 #define regBIF_CFG_DEV0_EPF2_PMI_CAP 0x10814 4086 #define regBIF_CFG_DEV0_EPF2_PMI_CAP_BASE_IDX 5 4087 #define regBIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL 0x10815 4088 #define regBIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL_BASE_IDX 5 4089 #define regBIF_CFG_DEV0_EPF2_SBRN 0x10818 4090 #define regBIF_CFG_DEV0_EPF2_SBRN_BASE_IDX 5 4091 #define regBIF_CFG_DEV0_EPF2_FLADJ 0x10818 4092 #define regBIF_CFG_DEV0_EPF2_FLADJ_BASE_IDX 5 4093 #define regBIF_CFG_DEV0_EPF2_DBESL_DBESLD 0x10818 4094 #define regBIF_CFG_DEV0_EPF2_DBESL_DBESLD_BASE_IDX 5 4095 #define regBIF_CFG_DEV0_EPF2_PCIE_CAP_LIST 0x10819 4096 #define regBIF_CFG_DEV0_EPF2_PCIE_CAP_LIST_BASE_IDX 5 4097 #define regBIF_CFG_DEV0_EPF2_PCIE_CAP 0x10819 4098 #define regBIF_CFG_DEV0_EPF2_PCIE_CAP_BASE_IDX 5 4099 #define regBIF_CFG_DEV0_EPF2_DEVICE_CAP 0x1081a 4100 #define regBIF_CFG_DEV0_EPF2_DEVICE_CAP_BASE_IDX 5 4101 #define regBIF_CFG_DEV0_EPF2_DEVICE_CNTL 0x1081b 4102 #define regBIF_CFG_DEV0_EPF2_DEVICE_CNTL_BASE_IDX 5 4103 #define regBIF_CFG_DEV0_EPF2_DEVICE_STATUS 0x1081b 4104 #define regBIF_CFG_DEV0_EPF2_DEVICE_STATUS_BASE_IDX 5 4105 #define regBIF_CFG_DEV0_EPF2_LINK_CAP 0x1081c 4106 #define regBIF_CFG_DEV0_EPF2_LINK_CAP_BASE_IDX 5 4107 #define regBIF_CFG_DEV0_EPF2_LINK_CNTL 0x1081d 4108 #define regBIF_CFG_DEV0_EPF2_LINK_CNTL_BASE_IDX 5 4109 #define regBIF_CFG_DEV0_EPF2_LINK_STATUS 0x1081d 4110 #define regBIF_CFG_DEV0_EPF2_LINK_STATUS_BASE_IDX 5 4111 #define regBIF_CFG_DEV0_EPF2_DEVICE_CAP2 0x10822 4112 #define regBIF_CFG_DEV0_EPF2_DEVICE_CAP2_BASE_IDX 5 4113 #define regBIF_CFG_DEV0_EPF2_DEVICE_CNTL2 0x10823 4114 #define regBIF_CFG_DEV0_EPF2_DEVICE_CNTL2_BASE_IDX 5 4115 #define regBIF_CFG_DEV0_EPF2_DEVICE_STATUS2 0x10823 4116 #define regBIF_CFG_DEV0_EPF2_DEVICE_STATUS2_BASE_IDX 5 4117 #define regBIF_CFG_DEV0_EPF2_LINK_CAP2 0x10824 4118 #define regBIF_CFG_DEV0_EPF2_LINK_CAP2_BASE_IDX 5 4119 #define regBIF_CFG_DEV0_EPF2_LINK_CNTL2 0x10825 4120 #define regBIF_CFG_DEV0_EPF2_LINK_CNTL2_BASE_IDX 5 4121 #define regBIF_CFG_DEV0_EPF2_LINK_STATUS2 0x10825 4122 #define regBIF_CFG_DEV0_EPF2_LINK_STATUS2_BASE_IDX 5 4123 #define regBIF_CFG_DEV0_EPF2_MSI_CAP_LIST 0x10828 4124 #define regBIF_CFG_DEV0_EPF2_MSI_CAP_LIST_BASE_IDX 5 4125 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_CNTL 0x10828 4126 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_CNTL_BASE_IDX 5 4127 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO 0x10829 4128 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO_BASE_IDX 5 4129 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI 0x1082a 4130 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI_BASE_IDX 5 4131 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA 0x1082a 4132 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_BASE_IDX 5 4133 #define regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA 0x1082a 4134 #define regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_BASE_IDX 5 4135 #define regBIF_CFG_DEV0_EPF2_MSI_MASK 0x1082b 4136 #define regBIF_CFG_DEV0_EPF2_MSI_MASK_BASE_IDX 5 4137 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64 0x1082b 4138 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64_BASE_IDX 5 4139 #define regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64 0x1082b 4140 #define regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64_BASE_IDX 5 4141 #define regBIF_CFG_DEV0_EPF2_MSI_MASK_64 0x1082c 4142 #define regBIF_CFG_DEV0_EPF2_MSI_MASK_64_BASE_IDX 5 4143 #define regBIF_CFG_DEV0_EPF2_MSI_PENDING 0x1082c 4144 #define regBIF_CFG_DEV0_EPF2_MSI_PENDING_BASE_IDX 5 4145 #define regBIF_CFG_DEV0_EPF2_MSI_PENDING_64 0x1082d 4146 #define regBIF_CFG_DEV0_EPF2_MSI_PENDING_64_BASE_IDX 5 4147 #define regBIF_CFG_DEV0_EPF2_MSIX_CAP_LIST 0x10830 4148 #define regBIF_CFG_DEV0_EPF2_MSIX_CAP_LIST_BASE_IDX 5 4149 #define regBIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL 0x10830 4150 #define regBIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL_BASE_IDX 5 4151 #define regBIF_CFG_DEV0_EPF2_MSIX_TABLE 0x10831 4152 #define regBIF_CFG_DEV0_EPF2_MSIX_TABLE_BASE_IDX 5 4153 #define regBIF_CFG_DEV0_EPF2_MSIX_PBA 0x10832 4154 #define regBIF_CFG_DEV0_EPF2_MSIX_PBA_BASE_IDX 5 4155 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10840 4156 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 4157 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR 0x10841 4158 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 4159 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1 0x10842 4160 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 4161 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2 0x10843 4162 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 4163 #define regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10854 4164 #define regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 4165 #define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS 0x10855 4166 #define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 4167 #define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK 0x10856 4168 #define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 4169 #define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY 0x10857 4170 #define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 4171 #define regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS 0x10858 4172 #define regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS_BASE_IDX 5 4173 #define regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK 0x10859 4174 #define regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK_BASE_IDX 5 4175 #define regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL 0x1085a 4176 #define regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 4177 #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0 0x1085b 4178 #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0_BASE_IDX 5 4179 #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1 0x1085c 4180 #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1_BASE_IDX 5 4181 #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2 0x1085d 4182 #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2_BASE_IDX 5 4183 #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3 0x1085e 4184 #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3_BASE_IDX 5 4185 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0 0x10862 4186 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 4187 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1 0x10863 4188 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 4189 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2 0x10864 4190 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 4191 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3 0x10865 4192 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 4193 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST 0x10880 4194 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 4195 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP 0x10881 4196 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP_BASE_IDX 5 4197 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL 0x10882 4198 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL_BASE_IDX 5 4199 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP 0x10883 4200 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP_BASE_IDX 5 4201 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL 0x10884 4202 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL_BASE_IDX 5 4203 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP 0x10885 4204 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP_BASE_IDX 5 4205 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL 0x10886 4206 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL_BASE_IDX 5 4207 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP 0x10887 4208 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP_BASE_IDX 5 4209 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL 0x10888 4210 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL_BASE_IDX 5 4211 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP 0x10889 4212 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP_BASE_IDX 5 4213 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL 0x1088a 4214 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL_BASE_IDX 5 4215 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP 0x1088b 4216 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP_BASE_IDX 5 4217 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL 0x1088c 4218 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL_BASE_IDX 5 4219 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10890 4220 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 4221 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT 0x10891 4222 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 4223 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA 0x10892 4224 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 4225 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP 0x10893 4226 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 4227 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST 0x10894 4228 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 4229 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_CAP 0x10895 4230 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_CAP_BASE_IDX 5 4231 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR 0x10896 4232 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 4233 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS 0x10897 4234 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS_BASE_IDX 5 4235 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL 0x10897 4236 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL_BASE_IDX 5 4237 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10898 4238 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 4239 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10898 4240 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 4241 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10898 4242 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 4243 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10898 4244 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 4245 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10899 4246 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 4247 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10899 4248 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 4249 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10899 4250 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 4251 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10899 4252 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 4253 #define regBIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST 0x108a8 4254 #define regBIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 4255 #define regBIF_CFG_DEV0_EPF2_PCIE_ACS_CAP 0x108a9 4256 #define regBIF_CFG_DEV0_EPF2_PCIE_ACS_CAP_BASE_IDX 5 4257 #define regBIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL 0x108a9 4258 #define regBIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL_BASE_IDX 5 4259 #define regBIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST 0x108b4 4260 #define regBIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 4261 #define regBIF_CFG_DEV0_EPF2_PCIE_PASID_CAP 0x108b5 4262 #define regBIF_CFG_DEV0_EPF2_PCIE_PASID_CAP_BASE_IDX 5 4263 #define regBIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL 0x108b5 4264 #define regBIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL_BASE_IDX 5 4265 #define regBIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST 0x108ca 4266 #define regBIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 4267 #define regBIF_CFG_DEV0_EPF2_PCIE_ARI_CAP 0x108cb 4268 #define regBIF_CFG_DEV0_EPF2_PCIE_ARI_CAP_BASE_IDX 5 4269 #define regBIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL 0x108cb 4270 #define regBIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL_BASE_IDX 5 4271 4272 4273 // addressBlock: nbif_bif_cfg_dev0_epf3_bifcfgdecp 4274 // base address: 0x10143000 4275 #define regBIF_CFG_DEV0_EPF3_VENDOR_ID 0x10c00 4276 #define regBIF_CFG_DEV0_EPF3_VENDOR_ID_BASE_IDX 5 4277 #define regBIF_CFG_DEV0_EPF3_DEVICE_ID 0x10c00 4278 #define regBIF_CFG_DEV0_EPF3_DEVICE_ID_BASE_IDX 5 4279 #define regBIF_CFG_DEV0_EPF3_COMMAND 0x10c01 4280 #define regBIF_CFG_DEV0_EPF3_COMMAND_BASE_IDX 5 4281 #define regBIF_CFG_DEV0_EPF3_STATUS 0x10c01 4282 #define regBIF_CFG_DEV0_EPF3_STATUS_BASE_IDX 5 4283 #define regBIF_CFG_DEV0_EPF3_REVISION_ID 0x10c02 4284 #define regBIF_CFG_DEV0_EPF3_REVISION_ID_BASE_IDX 5 4285 #define regBIF_CFG_DEV0_EPF3_PROG_INTERFACE 0x10c02 4286 #define regBIF_CFG_DEV0_EPF3_PROG_INTERFACE_BASE_IDX 5 4287 #define regBIF_CFG_DEV0_EPF3_SUB_CLASS 0x10c02 4288 #define regBIF_CFG_DEV0_EPF3_SUB_CLASS_BASE_IDX 5 4289 #define regBIF_CFG_DEV0_EPF3_BASE_CLASS 0x10c02 4290 #define regBIF_CFG_DEV0_EPF3_BASE_CLASS_BASE_IDX 5 4291 #define regBIF_CFG_DEV0_EPF3_CACHE_LINE 0x10c03 4292 #define regBIF_CFG_DEV0_EPF3_CACHE_LINE_BASE_IDX 5 4293 #define regBIF_CFG_DEV0_EPF3_LATENCY 0x10c03 4294 #define regBIF_CFG_DEV0_EPF3_LATENCY_BASE_IDX 5 4295 #define regBIF_CFG_DEV0_EPF3_HEADER 0x10c03 4296 #define regBIF_CFG_DEV0_EPF3_HEADER_BASE_IDX 5 4297 #define regBIF_CFG_DEV0_EPF3_BIST 0x10c03 4298 #define regBIF_CFG_DEV0_EPF3_BIST_BASE_IDX 5 4299 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_1 0x10c04 4300 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_1_BASE_IDX 5 4301 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_2 0x10c05 4302 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_2_BASE_IDX 5 4303 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_3 0x10c06 4304 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_3_BASE_IDX 5 4305 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_4 0x10c07 4306 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_4_BASE_IDX 5 4307 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_5 0x10c08 4308 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_5_BASE_IDX 5 4309 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_6 0x10c09 4310 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_6_BASE_IDX 5 4311 #define regBIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR 0x10c0a 4312 #define regBIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR_BASE_IDX 5 4313 #define regBIF_CFG_DEV0_EPF3_ADAPTER_ID 0x10c0b 4314 #define regBIF_CFG_DEV0_EPF3_ADAPTER_ID_BASE_IDX 5 4315 #define regBIF_CFG_DEV0_EPF3_ROM_BASE_ADDR 0x10c0c 4316 #define regBIF_CFG_DEV0_EPF3_ROM_BASE_ADDR_BASE_IDX 5 4317 #define regBIF_CFG_DEV0_EPF3_CAP_PTR 0x10c0d 4318 #define regBIF_CFG_DEV0_EPF3_CAP_PTR_BASE_IDX 5 4319 #define regBIF_CFG_DEV0_EPF3_INTERRUPT_LINE 0x10c0f 4320 #define regBIF_CFG_DEV0_EPF3_INTERRUPT_LINE_BASE_IDX 5 4321 #define regBIF_CFG_DEV0_EPF3_INTERRUPT_PIN 0x10c0f 4322 #define regBIF_CFG_DEV0_EPF3_INTERRUPT_PIN_BASE_IDX 5 4323 #define regBIF_CFG_DEV0_EPF3_MIN_GRANT 0x10c0f 4324 #define regBIF_CFG_DEV0_EPF3_MIN_GRANT_BASE_IDX 5 4325 #define regBIF_CFG_DEV0_EPF3_MAX_LATENCY 0x10c0f 4326 #define regBIF_CFG_DEV0_EPF3_MAX_LATENCY_BASE_IDX 5 4327 #define regBIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST 0x10c12 4328 #define regBIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST_BASE_IDX 5 4329 #define regBIF_CFG_DEV0_EPF3_ADAPTER_ID_W 0x10c13 4330 #define regBIF_CFG_DEV0_EPF3_ADAPTER_ID_W_BASE_IDX 5 4331 #define regBIF_CFG_DEV0_EPF3_PMI_CAP_LIST 0x10c14 4332 #define regBIF_CFG_DEV0_EPF3_PMI_CAP_LIST_BASE_IDX 5 4333 #define regBIF_CFG_DEV0_EPF3_PMI_CAP 0x10c14 4334 #define regBIF_CFG_DEV0_EPF3_PMI_CAP_BASE_IDX 5 4335 #define regBIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL 0x10c15 4336 #define regBIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL_BASE_IDX 5 4337 #define regBIF_CFG_DEV0_EPF3_SBRN 0x10c18 4338 #define regBIF_CFG_DEV0_EPF3_SBRN_BASE_IDX 5 4339 #define regBIF_CFG_DEV0_EPF3_FLADJ 0x10c18 4340 #define regBIF_CFG_DEV0_EPF3_FLADJ_BASE_IDX 5 4341 #define regBIF_CFG_DEV0_EPF3_DBESL_DBESLD 0x10c18 4342 #define regBIF_CFG_DEV0_EPF3_DBESL_DBESLD_BASE_IDX 5 4343 #define regBIF_CFG_DEV0_EPF3_PCIE_CAP_LIST 0x10c19 4344 #define regBIF_CFG_DEV0_EPF3_PCIE_CAP_LIST_BASE_IDX 5 4345 #define regBIF_CFG_DEV0_EPF3_PCIE_CAP 0x10c19 4346 #define regBIF_CFG_DEV0_EPF3_PCIE_CAP_BASE_IDX 5 4347 #define regBIF_CFG_DEV0_EPF3_DEVICE_CAP 0x10c1a 4348 #define regBIF_CFG_DEV0_EPF3_DEVICE_CAP_BASE_IDX 5 4349 #define regBIF_CFG_DEV0_EPF3_DEVICE_CNTL 0x10c1b 4350 #define regBIF_CFG_DEV0_EPF3_DEVICE_CNTL_BASE_IDX 5 4351 #define regBIF_CFG_DEV0_EPF3_DEVICE_STATUS 0x10c1b 4352 #define regBIF_CFG_DEV0_EPF3_DEVICE_STATUS_BASE_IDX 5 4353 #define regBIF_CFG_DEV0_EPF3_LINK_CAP 0x10c1c 4354 #define regBIF_CFG_DEV0_EPF3_LINK_CAP_BASE_IDX 5 4355 #define regBIF_CFG_DEV0_EPF3_LINK_CNTL 0x10c1d 4356 #define regBIF_CFG_DEV0_EPF3_LINK_CNTL_BASE_IDX 5 4357 #define regBIF_CFG_DEV0_EPF3_LINK_STATUS 0x10c1d 4358 #define regBIF_CFG_DEV0_EPF3_LINK_STATUS_BASE_IDX 5 4359 #define regBIF_CFG_DEV0_EPF3_DEVICE_CAP2 0x10c22 4360 #define regBIF_CFG_DEV0_EPF3_DEVICE_CAP2_BASE_IDX 5 4361 #define regBIF_CFG_DEV0_EPF3_DEVICE_CNTL2 0x10c23 4362 #define regBIF_CFG_DEV0_EPF3_DEVICE_CNTL2_BASE_IDX 5 4363 #define regBIF_CFG_DEV0_EPF3_DEVICE_STATUS2 0x10c23 4364 #define regBIF_CFG_DEV0_EPF3_DEVICE_STATUS2_BASE_IDX 5 4365 #define regBIF_CFG_DEV0_EPF3_LINK_CAP2 0x10c24 4366 #define regBIF_CFG_DEV0_EPF3_LINK_CAP2_BASE_IDX 5 4367 #define regBIF_CFG_DEV0_EPF3_LINK_CNTL2 0x10c25 4368 #define regBIF_CFG_DEV0_EPF3_LINK_CNTL2_BASE_IDX 5 4369 #define regBIF_CFG_DEV0_EPF3_LINK_STATUS2 0x10c25 4370 #define regBIF_CFG_DEV0_EPF3_LINK_STATUS2_BASE_IDX 5 4371 #define regBIF_CFG_DEV0_EPF3_MSI_CAP_LIST 0x10c28 4372 #define regBIF_CFG_DEV0_EPF3_MSI_CAP_LIST_BASE_IDX 5 4373 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_CNTL 0x10c28 4374 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_CNTL_BASE_IDX 5 4375 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO 0x10c29 4376 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO_BASE_IDX 5 4377 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI 0x10c2a 4378 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI_BASE_IDX 5 4379 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA 0x10c2a 4380 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_BASE_IDX 5 4381 #define regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA 0x10c2a 4382 #define regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_BASE_IDX 5 4383 #define regBIF_CFG_DEV0_EPF3_MSI_MASK 0x10c2b 4384 #define regBIF_CFG_DEV0_EPF3_MSI_MASK_BASE_IDX 5 4385 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64 0x10c2b 4386 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64_BASE_IDX 5 4387 #define regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64 0x10c2b 4388 #define regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64_BASE_IDX 5 4389 #define regBIF_CFG_DEV0_EPF3_MSI_MASK_64 0x10c2c 4390 #define regBIF_CFG_DEV0_EPF3_MSI_MASK_64_BASE_IDX 5 4391 #define regBIF_CFG_DEV0_EPF3_MSI_PENDING 0x10c2c 4392 #define regBIF_CFG_DEV0_EPF3_MSI_PENDING_BASE_IDX 5 4393 #define regBIF_CFG_DEV0_EPF3_MSI_PENDING_64 0x10c2d 4394 #define regBIF_CFG_DEV0_EPF3_MSI_PENDING_64_BASE_IDX 5 4395 #define regBIF_CFG_DEV0_EPF3_MSIX_CAP_LIST 0x10c30 4396 #define regBIF_CFG_DEV0_EPF3_MSIX_CAP_LIST_BASE_IDX 5 4397 #define regBIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL 0x10c30 4398 #define regBIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL_BASE_IDX 5 4399 #define regBIF_CFG_DEV0_EPF3_MSIX_TABLE 0x10c31 4400 #define regBIF_CFG_DEV0_EPF3_MSIX_TABLE_BASE_IDX 5 4401 #define regBIF_CFG_DEV0_EPF3_MSIX_PBA 0x10c32 4402 #define regBIF_CFG_DEV0_EPF3_MSIX_PBA_BASE_IDX 5 4403 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10c40 4404 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 4405 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR 0x10c41 4406 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 4407 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1 0x10c42 4408 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 4409 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2 0x10c43 4410 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 4411 #define regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10c54 4412 #define regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 4413 #define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS 0x10c55 4414 #define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 4415 #define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK 0x10c56 4416 #define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 4417 #define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY 0x10c57 4418 #define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 4419 #define regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS 0x10c58 4420 #define regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS_BASE_IDX 5 4421 #define regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK 0x10c59 4422 #define regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK_BASE_IDX 5 4423 #define regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL 0x10c5a 4424 #define regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 4425 #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0 0x10c5b 4426 #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0_BASE_IDX 5 4427 #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1 0x10c5c 4428 #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1_BASE_IDX 5 4429 #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2 0x10c5d 4430 #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2_BASE_IDX 5 4431 #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3 0x10c5e 4432 #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3_BASE_IDX 5 4433 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0 0x10c62 4434 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 4435 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1 0x10c63 4436 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 4437 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2 0x10c64 4438 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 4439 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3 0x10c65 4440 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 4441 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST 0x10c80 4442 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 4443 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP 0x10c81 4444 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP_BASE_IDX 5 4445 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL 0x10c82 4446 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL_BASE_IDX 5 4447 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP 0x10c83 4448 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP_BASE_IDX 5 4449 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL 0x10c84 4450 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL_BASE_IDX 5 4451 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP 0x10c85 4452 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP_BASE_IDX 5 4453 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL 0x10c86 4454 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL_BASE_IDX 5 4455 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP 0x10c87 4456 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP_BASE_IDX 5 4457 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL 0x10c88 4458 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL_BASE_IDX 5 4459 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP 0x10c89 4460 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP_BASE_IDX 5 4461 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL 0x10c8a 4462 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL_BASE_IDX 5 4463 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP 0x10c8b 4464 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP_BASE_IDX 5 4465 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL 0x10c8c 4466 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL_BASE_IDX 5 4467 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10c90 4468 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 4469 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT 0x10c91 4470 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 4471 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA 0x10c92 4472 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 4473 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP 0x10c93 4474 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 4475 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST 0x10c94 4476 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 4477 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_CAP 0x10c95 4478 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_CAP_BASE_IDX 5 4479 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR 0x10c96 4480 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 4481 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS 0x10c97 4482 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS_BASE_IDX 5 4483 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL 0x10c97 4484 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL_BASE_IDX 5 4485 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10c98 4486 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 4487 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10c98 4488 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 4489 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10c98 4490 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 4491 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10c98 4492 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 4493 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10c99 4494 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 4495 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10c99 4496 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 4497 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10c99 4498 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 4499 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10c99 4500 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 4501 #define regBIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST 0x10ca8 4502 #define regBIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 4503 #define regBIF_CFG_DEV0_EPF3_PCIE_ACS_CAP 0x10ca9 4504 #define regBIF_CFG_DEV0_EPF3_PCIE_ACS_CAP_BASE_IDX 5 4505 #define regBIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL 0x10ca9 4506 #define regBIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL_BASE_IDX 5 4507 #define regBIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST 0x10cb4 4508 #define regBIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 4509 #define regBIF_CFG_DEV0_EPF3_PCIE_PASID_CAP 0x10cb5 4510 #define regBIF_CFG_DEV0_EPF3_PCIE_PASID_CAP_BASE_IDX 5 4511 #define regBIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL 0x10cb5 4512 #define regBIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL_BASE_IDX 5 4513 #define regBIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST 0x10cca 4514 #define regBIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 4515 #define regBIF_CFG_DEV0_EPF3_PCIE_ARI_CAP 0x10ccb 4516 #define regBIF_CFG_DEV0_EPF3_PCIE_ARI_CAP_BASE_IDX 5 4517 #define regBIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL 0x10ccb 4518 #define regBIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL_BASE_IDX 5 4519 4520 4521 // addressBlock: nbif_rcc_dev0_RCCPORTDEC 4522 // base address: 0x10131000 4523 #define regRCC_DEV0_1_RCC_VDM_SUPPORT 0xc440 4524 #define regRCC_DEV0_1_RCC_VDM_SUPPORT_BASE_IDX 5 4525 #define regRCC_DEV0_1_RCC_BUS_CNTL 0xc441 4526 #define regRCC_DEV0_1_RCC_BUS_CNTL_BASE_IDX 5 4527 #define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC 0xc442 4528 #define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_BASE_IDX 5 4529 #define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL 0xc443 4530 #define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL_BASE_IDX 5 4531 #define regRCC_DEV0_1_RCC_CMN_LINK_CNTL 0xc444 4532 #define regRCC_DEV0_1_RCC_CMN_LINK_CNTL_BASE_IDX 5 4533 #define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE 0xc445 4534 #define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 5 4535 #define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL 0xc446 4536 #define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_BASE_IDX 5 4537 #define regRCC_DEV0_1_RCC_MH_ARB_CNTL 0xc447 4538 #define regRCC_DEV0_1_RCC_MH_ARB_CNTL_BASE_IDX 5 4539 #define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 0xc448 4540 #define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 5 4541 #define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 0xc449 4542 #define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 5 4543 4544 4545 // addressBlock: nbif_rcc_ep_dev0_RCCPORTDEC 4546 // base address: 0x10131000 4547 #define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH 0xc44c 4548 #define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH_BASE_IDX 5 4549 #define regRCC_EP_DEV0_1_EP_PCIE_CNTL 0xc44e 4550 #define regRCC_EP_DEV0_1_EP_PCIE_CNTL_BASE_IDX 5 4551 #define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL 0xc44f 4552 #define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_BASE_IDX 5 4553 #define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS 0xc450 4554 #define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_BASE_IDX 5 4555 #define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 0xc451 4556 #define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_BASE_IDX 5 4557 #define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL 0xc452 4558 #define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_BASE_IDX 5 4559 #define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL 0xc453 4560 #define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_BASE_IDX 5 4561 #define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL 0xc454 4562 #define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_BASE_IDX 5 4563 #define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC 0xc455 4564 #define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_BASE_IDX 5 4565 #define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 0xc456 4566 #define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_BASE_IDX 5 4567 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP 0xc457 4568 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_BASE_IDX 5 4569 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0xc458 4570 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 5 4571 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL 0xc458 4572 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_BASE_IDX 5 4573 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0xc458 4574 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 4575 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0xc459 4576 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 4577 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0xc459 4578 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 4579 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0xc459 4580 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 4581 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0xc459 4582 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 4583 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0xc45a 4584 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 4585 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0xc45a 4586 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 4587 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0xc45a 4588 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 4589 #define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL 0xc45c 4590 #define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_BASE_IDX 5 4591 #define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED 0xc45d 4592 #define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED_BASE_IDX 5 4593 #define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL 0xc45f 4594 #define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_BASE_IDX 5 4595 #define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID 0xc460 4596 #define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 5 4597 #define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL 0xc461 4598 #define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_BASE_IDX 5 4599 #define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL 0xc462 4600 #define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_BASE_IDX 5 4601 #define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL 0xc463 4602 #define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 5 4603 4604 4605 // addressBlock: nbif_rcc_dwn_dev0_RCCPORTDEC 4606 // base address: 0x10131000 4607 #define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED 0xc468 4608 #define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED_BASE_IDX 5 4609 #define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH 0xc469 4610 #define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_BASE_IDX 5 4611 #define regRCC_DWN_DEV0_1_DN_PCIE_CNTL 0xc46b 4612 #define regRCC_DWN_DEV0_1_DN_PCIE_CNTL_BASE_IDX 5 4613 #define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL 0xc46c 4614 #define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_BASE_IDX 5 4615 #define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 0xc46d 4616 #define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_BASE_IDX 5 4617 #define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL 0xc46e 4618 #define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_BASE_IDX 5 4619 #define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL 0xc46f 4620 #define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_BASE_IDX 5 4621 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 0xc470 4622 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_BASE_IDX 5 4623 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC 0xc471 4624 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_BASE_IDX 5 4625 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 0xc472 4626 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_BASE_IDX 5 4627 4628 4629 // addressBlock: nbif_rcc_dwnp_dev0_RCCPORTDEC 4630 // base address: 0x10131000 4631 #define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL 0xc475 4632 #define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_BASE_IDX 5 4633 #define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL 0xc476 4634 #define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL_BASE_IDX 5 4635 #define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL 0xc477 4636 #define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_BASE_IDX 5 4637 #define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2 0xc478 4638 #define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_BASE_IDX 5 4639 #define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC 0xc479 4640 #define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_BASE_IDX 5 4641 #define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP 0xc47a 4642 #define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_BASE_IDX 5 4643 4644 4645 // addressBlock: nbif_rcc_pfc_amdgfx_RCCPFCDEC 4646 // base address: 0x10134000 4647 #define regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL 0xd040 4648 #define regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL_BASE_IDX 5 4649 #define regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE 0xd041 4650 #define regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE_BASE_IDX 5 4651 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0 0xd042 4652 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0_BASE_IDX 5 4653 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1 0xd043 4654 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1_BASE_IDX 5 4655 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2 0xd044 4656 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2_BASE_IDX 5 4657 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3 0xd045 4658 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3_BASE_IDX 5 4659 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4 0xd046 4660 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4_BASE_IDX 5 4661 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5 0xd047 4662 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5_BASE_IDX 5 4663 #define regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL 0xd048 4664 #define regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL_BASE_IDX 5 4665 4666 4667 // addressBlock: nbif_rcc_pfc_amdgfxaz_RCCPFCDEC 4668 // base address: 0x10134200 4669 #define regRCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL 0xd0c0 4670 #define regRCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL_BASE_IDX 5 4671 #define regRCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE 0xd0c1 4672 #define regRCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE_BASE_IDX 5 4673 #define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0 0xd0c2 4674 #define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0_BASE_IDX 5 4675 #define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1 0xd0c3 4676 #define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1_BASE_IDX 5 4677 #define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2 0xd0c4 4678 #define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2_BASE_IDX 5 4679 #define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3 0xd0c5 4680 #define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3_BASE_IDX 5 4681 #define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4 0xd0c6 4682 #define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4_BASE_IDX 5 4683 #define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5 0xd0c7 4684 #define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5_BASE_IDX 5 4685 #define regRCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL 0xd0c8 4686 #define regRCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL_BASE_IDX 5 4687 4688 4689 // addressBlock: nbif_pciemsix_0_usb_MSIXTDEC 4690 // base address: 0x10178000 4691 #define regPCIEMSIX_VECT0_ADDR_LO 0x1e000 4692 #define regPCIEMSIX_VECT0_ADDR_LO_BASE_IDX 5 4693 #define regPCIEMSIX_VECT0_ADDR_HI 0x1e001 4694 #define regPCIEMSIX_VECT0_ADDR_HI_BASE_IDX 5 4695 #define regPCIEMSIX_VECT0_MSG_DATA 0x1e002 4696 #define regPCIEMSIX_VECT0_MSG_DATA_BASE_IDX 5 4697 #define regPCIEMSIX_VECT0_CONTROL 0x1e003 4698 #define regPCIEMSIX_VECT0_CONTROL_BASE_IDX 5 4699 #define regPCIEMSIX_VECT1_ADDR_LO 0x1e004 4700 #define regPCIEMSIX_VECT1_ADDR_LO_BASE_IDX 5 4701 #define regPCIEMSIX_VECT1_ADDR_HI 0x1e005 4702 #define regPCIEMSIX_VECT1_ADDR_HI_BASE_IDX 5 4703 #define regPCIEMSIX_VECT1_MSG_DATA 0x1e006 4704 #define regPCIEMSIX_VECT1_MSG_DATA_BASE_IDX 5 4705 #define regPCIEMSIX_VECT1_CONTROL 0x1e007 4706 #define regPCIEMSIX_VECT1_CONTROL_BASE_IDX 5 4707 #define regPCIEMSIX_VECT2_ADDR_LO 0x1e008 4708 #define regPCIEMSIX_VECT2_ADDR_LO_BASE_IDX 5 4709 #define regPCIEMSIX_VECT2_ADDR_HI 0x1e009 4710 #define regPCIEMSIX_VECT2_ADDR_HI_BASE_IDX 5 4711 #define regPCIEMSIX_VECT2_MSG_DATA 0x1e00a 4712 #define regPCIEMSIX_VECT2_MSG_DATA_BASE_IDX 5 4713 #define regPCIEMSIX_VECT2_CONTROL 0x1e00b 4714 #define regPCIEMSIX_VECT2_CONTROL_BASE_IDX 5 4715 #define regPCIEMSIX_VECT3_ADDR_LO 0x1e00c 4716 #define regPCIEMSIX_VECT3_ADDR_LO_BASE_IDX 5 4717 #define regPCIEMSIX_VECT3_ADDR_HI 0x1e00d 4718 #define regPCIEMSIX_VECT3_ADDR_HI_BASE_IDX 5 4719 #define regPCIEMSIX_VECT3_MSG_DATA 0x1e00e 4720 #define regPCIEMSIX_VECT3_MSG_DATA_BASE_IDX 5 4721 #define regPCIEMSIX_VECT3_CONTROL 0x1e00f 4722 #define regPCIEMSIX_VECT3_CONTROL_BASE_IDX 5 4723 #define regPCIEMSIX_VECT4_ADDR_LO 0x1e010 4724 #define regPCIEMSIX_VECT4_ADDR_LO_BASE_IDX 5 4725 #define regPCIEMSIX_VECT4_ADDR_HI 0x1e011 4726 #define regPCIEMSIX_VECT4_ADDR_HI_BASE_IDX 5 4727 #define regPCIEMSIX_VECT4_MSG_DATA 0x1e012 4728 #define regPCIEMSIX_VECT4_MSG_DATA_BASE_IDX 5 4729 #define regPCIEMSIX_VECT4_CONTROL 0x1e013 4730 #define regPCIEMSIX_VECT4_CONTROL_BASE_IDX 5 4731 #define regPCIEMSIX_VECT5_ADDR_LO 0x1e014 4732 #define regPCIEMSIX_VECT5_ADDR_LO_BASE_IDX 5 4733 #define regPCIEMSIX_VECT5_ADDR_HI 0x1e015 4734 #define regPCIEMSIX_VECT5_ADDR_HI_BASE_IDX 5 4735 #define regPCIEMSIX_VECT5_MSG_DATA 0x1e016 4736 #define regPCIEMSIX_VECT5_MSG_DATA_BASE_IDX 5 4737 #define regPCIEMSIX_VECT5_CONTROL 0x1e017 4738 #define regPCIEMSIX_VECT5_CONTROL_BASE_IDX 5 4739 #define regPCIEMSIX_VECT6_ADDR_LO 0x1e018 4740 #define regPCIEMSIX_VECT6_ADDR_LO_BASE_IDX 5 4741 #define regPCIEMSIX_VECT6_ADDR_HI 0x1e019 4742 #define regPCIEMSIX_VECT6_ADDR_HI_BASE_IDX 5 4743 #define regPCIEMSIX_VECT6_MSG_DATA 0x1e01a 4744 #define regPCIEMSIX_VECT6_MSG_DATA_BASE_IDX 5 4745 #define regPCIEMSIX_VECT6_CONTROL 0x1e01b 4746 #define regPCIEMSIX_VECT6_CONTROL_BASE_IDX 5 4747 #define regPCIEMSIX_VECT7_ADDR_LO 0x1e01c 4748 #define regPCIEMSIX_VECT7_ADDR_LO_BASE_IDX 5 4749 #define regPCIEMSIX_VECT7_ADDR_HI 0x1e01d 4750 #define regPCIEMSIX_VECT7_ADDR_HI_BASE_IDX 5 4751 #define regPCIEMSIX_VECT7_MSG_DATA 0x1e01e 4752 #define regPCIEMSIX_VECT7_MSG_DATA_BASE_IDX 5 4753 #define regPCIEMSIX_VECT7_CONTROL 0x1e01f 4754 #define regPCIEMSIX_VECT7_CONTROL_BASE_IDX 5 4755 #define regPCIEMSIX_VECT8_ADDR_LO 0x1e020 4756 #define regPCIEMSIX_VECT8_ADDR_LO_BASE_IDX 5 4757 #define regPCIEMSIX_VECT8_ADDR_HI 0x1e021 4758 #define regPCIEMSIX_VECT8_ADDR_HI_BASE_IDX 5 4759 #define regPCIEMSIX_VECT8_MSG_DATA 0x1e022 4760 #define regPCIEMSIX_VECT8_MSG_DATA_BASE_IDX 5 4761 #define regPCIEMSIX_VECT8_CONTROL 0x1e023 4762 #define regPCIEMSIX_VECT8_CONTROL_BASE_IDX 5 4763 #define regPCIEMSIX_VECT9_ADDR_LO 0x1e024 4764 #define regPCIEMSIX_VECT9_ADDR_LO_BASE_IDX 5 4765 #define regPCIEMSIX_VECT9_ADDR_HI 0x1e025 4766 #define regPCIEMSIX_VECT9_ADDR_HI_BASE_IDX 5 4767 #define regPCIEMSIX_VECT9_MSG_DATA 0x1e026 4768 #define regPCIEMSIX_VECT9_MSG_DATA_BASE_IDX 5 4769 #define regPCIEMSIX_VECT9_CONTROL 0x1e027 4770 #define regPCIEMSIX_VECT9_CONTROL_BASE_IDX 5 4771 #define regPCIEMSIX_VECT10_ADDR_LO 0x1e028 4772 #define regPCIEMSIX_VECT10_ADDR_LO_BASE_IDX 5 4773 #define regPCIEMSIX_VECT10_ADDR_HI 0x1e029 4774 #define regPCIEMSIX_VECT10_ADDR_HI_BASE_IDX 5 4775 #define regPCIEMSIX_VECT10_MSG_DATA 0x1e02a 4776 #define regPCIEMSIX_VECT10_MSG_DATA_BASE_IDX 5 4777 #define regPCIEMSIX_VECT10_CONTROL 0x1e02b 4778 #define regPCIEMSIX_VECT10_CONTROL_BASE_IDX 5 4779 #define regPCIEMSIX_VECT11_ADDR_LO 0x1e02c 4780 #define regPCIEMSIX_VECT11_ADDR_LO_BASE_IDX 5 4781 #define regPCIEMSIX_VECT11_ADDR_HI 0x1e02d 4782 #define regPCIEMSIX_VECT11_ADDR_HI_BASE_IDX 5 4783 #define regPCIEMSIX_VECT11_MSG_DATA 0x1e02e 4784 #define regPCIEMSIX_VECT11_MSG_DATA_BASE_IDX 5 4785 #define regPCIEMSIX_VECT11_CONTROL 0x1e02f 4786 #define regPCIEMSIX_VECT11_CONTROL_BASE_IDX 5 4787 #define regPCIEMSIX_VECT12_ADDR_LO 0x1e030 4788 #define regPCIEMSIX_VECT12_ADDR_LO_BASE_IDX 5 4789 #define regPCIEMSIX_VECT12_ADDR_HI 0x1e031 4790 #define regPCIEMSIX_VECT12_ADDR_HI_BASE_IDX 5 4791 #define regPCIEMSIX_VECT12_MSG_DATA 0x1e032 4792 #define regPCIEMSIX_VECT12_MSG_DATA_BASE_IDX 5 4793 #define regPCIEMSIX_VECT12_CONTROL 0x1e033 4794 #define regPCIEMSIX_VECT12_CONTROL_BASE_IDX 5 4795 #define regPCIEMSIX_VECT13_ADDR_LO 0x1e034 4796 #define regPCIEMSIX_VECT13_ADDR_LO_BASE_IDX 5 4797 #define regPCIEMSIX_VECT13_ADDR_HI 0x1e035 4798 #define regPCIEMSIX_VECT13_ADDR_HI_BASE_IDX 5 4799 #define regPCIEMSIX_VECT13_MSG_DATA 0x1e036 4800 #define regPCIEMSIX_VECT13_MSG_DATA_BASE_IDX 5 4801 #define regPCIEMSIX_VECT13_CONTROL 0x1e037 4802 #define regPCIEMSIX_VECT13_CONTROL_BASE_IDX 5 4803 #define regPCIEMSIX_VECT14_ADDR_LO 0x1e038 4804 #define regPCIEMSIX_VECT14_ADDR_LO_BASE_IDX 5 4805 #define regPCIEMSIX_VECT14_ADDR_HI 0x1e039 4806 #define regPCIEMSIX_VECT14_ADDR_HI_BASE_IDX 5 4807 #define regPCIEMSIX_VECT14_MSG_DATA 0x1e03a 4808 #define regPCIEMSIX_VECT14_MSG_DATA_BASE_IDX 5 4809 #define regPCIEMSIX_VECT14_CONTROL 0x1e03b 4810 #define regPCIEMSIX_VECT14_CONTROL_BASE_IDX 5 4811 #define regPCIEMSIX_VECT15_ADDR_LO 0x1e03c 4812 #define regPCIEMSIX_VECT15_ADDR_LO_BASE_IDX 5 4813 #define regPCIEMSIX_VECT15_ADDR_HI 0x1e03d 4814 #define regPCIEMSIX_VECT15_ADDR_HI_BASE_IDX 5 4815 #define regPCIEMSIX_VECT15_MSG_DATA 0x1e03e 4816 #define regPCIEMSIX_VECT15_MSG_DATA_BASE_IDX 5 4817 #define regPCIEMSIX_VECT15_CONTROL 0x1e03f 4818 #define regPCIEMSIX_VECT15_CONTROL_BASE_IDX 5 4819 #define regPCIEMSIX_VECT16_ADDR_LO 0x1e040 4820 #define regPCIEMSIX_VECT16_ADDR_LO_BASE_IDX 5 4821 #define regPCIEMSIX_VECT16_ADDR_HI 0x1e041 4822 #define regPCIEMSIX_VECT16_ADDR_HI_BASE_IDX 5 4823 #define regPCIEMSIX_VECT16_MSG_DATA 0x1e042 4824 #define regPCIEMSIX_VECT16_MSG_DATA_BASE_IDX 5 4825 #define regPCIEMSIX_VECT16_CONTROL 0x1e043 4826 #define regPCIEMSIX_VECT16_CONTROL_BASE_IDX 5 4827 #define regPCIEMSIX_VECT17_ADDR_LO 0x1e044 4828 #define regPCIEMSIX_VECT17_ADDR_LO_BASE_IDX 5 4829 #define regPCIEMSIX_VECT17_ADDR_HI 0x1e045 4830 #define regPCIEMSIX_VECT17_ADDR_HI_BASE_IDX 5 4831 #define regPCIEMSIX_VECT17_MSG_DATA 0x1e046 4832 #define regPCIEMSIX_VECT17_MSG_DATA_BASE_IDX 5 4833 #define regPCIEMSIX_VECT17_CONTROL 0x1e047 4834 #define regPCIEMSIX_VECT17_CONTROL_BASE_IDX 5 4835 #define regPCIEMSIX_VECT18_ADDR_LO 0x1e048 4836 #define regPCIEMSIX_VECT18_ADDR_LO_BASE_IDX 5 4837 #define regPCIEMSIX_VECT18_ADDR_HI 0x1e049 4838 #define regPCIEMSIX_VECT18_ADDR_HI_BASE_IDX 5 4839 #define regPCIEMSIX_VECT18_MSG_DATA 0x1e04a 4840 #define regPCIEMSIX_VECT18_MSG_DATA_BASE_IDX 5 4841 #define regPCIEMSIX_VECT18_CONTROL 0x1e04b 4842 #define regPCIEMSIX_VECT18_CONTROL_BASE_IDX 5 4843 #define regPCIEMSIX_VECT19_ADDR_LO 0x1e04c 4844 #define regPCIEMSIX_VECT19_ADDR_LO_BASE_IDX 5 4845 #define regPCIEMSIX_VECT19_ADDR_HI 0x1e04d 4846 #define regPCIEMSIX_VECT19_ADDR_HI_BASE_IDX 5 4847 #define regPCIEMSIX_VECT19_MSG_DATA 0x1e04e 4848 #define regPCIEMSIX_VECT19_MSG_DATA_BASE_IDX 5 4849 #define regPCIEMSIX_VECT19_CONTROL 0x1e04f 4850 #define regPCIEMSIX_VECT19_CONTROL_BASE_IDX 5 4851 #define regPCIEMSIX_VECT20_ADDR_LO 0x1e050 4852 #define regPCIEMSIX_VECT20_ADDR_LO_BASE_IDX 5 4853 #define regPCIEMSIX_VECT20_ADDR_HI 0x1e051 4854 #define regPCIEMSIX_VECT20_ADDR_HI_BASE_IDX 5 4855 #define regPCIEMSIX_VECT20_MSG_DATA 0x1e052 4856 #define regPCIEMSIX_VECT20_MSG_DATA_BASE_IDX 5 4857 #define regPCIEMSIX_VECT20_CONTROL 0x1e053 4858 #define regPCIEMSIX_VECT20_CONTROL_BASE_IDX 5 4859 #define regPCIEMSIX_VECT21_ADDR_LO 0x1e054 4860 #define regPCIEMSIX_VECT21_ADDR_LO_BASE_IDX 5 4861 #define regPCIEMSIX_VECT21_ADDR_HI 0x1e055 4862 #define regPCIEMSIX_VECT21_ADDR_HI_BASE_IDX 5 4863 #define regPCIEMSIX_VECT21_MSG_DATA 0x1e056 4864 #define regPCIEMSIX_VECT21_MSG_DATA_BASE_IDX 5 4865 #define regPCIEMSIX_VECT21_CONTROL 0x1e057 4866 #define regPCIEMSIX_VECT21_CONTROL_BASE_IDX 5 4867 #define regPCIEMSIX_VECT22_ADDR_LO 0x1e058 4868 #define regPCIEMSIX_VECT22_ADDR_LO_BASE_IDX 5 4869 #define regPCIEMSIX_VECT22_ADDR_HI 0x1e059 4870 #define regPCIEMSIX_VECT22_ADDR_HI_BASE_IDX 5 4871 #define regPCIEMSIX_VECT22_MSG_DATA 0x1e05a 4872 #define regPCIEMSIX_VECT22_MSG_DATA_BASE_IDX 5 4873 #define regPCIEMSIX_VECT22_CONTROL 0x1e05b 4874 #define regPCIEMSIX_VECT22_CONTROL_BASE_IDX 5 4875 #define regPCIEMSIX_VECT23_ADDR_LO 0x1e05c 4876 #define regPCIEMSIX_VECT23_ADDR_LO_BASE_IDX 5 4877 #define regPCIEMSIX_VECT23_ADDR_HI 0x1e05d 4878 #define regPCIEMSIX_VECT23_ADDR_HI_BASE_IDX 5 4879 #define regPCIEMSIX_VECT23_MSG_DATA 0x1e05e 4880 #define regPCIEMSIX_VECT23_MSG_DATA_BASE_IDX 5 4881 #define regPCIEMSIX_VECT23_CONTROL 0x1e05f 4882 #define regPCIEMSIX_VECT23_CONTROL_BASE_IDX 5 4883 #define regPCIEMSIX_VECT24_ADDR_LO 0x1e060 4884 #define regPCIEMSIX_VECT24_ADDR_LO_BASE_IDX 5 4885 #define regPCIEMSIX_VECT24_ADDR_HI 0x1e061 4886 #define regPCIEMSIX_VECT24_ADDR_HI_BASE_IDX 5 4887 #define regPCIEMSIX_VECT24_MSG_DATA 0x1e062 4888 #define regPCIEMSIX_VECT24_MSG_DATA_BASE_IDX 5 4889 #define regPCIEMSIX_VECT24_CONTROL 0x1e063 4890 #define regPCIEMSIX_VECT24_CONTROL_BASE_IDX 5 4891 #define regPCIEMSIX_VECT25_ADDR_LO 0x1e064 4892 #define regPCIEMSIX_VECT25_ADDR_LO_BASE_IDX 5 4893 #define regPCIEMSIX_VECT25_ADDR_HI 0x1e065 4894 #define regPCIEMSIX_VECT25_ADDR_HI_BASE_IDX 5 4895 #define regPCIEMSIX_VECT25_MSG_DATA 0x1e066 4896 #define regPCIEMSIX_VECT25_MSG_DATA_BASE_IDX 5 4897 #define regPCIEMSIX_VECT25_CONTROL 0x1e067 4898 #define regPCIEMSIX_VECT25_CONTROL_BASE_IDX 5 4899 #define regPCIEMSIX_VECT26_ADDR_LO 0x1e068 4900 #define regPCIEMSIX_VECT26_ADDR_LO_BASE_IDX 5 4901 #define regPCIEMSIX_VECT26_ADDR_HI 0x1e069 4902 #define regPCIEMSIX_VECT26_ADDR_HI_BASE_IDX 5 4903 #define regPCIEMSIX_VECT26_MSG_DATA 0x1e06a 4904 #define regPCIEMSIX_VECT26_MSG_DATA_BASE_IDX 5 4905 #define regPCIEMSIX_VECT26_CONTROL 0x1e06b 4906 #define regPCIEMSIX_VECT26_CONTROL_BASE_IDX 5 4907 #define regPCIEMSIX_VECT27_ADDR_LO 0x1e06c 4908 #define regPCIEMSIX_VECT27_ADDR_LO_BASE_IDX 5 4909 #define regPCIEMSIX_VECT27_ADDR_HI 0x1e06d 4910 #define regPCIEMSIX_VECT27_ADDR_HI_BASE_IDX 5 4911 #define regPCIEMSIX_VECT27_MSG_DATA 0x1e06e 4912 #define regPCIEMSIX_VECT27_MSG_DATA_BASE_IDX 5 4913 #define regPCIEMSIX_VECT27_CONTROL 0x1e06f 4914 #define regPCIEMSIX_VECT27_CONTROL_BASE_IDX 5 4915 #define regPCIEMSIX_VECT28_ADDR_LO 0x1e070 4916 #define regPCIEMSIX_VECT28_ADDR_LO_BASE_IDX 5 4917 #define regPCIEMSIX_VECT28_ADDR_HI 0x1e071 4918 #define regPCIEMSIX_VECT28_ADDR_HI_BASE_IDX 5 4919 #define regPCIEMSIX_VECT28_MSG_DATA 0x1e072 4920 #define regPCIEMSIX_VECT28_MSG_DATA_BASE_IDX 5 4921 #define regPCIEMSIX_VECT28_CONTROL 0x1e073 4922 #define regPCIEMSIX_VECT28_CONTROL_BASE_IDX 5 4923 #define regPCIEMSIX_VECT29_ADDR_LO 0x1e074 4924 #define regPCIEMSIX_VECT29_ADDR_LO_BASE_IDX 5 4925 #define regPCIEMSIX_VECT29_ADDR_HI 0x1e075 4926 #define regPCIEMSIX_VECT29_ADDR_HI_BASE_IDX 5 4927 #define regPCIEMSIX_VECT29_MSG_DATA 0x1e076 4928 #define regPCIEMSIX_VECT29_MSG_DATA_BASE_IDX 5 4929 #define regPCIEMSIX_VECT29_CONTROL 0x1e077 4930 #define regPCIEMSIX_VECT29_CONTROL_BASE_IDX 5 4931 #define regPCIEMSIX_VECT30_ADDR_LO 0x1e078 4932 #define regPCIEMSIX_VECT30_ADDR_LO_BASE_IDX 5 4933 #define regPCIEMSIX_VECT30_ADDR_HI 0x1e079 4934 #define regPCIEMSIX_VECT30_ADDR_HI_BASE_IDX 5 4935 #define regPCIEMSIX_VECT30_MSG_DATA 0x1e07a 4936 #define regPCIEMSIX_VECT30_MSG_DATA_BASE_IDX 5 4937 #define regPCIEMSIX_VECT30_CONTROL 0x1e07b 4938 #define regPCIEMSIX_VECT30_CONTROL_BASE_IDX 5 4939 #define regPCIEMSIX_VECT31_ADDR_LO 0x1e07c 4940 #define regPCIEMSIX_VECT31_ADDR_LO_BASE_IDX 5 4941 #define regPCIEMSIX_VECT31_ADDR_HI 0x1e07d 4942 #define regPCIEMSIX_VECT31_ADDR_HI_BASE_IDX 5 4943 #define regPCIEMSIX_VECT31_MSG_DATA 0x1e07e 4944 #define regPCIEMSIX_VECT31_MSG_DATA_BASE_IDX 5 4945 #define regPCIEMSIX_VECT31_CONTROL 0x1e07f 4946 #define regPCIEMSIX_VECT31_CONTROL_BASE_IDX 5 4947 #define regPCIEMSIX_VECT32_ADDR_LO 0x1e080 4948 #define regPCIEMSIX_VECT32_ADDR_LO_BASE_IDX 5 4949 #define regPCIEMSIX_VECT32_ADDR_HI 0x1e081 4950 #define regPCIEMSIX_VECT32_ADDR_HI_BASE_IDX 5 4951 #define regPCIEMSIX_VECT32_MSG_DATA 0x1e082 4952 #define regPCIEMSIX_VECT32_MSG_DATA_BASE_IDX 5 4953 #define regPCIEMSIX_VECT32_CONTROL 0x1e083 4954 #define regPCIEMSIX_VECT32_CONTROL_BASE_IDX 5 4955 #define regPCIEMSIX_VECT33_ADDR_LO 0x1e084 4956 #define regPCIEMSIX_VECT33_ADDR_LO_BASE_IDX 5 4957 #define regPCIEMSIX_VECT33_ADDR_HI 0x1e085 4958 #define regPCIEMSIX_VECT33_ADDR_HI_BASE_IDX 5 4959 #define regPCIEMSIX_VECT33_MSG_DATA 0x1e086 4960 #define regPCIEMSIX_VECT33_MSG_DATA_BASE_IDX 5 4961 #define regPCIEMSIX_VECT33_CONTROL 0x1e087 4962 #define regPCIEMSIX_VECT33_CONTROL_BASE_IDX 5 4963 #define regPCIEMSIX_VECT34_ADDR_LO 0x1e088 4964 #define regPCIEMSIX_VECT34_ADDR_LO_BASE_IDX 5 4965 #define regPCIEMSIX_VECT34_ADDR_HI 0x1e089 4966 #define regPCIEMSIX_VECT34_ADDR_HI_BASE_IDX 5 4967 #define regPCIEMSIX_VECT34_MSG_DATA 0x1e08a 4968 #define regPCIEMSIX_VECT34_MSG_DATA_BASE_IDX 5 4969 #define regPCIEMSIX_VECT34_CONTROL 0x1e08b 4970 #define regPCIEMSIX_VECT34_CONTROL_BASE_IDX 5 4971 #define regPCIEMSIX_VECT35_ADDR_LO 0x1e08c 4972 #define regPCIEMSIX_VECT35_ADDR_LO_BASE_IDX 5 4973 #define regPCIEMSIX_VECT35_ADDR_HI 0x1e08d 4974 #define regPCIEMSIX_VECT35_ADDR_HI_BASE_IDX 5 4975 #define regPCIEMSIX_VECT35_MSG_DATA 0x1e08e 4976 #define regPCIEMSIX_VECT35_MSG_DATA_BASE_IDX 5 4977 #define regPCIEMSIX_VECT35_CONTROL 0x1e08f 4978 #define regPCIEMSIX_VECT35_CONTROL_BASE_IDX 5 4979 #define regPCIEMSIX_VECT36_ADDR_LO 0x1e090 4980 #define regPCIEMSIX_VECT36_ADDR_LO_BASE_IDX 5 4981 #define regPCIEMSIX_VECT36_ADDR_HI 0x1e091 4982 #define regPCIEMSIX_VECT36_ADDR_HI_BASE_IDX 5 4983 #define regPCIEMSIX_VECT36_MSG_DATA 0x1e092 4984 #define regPCIEMSIX_VECT36_MSG_DATA_BASE_IDX 5 4985 #define regPCIEMSIX_VECT36_CONTROL 0x1e093 4986 #define regPCIEMSIX_VECT36_CONTROL_BASE_IDX 5 4987 #define regPCIEMSIX_VECT37_ADDR_LO 0x1e094 4988 #define regPCIEMSIX_VECT37_ADDR_LO_BASE_IDX 5 4989 #define regPCIEMSIX_VECT37_ADDR_HI 0x1e095 4990 #define regPCIEMSIX_VECT37_ADDR_HI_BASE_IDX 5 4991 #define regPCIEMSIX_VECT37_MSG_DATA 0x1e096 4992 #define regPCIEMSIX_VECT37_MSG_DATA_BASE_IDX 5 4993 #define regPCIEMSIX_VECT37_CONTROL 0x1e097 4994 #define regPCIEMSIX_VECT37_CONTROL_BASE_IDX 5 4995 #define regPCIEMSIX_VECT38_ADDR_LO 0x1e098 4996 #define regPCIEMSIX_VECT38_ADDR_LO_BASE_IDX 5 4997 #define regPCIEMSIX_VECT38_ADDR_HI 0x1e099 4998 #define regPCIEMSIX_VECT38_ADDR_HI_BASE_IDX 5 4999 #define regPCIEMSIX_VECT38_MSG_DATA 0x1e09a 5000 #define regPCIEMSIX_VECT38_MSG_DATA_BASE_IDX 5 5001 #define regPCIEMSIX_VECT38_CONTROL 0x1e09b 5002 #define regPCIEMSIX_VECT38_CONTROL_BASE_IDX 5 5003 #define regPCIEMSIX_VECT39_ADDR_LO 0x1e09c 5004 #define regPCIEMSIX_VECT39_ADDR_LO_BASE_IDX 5 5005 #define regPCIEMSIX_VECT39_ADDR_HI 0x1e09d 5006 #define regPCIEMSIX_VECT39_ADDR_HI_BASE_IDX 5 5007 #define regPCIEMSIX_VECT39_MSG_DATA 0x1e09e 5008 #define regPCIEMSIX_VECT39_MSG_DATA_BASE_IDX 5 5009 #define regPCIEMSIX_VECT39_CONTROL 0x1e09f 5010 #define regPCIEMSIX_VECT39_CONTROL_BASE_IDX 5 5011 #define regPCIEMSIX_VECT40_ADDR_LO 0x1e0a0 5012 #define regPCIEMSIX_VECT40_ADDR_LO_BASE_IDX 5 5013 #define regPCIEMSIX_VECT40_ADDR_HI 0x1e0a1 5014 #define regPCIEMSIX_VECT40_ADDR_HI_BASE_IDX 5 5015 #define regPCIEMSIX_VECT40_MSG_DATA 0x1e0a2 5016 #define regPCIEMSIX_VECT40_MSG_DATA_BASE_IDX 5 5017 #define regPCIEMSIX_VECT40_CONTROL 0x1e0a3 5018 #define regPCIEMSIX_VECT40_CONTROL_BASE_IDX 5 5019 #define regPCIEMSIX_VECT41_ADDR_LO 0x1e0a4 5020 #define regPCIEMSIX_VECT41_ADDR_LO_BASE_IDX 5 5021 #define regPCIEMSIX_VECT41_ADDR_HI 0x1e0a5 5022 #define regPCIEMSIX_VECT41_ADDR_HI_BASE_IDX 5 5023 #define regPCIEMSIX_VECT41_MSG_DATA 0x1e0a6 5024 #define regPCIEMSIX_VECT41_MSG_DATA_BASE_IDX 5 5025 #define regPCIEMSIX_VECT41_CONTROL 0x1e0a7 5026 #define regPCIEMSIX_VECT41_CONTROL_BASE_IDX 5 5027 #define regPCIEMSIX_VECT42_ADDR_LO 0x1e0a8 5028 #define regPCIEMSIX_VECT42_ADDR_LO_BASE_IDX 5 5029 #define regPCIEMSIX_VECT42_ADDR_HI 0x1e0a9 5030 #define regPCIEMSIX_VECT42_ADDR_HI_BASE_IDX 5 5031 #define regPCIEMSIX_VECT42_MSG_DATA 0x1e0aa 5032 #define regPCIEMSIX_VECT42_MSG_DATA_BASE_IDX 5 5033 #define regPCIEMSIX_VECT42_CONTROL 0x1e0ab 5034 #define regPCIEMSIX_VECT42_CONTROL_BASE_IDX 5 5035 #define regPCIEMSIX_VECT43_ADDR_LO 0x1e0ac 5036 #define regPCIEMSIX_VECT43_ADDR_LO_BASE_IDX 5 5037 #define regPCIEMSIX_VECT43_ADDR_HI 0x1e0ad 5038 #define regPCIEMSIX_VECT43_ADDR_HI_BASE_IDX 5 5039 #define regPCIEMSIX_VECT43_MSG_DATA 0x1e0ae 5040 #define regPCIEMSIX_VECT43_MSG_DATA_BASE_IDX 5 5041 #define regPCIEMSIX_VECT43_CONTROL 0x1e0af 5042 #define regPCIEMSIX_VECT43_CONTROL_BASE_IDX 5 5043 #define regPCIEMSIX_VECT44_ADDR_LO 0x1e0b0 5044 #define regPCIEMSIX_VECT44_ADDR_LO_BASE_IDX 5 5045 #define regPCIEMSIX_VECT44_ADDR_HI 0x1e0b1 5046 #define regPCIEMSIX_VECT44_ADDR_HI_BASE_IDX 5 5047 #define regPCIEMSIX_VECT44_MSG_DATA 0x1e0b2 5048 #define regPCIEMSIX_VECT44_MSG_DATA_BASE_IDX 5 5049 #define regPCIEMSIX_VECT44_CONTROL 0x1e0b3 5050 #define regPCIEMSIX_VECT44_CONTROL_BASE_IDX 5 5051 #define regPCIEMSIX_VECT45_ADDR_LO 0x1e0b4 5052 #define regPCIEMSIX_VECT45_ADDR_LO_BASE_IDX 5 5053 #define regPCIEMSIX_VECT45_ADDR_HI 0x1e0b5 5054 #define regPCIEMSIX_VECT45_ADDR_HI_BASE_IDX 5 5055 #define regPCIEMSIX_VECT45_MSG_DATA 0x1e0b6 5056 #define regPCIEMSIX_VECT45_MSG_DATA_BASE_IDX 5 5057 #define regPCIEMSIX_VECT45_CONTROL 0x1e0b7 5058 #define regPCIEMSIX_VECT45_CONTROL_BASE_IDX 5 5059 #define regPCIEMSIX_VECT46_ADDR_LO 0x1e0b8 5060 #define regPCIEMSIX_VECT46_ADDR_LO_BASE_IDX 5 5061 #define regPCIEMSIX_VECT46_ADDR_HI 0x1e0b9 5062 #define regPCIEMSIX_VECT46_ADDR_HI_BASE_IDX 5 5063 #define regPCIEMSIX_VECT46_MSG_DATA 0x1e0ba 5064 #define regPCIEMSIX_VECT46_MSG_DATA_BASE_IDX 5 5065 #define regPCIEMSIX_VECT46_CONTROL 0x1e0bb 5066 #define regPCIEMSIX_VECT46_CONTROL_BASE_IDX 5 5067 #define regPCIEMSIX_VECT47_ADDR_LO 0x1e0bc 5068 #define regPCIEMSIX_VECT47_ADDR_LO_BASE_IDX 5 5069 #define regPCIEMSIX_VECT47_ADDR_HI 0x1e0bd 5070 #define regPCIEMSIX_VECT47_ADDR_HI_BASE_IDX 5 5071 #define regPCIEMSIX_VECT47_MSG_DATA 0x1e0be 5072 #define regPCIEMSIX_VECT47_MSG_DATA_BASE_IDX 5 5073 #define regPCIEMSIX_VECT47_CONTROL 0x1e0bf 5074 #define regPCIEMSIX_VECT47_CONTROL_BASE_IDX 5 5075 #define regPCIEMSIX_VECT48_ADDR_LO 0x1e0c0 5076 #define regPCIEMSIX_VECT48_ADDR_LO_BASE_IDX 5 5077 #define regPCIEMSIX_VECT48_ADDR_HI 0x1e0c1 5078 #define regPCIEMSIX_VECT48_ADDR_HI_BASE_IDX 5 5079 #define regPCIEMSIX_VECT48_MSG_DATA 0x1e0c2 5080 #define regPCIEMSIX_VECT48_MSG_DATA_BASE_IDX 5 5081 #define regPCIEMSIX_VECT48_CONTROL 0x1e0c3 5082 #define regPCIEMSIX_VECT48_CONTROL_BASE_IDX 5 5083 #define regPCIEMSIX_VECT49_ADDR_LO 0x1e0c4 5084 #define regPCIEMSIX_VECT49_ADDR_LO_BASE_IDX 5 5085 #define regPCIEMSIX_VECT49_ADDR_HI 0x1e0c5 5086 #define regPCIEMSIX_VECT49_ADDR_HI_BASE_IDX 5 5087 #define regPCIEMSIX_VECT49_MSG_DATA 0x1e0c6 5088 #define regPCIEMSIX_VECT49_MSG_DATA_BASE_IDX 5 5089 #define regPCIEMSIX_VECT49_CONTROL 0x1e0c7 5090 #define regPCIEMSIX_VECT49_CONTROL_BASE_IDX 5 5091 #define regPCIEMSIX_VECT50_ADDR_LO 0x1e0c8 5092 #define regPCIEMSIX_VECT50_ADDR_LO_BASE_IDX 5 5093 #define regPCIEMSIX_VECT50_ADDR_HI 0x1e0c9 5094 #define regPCIEMSIX_VECT50_ADDR_HI_BASE_IDX 5 5095 #define regPCIEMSIX_VECT50_MSG_DATA 0x1e0ca 5096 #define regPCIEMSIX_VECT50_MSG_DATA_BASE_IDX 5 5097 #define regPCIEMSIX_VECT50_CONTROL 0x1e0cb 5098 #define regPCIEMSIX_VECT50_CONTROL_BASE_IDX 5 5099 #define regPCIEMSIX_VECT51_ADDR_LO 0x1e0cc 5100 #define regPCIEMSIX_VECT51_ADDR_LO_BASE_IDX 5 5101 #define regPCIEMSIX_VECT51_ADDR_HI 0x1e0cd 5102 #define regPCIEMSIX_VECT51_ADDR_HI_BASE_IDX 5 5103 #define regPCIEMSIX_VECT51_MSG_DATA 0x1e0ce 5104 #define regPCIEMSIX_VECT51_MSG_DATA_BASE_IDX 5 5105 #define regPCIEMSIX_VECT51_CONTROL 0x1e0cf 5106 #define regPCIEMSIX_VECT51_CONTROL_BASE_IDX 5 5107 #define regPCIEMSIX_VECT52_ADDR_LO 0x1e0d0 5108 #define regPCIEMSIX_VECT52_ADDR_LO_BASE_IDX 5 5109 #define regPCIEMSIX_VECT52_ADDR_HI 0x1e0d1 5110 #define regPCIEMSIX_VECT52_ADDR_HI_BASE_IDX 5 5111 #define regPCIEMSIX_VECT52_MSG_DATA 0x1e0d2 5112 #define regPCIEMSIX_VECT52_MSG_DATA_BASE_IDX 5 5113 #define regPCIEMSIX_VECT52_CONTROL 0x1e0d3 5114 #define regPCIEMSIX_VECT52_CONTROL_BASE_IDX 5 5115 #define regPCIEMSIX_VECT53_ADDR_LO 0x1e0d4 5116 #define regPCIEMSIX_VECT53_ADDR_LO_BASE_IDX 5 5117 #define regPCIEMSIX_VECT53_ADDR_HI 0x1e0d5 5118 #define regPCIEMSIX_VECT53_ADDR_HI_BASE_IDX 5 5119 #define regPCIEMSIX_VECT53_MSG_DATA 0x1e0d6 5120 #define regPCIEMSIX_VECT53_MSG_DATA_BASE_IDX 5 5121 #define regPCIEMSIX_VECT53_CONTROL 0x1e0d7 5122 #define regPCIEMSIX_VECT53_CONTROL_BASE_IDX 5 5123 #define regPCIEMSIX_VECT54_ADDR_LO 0x1e0d8 5124 #define regPCIEMSIX_VECT54_ADDR_LO_BASE_IDX 5 5125 #define regPCIEMSIX_VECT54_ADDR_HI 0x1e0d9 5126 #define regPCIEMSIX_VECT54_ADDR_HI_BASE_IDX 5 5127 #define regPCIEMSIX_VECT54_MSG_DATA 0x1e0da 5128 #define regPCIEMSIX_VECT54_MSG_DATA_BASE_IDX 5 5129 #define regPCIEMSIX_VECT54_CONTROL 0x1e0db 5130 #define regPCIEMSIX_VECT54_CONTROL_BASE_IDX 5 5131 #define regPCIEMSIX_VECT55_ADDR_LO 0x1e0dc 5132 #define regPCIEMSIX_VECT55_ADDR_LO_BASE_IDX 5 5133 #define regPCIEMSIX_VECT55_ADDR_HI 0x1e0dd 5134 #define regPCIEMSIX_VECT55_ADDR_HI_BASE_IDX 5 5135 #define regPCIEMSIX_VECT55_MSG_DATA 0x1e0de 5136 #define regPCIEMSIX_VECT55_MSG_DATA_BASE_IDX 5 5137 #define regPCIEMSIX_VECT55_CONTROL 0x1e0df 5138 #define regPCIEMSIX_VECT55_CONTROL_BASE_IDX 5 5139 #define regPCIEMSIX_VECT56_ADDR_LO 0x1e0e0 5140 #define regPCIEMSIX_VECT56_ADDR_LO_BASE_IDX 5 5141 #define regPCIEMSIX_VECT56_ADDR_HI 0x1e0e1 5142 #define regPCIEMSIX_VECT56_ADDR_HI_BASE_IDX 5 5143 #define regPCIEMSIX_VECT56_MSG_DATA 0x1e0e2 5144 #define regPCIEMSIX_VECT56_MSG_DATA_BASE_IDX 5 5145 #define regPCIEMSIX_VECT56_CONTROL 0x1e0e3 5146 #define regPCIEMSIX_VECT56_CONTROL_BASE_IDX 5 5147 #define regPCIEMSIX_VECT57_ADDR_LO 0x1e0e4 5148 #define regPCIEMSIX_VECT57_ADDR_LO_BASE_IDX 5 5149 #define regPCIEMSIX_VECT57_ADDR_HI 0x1e0e5 5150 #define regPCIEMSIX_VECT57_ADDR_HI_BASE_IDX 5 5151 #define regPCIEMSIX_VECT57_MSG_DATA 0x1e0e6 5152 #define regPCIEMSIX_VECT57_MSG_DATA_BASE_IDX 5 5153 #define regPCIEMSIX_VECT57_CONTROL 0x1e0e7 5154 #define regPCIEMSIX_VECT57_CONTROL_BASE_IDX 5 5155 #define regPCIEMSIX_VECT58_ADDR_LO 0x1e0e8 5156 #define regPCIEMSIX_VECT58_ADDR_LO_BASE_IDX 5 5157 #define regPCIEMSIX_VECT58_ADDR_HI 0x1e0e9 5158 #define regPCIEMSIX_VECT58_ADDR_HI_BASE_IDX 5 5159 #define regPCIEMSIX_VECT58_MSG_DATA 0x1e0ea 5160 #define regPCIEMSIX_VECT58_MSG_DATA_BASE_IDX 5 5161 #define regPCIEMSIX_VECT58_CONTROL 0x1e0eb 5162 #define regPCIEMSIX_VECT58_CONTROL_BASE_IDX 5 5163 #define regPCIEMSIX_VECT59_ADDR_LO 0x1e0ec 5164 #define regPCIEMSIX_VECT59_ADDR_LO_BASE_IDX 5 5165 #define regPCIEMSIX_VECT59_ADDR_HI 0x1e0ed 5166 #define regPCIEMSIX_VECT59_ADDR_HI_BASE_IDX 5 5167 #define regPCIEMSIX_VECT59_MSG_DATA 0x1e0ee 5168 #define regPCIEMSIX_VECT59_MSG_DATA_BASE_IDX 5 5169 #define regPCIEMSIX_VECT59_CONTROL 0x1e0ef 5170 #define regPCIEMSIX_VECT59_CONTROL_BASE_IDX 5 5171 #define regPCIEMSIX_VECT60_ADDR_LO 0x1e0f0 5172 #define regPCIEMSIX_VECT60_ADDR_LO_BASE_IDX 5 5173 #define regPCIEMSIX_VECT60_ADDR_HI 0x1e0f1 5174 #define regPCIEMSIX_VECT60_ADDR_HI_BASE_IDX 5 5175 #define regPCIEMSIX_VECT60_MSG_DATA 0x1e0f2 5176 #define regPCIEMSIX_VECT60_MSG_DATA_BASE_IDX 5 5177 #define regPCIEMSIX_VECT60_CONTROL 0x1e0f3 5178 #define regPCIEMSIX_VECT60_CONTROL_BASE_IDX 5 5179 #define regPCIEMSIX_VECT61_ADDR_LO 0x1e0f4 5180 #define regPCIEMSIX_VECT61_ADDR_LO_BASE_IDX 5 5181 #define regPCIEMSIX_VECT61_ADDR_HI 0x1e0f5 5182 #define regPCIEMSIX_VECT61_ADDR_HI_BASE_IDX 5 5183 #define regPCIEMSIX_VECT61_MSG_DATA 0x1e0f6 5184 #define regPCIEMSIX_VECT61_MSG_DATA_BASE_IDX 5 5185 #define regPCIEMSIX_VECT61_CONTROL 0x1e0f7 5186 #define regPCIEMSIX_VECT61_CONTROL_BASE_IDX 5 5187 #define regPCIEMSIX_VECT62_ADDR_LO 0x1e0f8 5188 #define regPCIEMSIX_VECT62_ADDR_LO_BASE_IDX 5 5189 #define regPCIEMSIX_VECT62_ADDR_HI 0x1e0f9 5190 #define regPCIEMSIX_VECT62_ADDR_HI_BASE_IDX 5 5191 #define regPCIEMSIX_VECT62_MSG_DATA 0x1e0fa 5192 #define regPCIEMSIX_VECT62_MSG_DATA_BASE_IDX 5 5193 #define regPCIEMSIX_VECT62_CONTROL 0x1e0fb 5194 #define regPCIEMSIX_VECT62_CONTROL_BASE_IDX 5 5195 #define regPCIEMSIX_VECT63_ADDR_LO 0x1e0fc 5196 #define regPCIEMSIX_VECT63_ADDR_LO_BASE_IDX 5 5197 #define regPCIEMSIX_VECT63_ADDR_HI 0x1e0fd 5198 #define regPCIEMSIX_VECT63_ADDR_HI_BASE_IDX 5 5199 #define regPCIEMSIX_VECT63_MSG_DATA 0x1e0fe 5200 #define regPCIEMSIX_VECT63_MSG_DATA_BASE_IDX 5 5201 #define regPCIEMSIX_VECT63_CONTROL 0x1e0ff 5202 #define regPCIEMSIX_VECT63_CONTROL_BASE_IDX 5 5203 #define regPCIEMSIX_VECT64_ADDR_LO 0x1e100 5204 #define regPCIEMSIX_VECT64_ADDR_LO_BASE_IDX 5 5205 #define regPCIEMSIX_VECT64_ADDR_HI 0x1e101 5206 #define regPCIEMSIX_VECT64_ADDR_HI_BASE_IDX 5 5207 #define regPCIEMSIX_VECT64_MSG_DATA 0x1e102 5208 #define regPCIEMSIX_VECT64_MSG_DATA_BASE_IDX 5 5209 #define regPCIEMSIX_VECT64_CONTROL 0x1e103 5210 #define regPCIEMSIX_VECT64_CONTROL_BASE_IDX 5 5211 #define regPCIEMSIX_VECT65_ADDR_LO 0x1e104 5212 #define regPCIEMSIX_VECT65_ADDR_LO_BASE_IDX 5 5213 #define regPCIEMSIX_VECT65_ADDR_HI 0x1e105 5214 #define regPCIEMSIX_VECT65_ADDR_HI_BASE_IDX 5 5215 #define regPCIEMSIX_VECT65_MSG_DATA 0x1e106 5216 #define regPCIEMSIX_VECT65_MSG_DATA_BASE_IDX 5 5217 #define regPCIEMSIX_VECT65_CONTROL 0x1e107 5218 #define regPCIEMSIX_VECT65_CONTROL_BASE_IDX 5 5219 #define regPCIEMSIX_VECT66_ADDR_LO 0x1e108 5220 #define regPCIEMSIX_VECT66_ADDR_LO_BASE_IDX 5 5221 #define regPCIEMSIX_VECT66_ADDR_HI 0x1e109 5222 #define regPCIEMSIX_VECT66_ADDR_HI_BASE_IDX 5 5223 #define regPCIEMSIX_VECT66_MSG_DATA 0x1e10a 5224 #define regPCIEMSIX_VECT66_MSG_DATA_BASE_IDX 5 5225 #define regPCIEMSIX_VECT66_CONTROL 0x1e10b 5226 #define regPCIEMSIX_VECT66_CONTROL_BASE_IDX 5 5227 #define regPCIEMSIX_VECT67_ADDR_LO 0x1e10c 5228 #define regPCIEMSIX_VECT67_ADDR_LO_BASE_IDX 5 5229 #define regPCIEMSIX_VECT67_ADDR_HI 0x1e10d 5230 #define regPCIEMSIX_VECT67_ADDR_HI_BASE_IDX 5 5231 #define regPCIEMSIX_VECT67_MSG_DATA 0x1e10e 5232 #define regPCIEMSIX_VECT67_MSG_DATA_BASE_IDX 5 5233 #define regPCIEMSIX_VECT67_CONTROL 0x1e10f 5234 #define regPCIEMSIX_VECT67_CONTROL_BASE_IDX 5 5235 #define regPCIEMSIX_VECT68_ADDR_LO 0x1e110 5236 #define regPCIEMSIX_VECT68_ADDR_LO_BASE_IDX 5 5237 #define regPCIEMSIX_VECT68_ADDR_HI 0x1e111 5238 #define regPCIEMSIX_VECT68_ADDR_HI_BASE_IDX 5 5239 #define regPCIEMSIX_VECT68_MSG_DATA 0x1e112 5240 #define regPCIEMSIX_VECT68_MSG_DATA_BASE_IDX 5 5241 #define regPCIEMSIX_VECT68_CONTROL 0x1e113 5242 #define regPCIEMSIX_VECT68_CONTROL_BASE_IDX 5 5243 #define regPCIEMSIX_VECT69_ADDR_LO 0x1e114 5244 #define regPCIEMSIX_VECT69_ADDR_LO_BASE_IDX 5 5245 #define regPCIEMSIX_VECT69_ADDR_HI 0x1e115 5246 #define regPCIEMSIX_VECT69_ADDR_HI_BASE_IDX 5 5247 #define regPCIEMSIX_VECT69_MSG_DATA 0x1e116 5248 #define regPCIEMSIX_VECT69_MSG_DATA_BASE_IDX 5 5249 #define regPCIEMSIX_VECT69_CONTROL 0x1e117 5250 #define regPCIEMSIX_VECT69_CONTROL_BASE_IDX 5 5251 #define regPCIEMSIX_VECT70_ADDR_LO 0x1e118 5252 #define regPCIEMSIX_VECT70_ADDR_LO_BASE_IDX 5 5253 #define regPCIEMSIX_VECT70_ADDR_HI 0x1e119 5254 #define regPCIEMSIX_VECT70_ADDR_HI_BASE_IDX 5 5255 #define regPCIEMSIX_VECT70_MSG_DATA 0x1e11a 5256 #define regPCIEMSIX_VECT70_MSG_DATA_BASE_IDX 5 5257 #define regPCIEMSIX_VECT70_CONTROL 0x1e11b 5258 #define regPCIEMSIX_VECT70_CONTROL_BASE_IDX 5 5259 #define regPCIEMSIX_VECT71_ADDR_LO 0x1e11c 5260 #define regPCIEMSIX_VECT71_ADDR_LO_BASE_IDX 5 5261 #define regPCIEMSIX_VECT71_ADDR_HI 0x1e11d 5262 #define regPCIEMSIX_VECT71_ADDR_HI_BASE_IDX 5 5263 #define regPCIEMSIX_VECT71_MSG_DATA 0x1e11e 5264 #define regPCIEMSIX_VECT71_MSG_DATA_BASE_IDX 5 5265 #define regPCIEMSIX_VECT71_CONTROL 0x1e11f 5266 #define regPCIEMSIX_VECT71_CONTROL_BASE_IDX 5 5267 #define regPCIEMSIX_VECT72_ADDR_LO 0x1e120 5268 #define regPCIEMSIX_VECT72_ADDR_LO_BASE_IDX 5 5269 #define regPCIEMSIX_VECT72_ADDR_HI 0x1e121 5270 #define regPCIEMSIX_VECT72_ADDR_HI_BASE_IDX 5 5271 #define regPCIEMSIX_VECT72_MSG_DATA 0x1e122 5272 #define regPCIEMSIX_VECT72_MSG_DATA_BASE_IDX 5 5273 #define regPCIEMSIX_VECT72_CONTROL 0x1e123 5274 #define regPCIEMSIX_VECT72_CONTROL_BASE_IDX 5 5275 #define regPCIEMSIX_VECT73_ADDR_LO 0x1e124 5276 #define regPCIEMSIX_VECT73_ADDR_LO_BASE_IDX 5 5277 #define regPCIEMSIX_VECT73_ADDR_HI 0x1e125 5278 #define regPCIEMSIX_VECT73_ADDR_HI_BASE_IDX 5 5279 #define regPCIEMSIX_VECT73_MSG_DATA 0x1e126 5280 #define regPCIEMSIX_VECT73_MSG_DATA_BASE_IDX 5 5281 #define regPCIEMSIX_VECT73_CONTROL 0x1e127 5282 #define regPCIEMSIX_VECT73_CONTROL_BASE_IDX 5 5283 #define regPCIEMSIX_VECT74_ADDR_LO 0x1e128 5284 #define regPCIEMSIX_VECT74_ADDR_LO_BASE_IDX 5 5285 #define regPCIEMSIX_VECT74_ADDR_HI 0x1e129 5286 #define regPCIEMSIX_VECT74_ADDR_HI_BASE_IDX 5 5287 #define regPCIEMSIX_VECT74_MSG_DATA 0x1e12a 5288 #define regPCIEMSIX_VECT74_MSG_DATA_BASE_IDX 5 5289 #define regPCIEMSIX_VECT74_CONTROL 0x1e12b 5290 #define regPCIEMSIX_VECT74_CONTROL_BASE_IDX 5 5291 #define regPCIEMSIX_VECT75_ADDR_LO 0x1e12c 5292 #define regPCIEMSIX_VECT75_ADDR_LO_BASE_IDX 5 5293 #define regPCIEMSIX_VECT75_ADDR_HI 0x1e12d 5294 #define regPCIEMSIX_VECT75_ADDR_HI_BASE_IDX 5 5295 #define regPCIEMSIX_VECT75_MSG_DATA 0x1e12e 5296 #define regPCIEMSIX_VECT75_MSG_DATA_BASE_IDX 5 5297 #define regPCIEMSIX_VECT75_CONTROL 0x1e12f 5298 #define regPCIEMSIX_VECT75_CONTROL_BASE_IDX 5 5299 #define regPCIEMSIX_VECT76_ADDR_LO 0x1e130 5300 #define regPCIEMSIX_VECT76_ADDR_LO_BASE_IDX 5 5301 #define regPCIEMSIX_VECT76_ADDR_HI 0x1e131 5302 #define regPCIEMSIX_VECT76_ADDR_HI_BASE_IDX 5 5303 #define regPCIEMSIX_VECT76_MSG_DATA 0x1e132 5304 #define regPCIEMSIX_VECT76_MSG_DATA_BASE_IDX 5 5305 #define regPCIEMSIX_VECT76_CONTROL 0x1e133 5306 #define regPCIEMSIX_VECT76_CONTROL_BASE_IDX 5 5307 #define regPCIEMSIX_VECT77_ADDR_LO 0x1e134 5308 #define regPCIEMSIX_VECT77_ADDR_LO_BASE_IDX 5 5309 #define regPCIEMSIX_VECT77_ADDR_HI 0x1e135 5310 #define regPCIEMSIX_VECT77_ADDR_HI_BASE_IDX 5 5311 #define regPCIEMSIX_VECT77_MSG_DATA 0x1e136 5312 #define regPCIEMSIX_VECT77_MSG_DATA_BASE_IDX 5 5313 #define regPCIEMSIX_VECT77_CONTROL 0x1e137 5314 #define regPCIEMSIX_VECT77_CONTROL_BASE_IDX 5 5315 #define regPCIEMSIX_VECT78_ADDR_LO 0x1e138 5316 #define regPCIEMSIX_VECT78_ADDR_LO_BASE_IDX 5 5317 #define regPCIEMSIX_VECT78_ADDR_HI 0x1e139 5318 #define regPCIEMSIX_VECT78_ADDR_HI_BASE_IDX 5 5319 #define regPCIEMSIX_VECT78_MSG_DATA 0x1e13a 5320 #define regPCIEMSIX_VECT78_MSG_DATA_BASE_IDX 5 5321 #define regPCIEMSIX_VECT78_CONTROL 0x1e13b 5322 #define regPCIEMSIX_VECT78_CONTROL_BASE_IDX 5 5323 #define regPCIEMSIX_VECT79_ADDR_LO 0x1e13c 5324 #define regPCIEMSIX_VECT79_ADDR_LO_BASE_IDX 5 5325 #define regPCIEMSIX_VECT79_ADDR_HI 0x1e13d 5326 #define regPCIEMSIX_VECT79_ADDR_HI_BASE_IDX 5 5327 #define regPCIEMSIX_VECT79_MSG_DATA 0x1e13e 5328 #define regPCIEMSIX_VECT79_MSG_DATA_BASE_IDX 5 5329 #define regPCIEMSIX_VECT79_CONTROL 0x1e13f 5330 #define regPCIEMSIX_VECT79_CONTROL_BASE_IDX 5 5331 #define regPCIEMSIX_VECT80_ADDR_LO 0x1e140 5332 #define regPCIEMSIX_VECT80_ADDR_LO_BASE_IDX 5 5333 #define regPCIEMSIX_VECT80_ADDR_HI 0x1e141 5334 #define regPCIEMSIX_VECT80_ADDR_HI_BASE_IDX 5 5335 #define regPCIEMSIX_VECT80_MSG_DATA 0x1e142 5336 #define regPCIEMSIX_VECT80_MSG_DATA_BASE_IDX 5 5337 #define regPCIEMSIX_VECT80_CONTROL 0x1e143 5338 #define regPCIEMSIX_VECT80_CONTROL_BASE_IDX 5 5339 #define regPCIEMSIX_VECT81_ADDR_LO 0x1e144 5340 #define regPCIEMSIX_VECT81_ADDR_LO_BASE_IDX 5 5341 #define regPCIEMSIX_VECT81_ADDR_HI 0x1e145 5342 #define regPCIEMSIX_VECT81_ADDR_HI_BASE_IDX 5 5343 #define regPCIEMSIX_VECT81_MSG_DATA 0x1e146 5344 #define regPCIEMSIX_VECT81_MSG_DATA_BASE_IDX 5 5345 #define regPCIEMSIX_VECT81_CONTROL 0x1e147 5346 #define regPCIEMSIX_VECT81_CONTROL_BASE_IDX 5 5347 #define regPCIEMSIX_VECT82_ADDR_LO 0x1e148 5348 #define regPCIEMSIX_VECT82_ADDR_LO_BASE_IDX 5 5349 #define regPCIEMSIX_VECT82_ADDR_HI 0x1e149 5350 #define regPCIEMSIX_VECT82_ADDR_HI_BASE_IDX 5 5351 #define regPCIEMSIX_VECT82_MSG_DATA 0x1e14a 5352 #define regPCIEMSIX_VECT82_MSG_DATA_BASE_IDX 5 5353 #define regPCIEMSIX_VECT82_CONTROL 0x1e14b 5354 #define regPCIEMSIX_VECT82_CONTROL_BASE_IDX 5 5355 #define regPCIEMSIX_VECT83_ADDR_LO 0x1e14c 5356 #define regPCIEMSIX_VECT83_ADDR_LO_BASE_IDX 5 5357 #define regPCIEMSIX_VECT83_ADDR_HI 0x1e14d 5358 #define regPCIEMSIX_VECT83_ADDR_HI_BASE_IDX 5 5359 #define regPCIEMSIX_VECT83_MSG_DATA 0x1e14e 5360 #define regPCIEMSIX_VECT83_MSG_DATA_BASE_IDX 5 5361 #define regPCIEMSIX_VECT83_CONTROL 0x1e14f 5362 #define regPCIEMSIX_VECT83_CONTROL_BASE_IDX 5 5363 #define regPCIEMSIX_VECT84_ADDR_LO 0x1e150 5364 #define regPCIEMSIX_VECT84_ADDR_LO_BASE_IDX 5 5365 #define regPCIEMSIX_VECT84_ADDR_HI 0x1e151 5366 #define regPCIEMSIX_VECT84_ADDR_HI_BASE_IDX 5 5367 #define regPCIEMSIX_VECT84_MSG_DATA 0x1e152 5368 #define regPCIEMSIX_VECT84_MSG_DATA_BASE_IDX 5 5369 #define regPCIEMSIX_VECT84_CONTROL 0x1e153 5370 #define regPCIEMSIX_VECT84_CONTROL_BASE_IDX 5 5371 #define regPCIEMSIX_VECT85_ADDR_LO 0x1e154 5372 #define regPCIEMSIX_VECT85_ADDR_LO_BASE_IDX 5 5373 #define regPCIEMSIX_VECT85_ADDR_HI 0x1e155 5374 #define regPCIEMSIX_VECT85_ADDR_HI_BASE_IDX 5 5375 #define regPCIEMSIX_VECT85_MSG_DATA 0x1e156 5376 #define regPCIEMSIX_VECT85_MSG_DATA_BASE_IDX 5 5377 #define regPCIEMSIX_VECT85_CONTROL 0x1e157 5378 #define regPCIEMSIX_VECT85_CONTROL_BASE_IDX 5 5379 #define regPCIEMSIX_VECT86_ADDR_LO 0x1e158 5380 #define regPCIEMSIX_VECT86_ADDR_LO_BASE_IDX 5 5381 #define regPCIEMSIX_VECT86_ADDR_HI 0x1e159 5382 #define regPCIEMSIX_VECT86_ADDR_HI_BASE_IDX 5 5383 #define regPCIEMSIX_VECT86_MSG_DATA 0x1e15a 5384 #define regPCIEMSIX_VECT86_MSG_DATA_BASE_IDX 5 5385 #define regPCIEMSIX_VECT86_CONTROL 0x1e15b 5386 #define regPCIEMSIX_VECT86_CONTROL_BASE_IDX 5 5387 #define regPCIEMSIX_VECT87_ADDR_LO 0x1e15c 5388 #define regPCIEMSIX_VECT87_ADDR_LO_BASE_IDX 5 5389 #define regPCIEMSIX_VECT87_ADDR_HI 0x1e15d 5390 #define regPCIEMSIX_VECT87_ADDR_HI_BASE_IDX 5 5391 #define regPCIEMSIX_VECT87_MSG_DATA 0x1e15e 5392 #define regPCIEMSIX_VECT87_MSG_DATA_BASE_IDX 5 5393 #define regPCIEMSIX_VECT87_CONTROL 0x1e15f 5394 #define regPCIEMSIX_VECT87_CONTROL_BASE_IDX 5 5395 #define regPCIEMSIX_VECT88_ADDR_LO 0x1e160 5396 #define regPCIEMSIX_VECT88_ADDR_LO_BASE_IDX 5 5397 #define regPCIEMSIX_VECT88_ADDR_HI 0x1e161 5398 #define regPCIEMSIX_VECT88_ADDR_HI_BASE_IDX 5 5399 #define regPCIEMSIX_VECT88_MSG_DATA 0x1e162 5400 #define regPCIEMSIX_VECT88_MSG_DATA_BASE_IDX 5 5401 #define regPCIEMSIX_VECT88_CONTROL 0x1e163 5402 #define regPCIEMSIX_VECT88_CONTROL_BASE_IDX 5 5403 #define regPCIEMSIX_VECT89_ADDR_LO 0x1e164 5404 #define regPCIEMSIX_VECT89_ADDR_LO_BASE_IDX 5 5405 #define regPCIEMSIX_VECT89_ADDR_HI 0x1e165 5406 #define regPCIEMSIX_VECT89_ADDR_HI_BASE_IDX 5 5407 #define regPCIEMSIX_VECT89_MSG_DATA 0x1e166 5408 #define regPCIEMSIX_VECT89_MSG_DATA_BASE_IDX 5 5409 #define regPCIEMSIX_VECT89_CONTROL 0x1e167 5410 #define regPCIEMSIX_VECT89_CONTROL_BASE_IDX 5 5411 #define regPCIEMSIX_VECT90_ADDR_LO 0x1e168 5412 #define regPCIEMSIX_VECT90_ADDR_LO_BASE_IDX 5 5413 #define regPCIEMSIX_VECT90_ADDR_HI 0x1e169 5414 #define regPCIEMSIX_VECT90_ADDR_HI_BASE_IDX 5 5415 #define regPCIEMSIX_VECT90_MSG_DATA 0x1e16a 5416 #define regPCIEMSIX_VECT90_MSG_DATA_BASE_IDX 5 5417 #define regPCIEMSIX_VECT90_CONTROL 0x1e16b 5418 #define regPCIEMSIX_VECT90_CONTROL_BASE_IDX 5 5419 #define regPCIEMSIX_VECT91_ADDR_LO 0x1e16c 5420 #define regPCIEMSIX_VECT91_ADDR_LO_BASE_IDX 5 5421 #define regPCIEMSIX_VECT91_ADDR_HI 0x1e16d 5422 #define regPCIEMSIX_VECT91_ADDR_HI_BASE_IDX 5 5423 #define regPCIEMSIX_VECT91_MSG_DATA 0x1e16e 5424 #define regPCIEMSIX_VECT91_MSG_DATA_BASE_IDX 5 5425 #define regPCIEMSIX_VECT91_CONTROL 0x1e16f 5426 #define regPCIEMSIX_VECT91_CONTROL_BASE_IDX 5 5427 #define regPCIEMSIX_VECT92_ADDR_LO 0x1e170 5428 #define regPCIEMSIX_VECT92_ADDR_LO_BASE_IDX 5 5429 #define regPCIEMSIX_VECT92_ADDR_HI 0x1e171 5430 #define regPCIEMSIX_VECT92_ADDR_HI_BASE_IDX 5 5431 #define regPCIEMSIX_VECT92_MSG_DATA 0x1e172 5432 #define regPCIEMSIX_VECT92_MSG_DATA_BASE_IDX 5 5433 #define regPCIEMSIX_VECT92_CONTROL 0x1e173 5434 #define regPCIEMSIX_VECT92_CONTROL_BASE_IDX 5 5435 #define regPCIEMSIX_VECT93_ADDR_LO 0x1e174 5436 #define regPCIEMSIX_VECT93_ADDR_LO_BASE_IDX 5 5437 #define regPCIEMSIX_VECT93_ADDR_HI 0x1e175 5438 #define regPCIEMSIX_VECT93_ADDR_HI_BASE_IDX 5 5439 #define regPCIEMSIX_VECT93_MSG_DATA 0x1e176 5440 #define regPCIEMSIX_VECT93_MSG_DATA_BASE_IDX 5 5441 #define regPCIEMSIX_VECT93_CONTROL 0x1e177 5442 #define regPCIEMSIX_VECT93_CONTROL_BASE_IDX 5 5443 #define regPCIEMSIX_VECT94_ADDR_LO 0x1e178 5444 #define regPCIEMSIX_VECT94_ADDR_LO_BASE_IDX 5 5445 #define regPCIEMSIX_VECT94_ADDR_HI 0x1e179 5446 #define regPCIEMSIX_VECT94_ADDR_HI_BASE_IDX 5 5447 #define regPCIEMSIX_VECT94_MSG_DATA 0x1e17a 5448 #define regPCIEMSIX_VECT94_MSG_DATA_BASE_IDX 5 5449 #define regPCIEMSIX_VECT94_CONTROL 0x1e17b 5450 #define regPCIEMSIX_VECT94_CONTROL_BASE_IDX 5 5451 #define regPCIEMSIX_VECT95_ADDR_LO 0x1e17c 5452 #define regPCIEMSIX_VECT95_ADDR_LO_BASE_IDX 5 5453 #define regPCIEMSIX_VECT95_ADDR_HI 0x1e17d 5454 #define regPCIEMSIX_VECT95_ADDR_HI_BASE_IDX 5 5455 #define regPCIEMSIX_VECT95_MSG_DATA 0x1e17e 5456 #define regPCIEMSIX_VECT95_MSG_DATA_BASE_IDX 5 5457 #define regPCIEMSIX_VECT95_CONTROL 0x1e17f 5458 #define regPCIEMSIX_VECT95_CONTROL_BASE_IDX 5 5459 #define regPCIEMSIX_VECT96_ADDR_LO 0x1e180 5460 #define regPCIEMSIX_VECT96_ADDR_LO_BASE_IDX 5 5461 #define regPCIEMSIX_VECT96_ADDR_HI 0x1e181 5462 #define regPCIEMSIX_VECT96_ADDR_HI_BASE_IDX 5 5463 #define regPCIEMSIX_VECT96_MSG_DATA 0x1e182 5464 #define regPCIEMSIX_VECT96_MSG_DATA_BASE_IDX 5 5465 #define regPCIEMSIX_VECT96_CONTROL 0x1e183 5466 #define regPCIEMSIX_VECT96_CONTROL_BASE_IDX 5 5467 #define regPCIEMSIX_VECT97_ADDR_LO 0x1e184 5468 #define regPCIEMSIX_VECT97_ADDR_LO_BASE_IDX 5 5469 #define regPCIEMSIX_VECT97_ADDR_HI 0x1e185 5470 #define regPCIEMSIX_VECT97_ADDR_HI_BASE_IDX 5 5471 #define regPCIEMSIX_VECT97_MSG_DATA 0x1e186 5472 #define regPCIEMSIX_VECT97_MSG_DATA_BASE_IDX 5 5473 #define regPCIEMSIX_VECT97_CONTROL 0x1e187 5474 #define regPCIEMSIX_VECT97_CONTROL_BASE_IDX 5 5475 #define regPCIEMSIX_VECT98_ADDR_LO 0x1e188 5476 #define regPCIEMSIX_VECT98_ADDR_LO_BASE_IDX 5 5477 #define regPCIEMSIX_VECT98_ADDR_HI 0x1e189 5478 #define regPCIEMSIX_VECT98_ADDR_HI_BASE_IDX 5 5479 #define regPCIEMSIX_VECT98_MSG_DATA 0x1e18a 5480 #define regPCIEMSIX_VECT98_MSG_DATA_BASE_IDX 5 5481 #define regPCIEMSIX_VECT98_CONTROL 0x1e18b 5482 #define regPCIEMSIX_VECT98_CONTROL_BASE_IDX 5 5483 #define regPCIEMSIX_VECT99_ADDR_LO 0x1e18c 5484 #define regPCIEMSIX_VECT99_ADDR_LO_BASE_IDX 5 5485 #define regPCIEMSIX_VECT99_ADDR_HI 0x1e18d 5486 #define regPCIEMSIX_VECT99_ADDR_HI_BASE_IDX 5 5487 #define regPCIEMSIX_VECT99_MSG_DATA 0x1e18e 5488 #define regPCIEMSIX_VECT99_MSG_DATA_BASE_IDX 5 5489 #define regPCIEMSIX_VECT99_CONTROL 0x1e18f 5490 #define regPCIEMSIX_VECT99_CONTROL_BASE_IDX 5 5491 #define regPCIEMSIX_VECT100_ADDR_LO 0x1e190 5492 #define regPCIEMSIX_VECT100_ADDR_LO_BASE_IDX 5 5493 #define regPCIEMSIX_VECT100_ADDR_HI 0x1e191 5494 #define regPCIEMSIX_VECT100_ADDR_HI_BASE_IDX 5 5495 #define regPCIEMSIX_VECT100_MSG_DATA 0x1e192 5496 #define regPCIEMSIX_VECT100_MSG_DATA_BASE_IDX 5 5497 #define regPCIEMSIX_VECT100_CONTROL 0x1e193 5498 #define regPCIEMSIX_VECT100_CONTROL_BASE_IDX 5 5499 #define regPCIEMSIX_VECT101_ADDR_LO 0x1e194 5500 #define regPCIEMSIX_VECT101_ADDR_LO_BASE_IDX 5 5501 #define regPCIEMSIX_VECT101_ADDR_HI 0x1e195 5502 #define regPCIEMSIX_VECT101_ADDR_HI_BASE_IDX 5 5503 #define regPCIEMSIX_VECT101_MSG_DATA 0x1e196 5504 #define regPCIEMSIX_VECT101_MSG_DATA_BASE_IDX 5 5505 #define regPCIEMSIX_VECT101_CONTROL 0x1e197 5506 #define regPCIEMSIX_VECT101_CONTROL_BASE_IDX 5 5507 #define regPCIEMSIX_VECT102_ADDR_LO 0x1e198 5508 #define regPCIEMSIX_VECT102_ADDR_LO_BASE_IDX 5 5509 #define regPCIEMSIX_VECT102_ADDR_HI 0x1e199 5510 #define regPCIEMSIX_VECT102_ADDR_HI_BASE_IDX 5 5511 #define regPCIEMSIX_VECT102_MSG_DATA 0x1e19a 5512 #define regPCIEMSIX_VECT102_MSG_DATA_BASE_IDX 5 5513 #define regPCIEMSIX_VECT102_CONTROL 0x1e19b 5514 #define regPCIEMSIX_VECT102_CONTROL_BASE_IDX 5 5515 #define regPCIEMSIX_VECT103_ADDR_LO 0x1e19c 5516 #define regPCIEMSIX_VECT103_ADDR_LO_BASE_IDX 5 5517 #define regPCIEMSIX_VECT103_ADDR_HI 0x1e19d 5518 #define regPCIEMSIX_VECT103_ADDR_HI_BASE_IDX 5 5519 #define regPCIEMSIX_VECT103_MSG_DATA 0x1e19e 5520 #define regPCIEMSIX_VECT103_MSG_DATA_BASE_IDX 5 5521 #define regPCIEMSIX_VECT103_CONTROL 0x1e19f 5522 #define regPCIEMSIX_VECT103_CONTROL_BASE_IDX 5 5523 #define regPCIEMSIX_VECT104_ADDR_LO 0x1e1a0 5524 #define regPCIEMSIX_VECT104_ADDR_LO_BASE_IDX 5 5525 #define regPCIEMSIX_VECT104_ADDR_HI 0x1e1a1 5526 #define regPCIEMSIX_VECT104_ADDR_HI_BASE_IDX 5 5527 #define regPCIEMSIX_VECT104_MSG_DATA 0x1e1a2 5528 #define regPCIEMSIX_VECT104_MSG_DATA_BASE_IDX 5 5529 #define regPCIEMSIX_VECT104_CONTROL 0x1e1a3 5530 #define regPCIEMSIX_VECT104_CONTROL_BASE_IDX 5 5531 #define regPCIEMSIX_VECT105_ADDR_LO 0x1e1a4 5532 #define regPCIEMSIX_VECT105_ADDR_LO_BASE_IDX 5 5533 #define regPCIEMSIX_VECT105_ADDR_HI 0x1e1a5 5534 #define regPCIEMSIX_VECT105_ADDR_HI_BASE_IDX 5 5535 #define regPCIEMSIX_VECT105_MSG_DATA 0x1e1a6 5536 #define regPCIEMSIX_VECT105_MSG_DATA_BASE_IDX 5 5537 #define regPCIEMSIX_VECT105_CONTROL 0x1e1a7 5538 #define regPCIEMSIX_VECT105_CONTROL_BASE_IDX 5 5539 #define regPCIEMSIX_VECT106_ADDR_LO 0x1e1a8 5540 #define regPCIEMSIX_VECT106_ADDR_LO_BASE_IDX 5 5541 #define regPCIEMSIX_VECT106_ADDR_HI 0x1e1a9 5542 #define regPCIEMSIX_VECT106_ADDR_HI_BASE_IDX 5 5543 #define regPCIEMSIX_VECT106_MSG_DATA 0x1e1aa 5544 #define regPCIEMSIX_VECT106_MSG_DATA_BASE_IDX 5 5545 #define regPCIEMSIX_VECT106_CONTROL 0x1e1ab 5546 #define regPCIEMSIX_VECT106_CONTROL_BASE_IDX 5 5547 #define regPCIEMSIX_VECT107_ADDR_LO 0x1e1ac 5548 #define regPCIEMSIX_VECT107_ADDR_LO_BASE_IDX 5 5549 #define regPCIEMSIX_VECT107_ADDR_HI 0x1e1ad 5550 #define regPCIEMSIX_VECT107_ADDR_HI_BASE_IDX 5 5551 #define regPCIEMSIX_VECT107_MSG_DATA 0x1e1ae 5552 #define regPCIEMSIX_VECT107_MSG_DATA_BASE_IDX 5 5553 #define regPCIEMSIX_VECT107_CONTROL 0x1e1af 5554 #define regPCIEMSIX_VECT107_CONTROL_BASE_IDX 5 5555 #define regPCIEMSIX_VECT108_ADDR_LO 0x1e1b0 5556 #define regPCIEMSIX_VECT108_ADDR_LO_BASE_IDX 5 5557 #define regPCIEMSIX_VECT108_ADDR_HI 0x1e1b1 5558 #define regPCIEMSIX_VECT108_ADDR_HI_BASE_IDX 5 5559 #define regPCIEMSIX_VECT108_MSG_DATA 0x1e1b2 5560 #define regPCIEMSIX_VECT108_MSG_DATA_BASE_IDX 5 5561 #define regPCIEMSIX_VECT108_CONTROL 0x1e1b3 5562 #define regPCIEMSIX_VECT108_CONTROL_BASE_IDX 5 5563 #define regPCIEMSIX_VECT109_ADDR_LO 0x1e1b4 5564 #define regPCIEMSIX_VECT109_ADDR_LO_BASE_IDX 5 5565 #define regPCIEMSIX_VECT109_ADDR_HI 0x1e1b5 5566 #define regPCIEMSIX_VECT109_ADDR_HI_BASE_IDX 5 5567 #define regPCIEMSIX_VECT109_MSG_DATA 0x1e1b6 5568 #define regPCIEMSIX_VECT109_MSG_DATA_BASE_IDX 5 5569 #define regPCIEMSIX_VECT109_CONTROL 0x1e1b7 5570 #define regPCIEMSIX_VECT109_CONTROL_BASE_IDX 5 5571 #define regPCIEMSIX_VECT110_ADDR_LO 0x1e1b8 5572 #define regPCIEMSIX_VECT110_ADDR_LO_BASE_IDX 5 5573 #define regPCIEMSIX_VECT110_ADDR_HI 0x1e1b9 5574 #define regPCIEMSIX_VECT110_ADDR_HI_BASE_IDX 5 5575 #define regPCIEMSIX_VECT110_MSG_DATA 0x1e1ba 5576 #define regPCIEMSIX_VECT110_MSG_DATA_BASE_IDX 5 5577 #define regPCIEMSIX_VECT110_CONTROL 0x1e1bb 5578 #define regPCIEMSIX_VECT110_CONTROL_BASE_IDX 5 5579 #define regPCIEMSIX_VECT111_ADDR_LO 0x1e1bc 5580 #define regPCIEMSIX_VECT111_ADDR_LO_BASE_IDX 5 5581 #define regPCIEMSIX_VECT111_ADDR_HI 0x1e1bd 5582 #define regPCIEMSIX_VECT111_ADDR_HI_BASE_IDX 5 5583 #define regPCIEMSIX_VECT111_MSG_DATA 0x1e1be 5584 #define regPCIEMSIX_VECT111_MSG_DATA_BASE_IDX 5 5585 #define regPCIEMSIX_VECT111_CONTROL 0x1e1bf 5586 #define regPCIEMSIX_VECT111_CONTROL_BASE_IDX 5 5587 #define regPCIEMSIX_VECT112_ADDR_LO 0x1e1c0 5588 #define regPCIEMSIX_VECT112_ADDR_LO_BASE_IDX 5 5589 #define regPCIEMSIX_VECT112_ADDR_HI 0x1e1c1 5590 #define regPCIEMSIX_VECT112_ADDR_HI_BASE_IDX 5 5591 #define regPCIEMSIX_VECT112_MSG_DATA 0x1e1c2 5592 #define regPCIEMSIX_VECT112_MSG_DATA_BASE_IDX 5 5593 #define regPCIEMSIX_VECT112_CONTROL 0x1e1c3 5594 #define regPCIEMSIX_VECT112_CONTROL_BASE_IDX 5 5595 #define regPCIEMSIX_VECT113_ADDR_LO 0x1e1c4 5596 #define regPCIEMSIX_VECT113_ADDR_LO_BASE_IDX 5 5597 #define regPCIEMSIX_VECT113_ADDR_HI 0x1e1c5 5598 #define regPCIEMSIX_VECT113_ADDR_HI_BASE_IDX 5 5599 #define regPCIEMSIX_VECT113_MSG_DATA 0x1e1c6 5600 #define regPCIEMSIX_VECT113_MSG_DATA_BASE_IDX 5 5601 #define regPCIEMSIX_VECT113_CONTROL 0x1e1c7 5602 #define regPCIEMSIX_VECT113_CONTROL_BASE_IDX 5 5603 #define regPCIEMSIX_VECT114_ADDR_LO 0x1e1c8 5604 #define regPCIEMSIX_VECT114_ADDR_LO_BASE_IDX 5 5605 #define regPCIEMSIX_VECT114_ADDR_HI 0x1e1c9 5606 #define regPCIEMSIX_VECT114_ADDR_HI_BASE_IDX 5 5607 #define regPCIEMSIX_VECT114_MSG_DATA 0x1e1ca 5608 #define regPCIEMSIX_VECT114_MSG_DATA_BASE_IDX 5 5609 #define regPCIEMSIX_VECT114_CONTROL 0x1e1cb 5610 #define regPCIEMSIX_VECT114_CONTROL_BASE_IDX 5 5611 #define regPCIEMSIX_VECT115_ADDR_LO 0x1e1cc 5612 #define regPCIEMSIX_VECT115_ADDR_LO_BASE_IDX 5 5613 #define regPCIEMSIX_VECT115_ADDR_HI 0x1e1cd 5614 #define regPCIEMSIX_VECT115_ADDR_HI_BASE_IDX 5 5615 #define regPCIEMSIX_VECT115_MSG_DATA 0x1e1ce 5616 #define regPCIEMSIX_VECT115_MSG_DATA_BASE_IDX 5 5617 #define regPCIEMSIX_VECT115_CONTROL 0x1e1cf 5618 #define regPCIEMSIX_VECT115_CONTROL_BASE_IDX 5 5619 #define regPCIEMSIX_VECT116_ADDR_LO 0x1e1d0 5620 #define regPCIEMSIX_VECT116_ADDR_LO_BASE_IDX 5 5621 #define regPCIEMSIX_VECT116_ADDR_HI 0x1e1d1 5622 #define regPCIEMSIX_VECT116_ADDR_HI_BASE_IDX 5 5623 #define regPCIEMSIX_VECT116_MSG_DATA 0x1e1d2 5624 #define regPCIEMSIX_VECT116_MSG_DATA_BASE_IDX 5 5625 #define regPCIEMSIX_VECT116_CONTROL 0x1e1d3 5626 #define regPCIEMSIX_VECT116_CONTROL_BASE_IDX 5 5627 #define regPCIEMSIX_VECT117_ADDR_LO 0x1e1d4 5628 #define regPCIEMSIX_VECT117_ADDR_LO_BASE_IDX 5 5629 #define regPCIEMSIX_VECT117_ADDR_HI 0x1e1d5 5630 #define regPCIEMSIX_VECT117_ADDR_HI_BASE_IDX 5 5631 #define regPCIEMSIX_VECT117_MSG_DATA 0x1e1d6 5632 #define regPCIEMSIX_VECT117_MSG_DATA_BASE_IDX 5 5633 #define regPCIEMSIX_VECT117_CONTROL 0x1e1d7 5634 #define regPCIEMSIX_VECT117_CONTROL_BASE_IDX 5 5635 #define regPCIEMSIX_VECT118_ADDR_LO 0x1e1d8 5636 #define regPCIEMSIX_VECT118_ADDR_LO_BASE_IDX 5 5637 #define regPCIEMSIX_VECT118_ADDR_HI 0x1e1d9 5638 #define regPCIEMSIX_VECT118_ADDR_HI_BASE_IDX 5 5639 #define regPCIEMSIX_VECT118_MSG_DATA 0x1e1da 5640 #define regPCIEMSIX_VECT118_MSG_DATA_BASE_IDX 5 5641 #define regPCIEMSIX_VECT118_CONTROL 0x1e1db 5642 #define regPCIEMSIX_VECT118_CONTROL_BASE_IDX 5 5643 #define regPCIEMSIX_VECT119_ADDR_LO 0x1e1dc 5644 #define regPCIEMSIX_VECT119_ADDR_LO_BASE_IDX 5 5645 #define regPCIEMSIX_VECT119_ADDR_HI 0x1e1dd 5646 #define regPCIEMSIX_VECT119_ADDR_HI_BASE_IDX 5 5647 #define regPCIEMSIX_VECT119_MSG_DATA 0x1e1de 5648 #define regPCIEMSIX_VECT119_MSG_DATA_BASE_IDX 5 5649 #define regPCIEMSIX_VECT119_CONTROL 0x1e1df 5650 #define regPCIEMSIX_VECT119_CONTROL_BASE_IDX 5 5651 #define regPCIEMSIX_VECT120_ADDR_LO 0x1e1e0 5652 #define regPCIEMSIX_VECT120_ADDR_LO_BASE_IDX 5 5653 #define regPCIEMSIX_VECT120_ADDR_HI 0x1e1e1 5654 #define regPCIEMSIX_VECT120_ADDR_HI_BASE_IDX 5 5655 #define regPCIEMSIX_VECT120_MSG_DATA 0x1e1e2 5656 #define regPCIEMSIX_VECT120_MSG_DATA_BASE_IDX 5 5657 #define regPCIEMSIX_VECT120_CONTROL 0x1e1e3 5658 #define regPCIEMSIX_VECT120_CONTROL_BASE_IDX 5 5659 #define regPCIEMSIX_VECT121_ADDR_LO 0x1e1e4 5660 #define regPCIEMSIX_VECT121_ADDR_LO_BASE_IDX 5 5661 #define regPCIEMSIX_VECT121_ADDR_HI 0x1e1e5 5662 #define regPCIEMSIX_VECT121_ADDR_HI_BASE_IDX 5 5663 #define regPCIEMSIX_VECT121_MSG_DATA 0x1e1e6 5664 #define regPCIEMSIX_VECT121_MSG_DATA_BASE_IDX 5 5665 #define regPCIEMSIX_VECT121_CONTROL 0x1e1e7 5666 #define regPCIEMSIX_VECT121_CONTROL_BASE_IDX 5 5667 #define regPCIEMSIX_VECT122_ADDR_LO 0x1e1e8 5668 #define regPCIEMSIX_VECT122_ADDR_LO_BASE_IDX 5 5669 #define regPCIEMSIX_VECT122_ADDR_HI 0x1e1e9 5670 #define regPCIEMSIX_VECT122_ADDR_HI_BASE_IDX 5 5671 #define regPCIEMSIX_VECT122_MSG_DATA 0x1e1ea 5672 #define regPCIEMSIX_VECT122_MSG_DATA_BASE_IDX 5 5673 #define regPCIEMSIX_VECT122_CONTROL 0x1e1eb 5674 #define regPCIEMSIX_VECT122_CONTROL_BASE_IDX 5 5675 #define regPCIEMSIX_VECT123_ADDR_LO 0x1e1ec 5676 #define regPCIEMSIX_VECT123_ADDR_LO_BASE_IDX 5 5677 #define regPCIEMSIX_VECT123_ADDR_HI 0x1e1ed 5678 #define regPCIEMSIX_VECT123_ADDR_HI_BASE_IDX 5 5679 #define regPCIEMSIX_VECT123_MSG_DATA 0x1e1ee 5680 #define regPCIEMSIX_VECT123_MSG_DATA_BASE_IDX 5 5681 #define regPCIEMSIX_VECT123_CONTROL 0x1e1ef 5682 #define regPCIEMSIX_VECT123_CONTROL_BASE_IDX 5 5683 #define regPCIEMSIX_VECT124_ADDR_LO 0x1e1f0 5684 #define regPCIEMSIX_VECT124_ADDR_LO_BASE_IDX 5 5685 #define regPCIEMSIX_VECT124_ADDR_HI 0x1e1f1 5686 #define regPCIEMSIX_VECT124_ADDR_HI_BASE_IDX 5 5687 #define regPCIEMSIX_VECT124_MSG_DATA 0x1e1f2 5688 #define regPCIEMSIX_VECT124_MSG_DATA_BASE_IDX 5 5689 #define regPCIEMSIX_VECT124_CONTROL 0x1e1f3 5690 #define regPCIEMSIX_VECT124_CONTROL_BASE_IDX 5 5691 #define regPCIEMSIX_VECT125_ADDR_LO 0x1e1f4 5692 #define regPCIEMSIX_VECT125_ADDR_LO_BASE_IDX 5 5693 #define regPCIEMSIX_VECT125_ADDR_HI 0x1e1f5 5694 #define regPCIEMSIX_VECT125_ADDR_HI_BASE_IDX 5 5695 #define regPCIEMSIX_VECT125_MSG_DATA 0x1e1f6 5696 #define regPCIEMSIX_VECT125_MSG_DATA_BASE_IDX 5 5697 #define regPCIEMSIX_VECT125_CONTROL 0x1e1f7 5698 #define regPCIEMSIX_VECT125_CONTROL_BASE_IDX 5 5699 #define regPCIEMSIX_VECT126_ADDR_LO 0x1e1f8 5700 #define regPCIEMSIX_VECT126_ADDR_LO_BASE_IDX 5 5701 #define regPCIEMSIX_VECT126_ADDR_HI 0x1e1f9 5702 #define regPCIEMSIX_VECT126_ADDR_HI_BASE_IDX 5 5703 #define regPCIEMSIX_VECT126_MSG_DATA 0x1e1fa 5704 #define regPCIEMSIX_VECT126_MSG_DATA_BASE_IDX 5 5705 #define regPCIEMSIX_VECT126_CONTROL 0x1e1fb 5706 #define regPCIEMSIX_VECT126_CONTROL_BASE_IDX 5 5707 #define regPCIEMSIX_VECT127_ADDR_LO 0x1e1fc 5708 #define regPCIEMSIX_VECT127_ADDR_LO_BASE_IDX 5 5709 #define regPCIEMSIX_VECT127_ADDR_HI 0x1e1fd 5710 #define regPCIEMSIX_VECT127_ADDR_HI_BASE_IDX 5 5711 #define regPCIEMSIX_VECT127_MSG_DATA 0x1e1fe 5712 #define regPCIEMSIX_VECT127_MSG_DATA_BASE_IDX 5 5713 #define regPCIEMSIX_VECT127_CONTROL 0x1e1ff 5714 #define regPCIEMSIX_VECT127_CONTROL_BASE_IDX 5 5715 #define regPCIEMSIX_VECT128_ADDR_LO 0x1e200 5716 #define regPCIEMSIX_VECT128_ADDR_LO_BASE_IDX 5 5717 #define regPCIEMSIX_VECT128_ADDR_HI 0x1e201 5718 #define regPCIEMSIX_VECT128_ADDR_HI_BASE_IDX 5 5719 #define regPCIEMSIX_VECT128_MSG_DATA 0x1e202 5720 #define regPCIEMSIX_VECT128_MSG_DATA_BASE_IDX 5 5721 #define regPCIEMSIX_VECT128_CONTROL 0x1e203 5722 #define regPCIEMSIX_VECT128_CONTROL_BASE_IDX 5 5723 #define regPCIEMSIX_VECT129_ADDR_LO 0x1e204 5724 #define regPCIEMSIX_VECT129_ADDR_LO_BASE_IDX 5 5725 #define regPCIEMSIX_VECT129_ADDR_HI 0x1e205 5726 #define regPCIEMSIX_VECT129_ADDR_HI_BASE_IDX 5 5727 #define regPCIEMSIX_VECT129_MSG_DATA 0x1e206 5728 #define regPCIEMSIX_VECT129_MSG_DATA_BASE_IDX 5 5729 #define regPCIEMSIX_VECT129_CONTROL 0x1e207 5730 #define regPCIEMSIX_VECT129_CONTROL_BASE_IDX 5 5731 #define regPCIEMSIX_VECT130_ADDR_LO 0x1e208 5732 #define regPCIEMSIX_VECT130_ADDR_LO_BASE_IDX 5 5733 #define regPCIEMSIX_VECT130_ADDR_HI 0x1e209 5734 #define regPCIEMSIX_VECT130_ADDR_HI_BASE_IDX 5 5735 #define regPCIEMSIX_VECT130_MSG_DATA 0x1e20a 5736 #define regPCIEMSIX_VECT130_MSG_DATA_BASE_IDX 5 5737 #define regPCIEMSIX_VECT130_CONTROL 0x1e20b 5738 #define regPCIEMSIX_VECT130_CONTROL_BASE_IDX 5 5739 #define regPCIEMSIX_VECT131_ADDR_LO 0x1e20c 5740 #define regPCIEMSIX_VECT131_ADDR_LO_BASE_IDX 5 5741 #define regPCIEMSIX_VECT131_ADDR_HI 0x1e20d 5742 #define regPCIEMSIX_VECT131_ADDR_HI_BASE_IDX 5 5743 #define regPCIEMSIX_VECT131_MSG_DATA 0x1e20e 5744 #define regPCIEMSIX_VECT131_MSG_DATA_BASE_IDX 5 5745 #define regPCIEMSIX_VECT131_CONTROL 0x1e20f 5746 #define regPCIEMSIX_VECT131_CONTROL_BASE_IDX 5 5747 #define regPCIEMSIX_VECT132_ADDR_LO 0x1e210 5748 #define regPCIEMSIX_VECT132_ADDR_LO_BASE_IDX 5 5749 #define regPCIEMSIX_VECT132_ADDR_HI 0x1e211 5750 #define regPCIEMSIX_VECT132_ADDR_HI_BASE_IDX 5 5751 #define regPCIEMSIX_VECT132_MSG_DATA 0x1e212 5752 #define regPCIEMSIX_VECT132_MSG_DATA_BASE_IDX 5 5753 #define regPCIEMSIX_VECT132_CONTROL 0x1e213 5754 #define regPCIEMSIX_VECT132_CONTROL_BASE_IDX 5 5755 #define regPCIEMSIX_VECT133_ADDR_LO 0x1e214 5756 #define regPCIEMSIX_VECT133_ADDR_LO_BASE_IDX 5 5757 #define regPCIEMSIX_VECT133_ADDR_HI 0x1e215 5758 #define regPCIEMSIX_VECT133_ADDR_HI_BASE_IDX 5 5759 #define regPCIEMSIX_VECT133_MSG_DATA 0x1e216 5760 #define regPCIEMSIX_VECT133_MSG_DATA_BASE_IDX 5 5761 #define regPCIEMSIX_VECT133_CONTROL 0x1e217 5762 #define regPCIEMSIX_VECT133_CONTROL_BASE_IDX 5 5763 #define regPCIEMSIX_VECT134_ADDR_LO 0x1e218 5764 #define regPCIEMSIX_VECT134_ADDR_LO_BASE_IDX 5 5765 #define regPCIEMSIX_VECT134_ADDR_HI 0x1e219 5766 #define regPCIEMSIX_VECT134_ADDR_HI_BASE_IDX 5 5767 #define regPCIEMSIX_VECT134_MSG_DATA 0x1e21a 5768 #define regPCIEMSIX_VECT134_MSG_DATA_BASE_IDX 5 5769 #define regPCIEMSIX_VECT134_CONTROL 0x1e21b 5770 #define regPCIEMSIX_VECT134_CONTROL_BASE_IDX 5 5771 #define regPCIEMSIX_VECT135_ADDR_LO 0x1e21c 5772 #define regPCIEMSIX_VECT135_ADDR_LO_BASE_IDX 5 5773 #define regPCIEMSIX_VECT135_ADDR_HI 0x1e21d 5774 #define regPCIEMSIX_VECT135_ADDR_HI_BASE_IDX 5 5775 #define regPCIEMSIX_VECT135_MSG_DATA 0x1e21e 5776 #define regPCIEMSIX_VECT135_MSG_DATA_BASE_IDX 5 5777 #define regPCIEMSIX_VECT135_CONTROL 0x1e21f 5778 #define regPCIEMSIX_VECT135_CONTROL_BASE_IDX 5 5779 #define regPCIEMSIX_VECT136_ADDR_LO 0x1e220 5780 #define regPCIEMSIX_VECT136_ADDR_LO_BASE_IDX 5 5781 #define regPCIEMSIX_VECT136_ADDR_HI 0x1e221 5782 #define regPCIEMSIX_VECT136_ADDR_HI_BASE_IDX 5 5783 #define regPCIEMSIX_VECT136_MSG_DATA 0x1e222 5784 #define regPCIEMSIX_VECT136_MSG_DATA_BASE_IDX 5 5785 #define regPCIEMSIX_VECT136_CONTROL 0x1e223 5786 #define regPCIEMSIX_VECT136_CONTROL_BASE_IDX 5 5787 #define regPCIEMSIX_VECT137_ADDR_LO 0x1e224 5788 #define regPCIEMSIX_VECT137_ADDR_LO_BASE_IDX 5 5789 #define regPCIEMSIX_VECT137_ADDR_HI 0x1e225 5790 #define regPCIEMSIX_VECT137_ADDR_HI_BASE_IDX 5 5791 #define regPCIEMSIX_VECT137_MSG_DATA 0x1e226 5792 #define regPCIEMSIX_VECT137_MSG_DATA_BASE_IDX 5 5793 #define regPCIEMSIX_VECT137_CONTROL 0x1e227 5794 #define regPCIEMSIX_VECT137_CONTROL_BASE_IDX 5 5795 #define regPCIEMSIX_VECT138_ADDR_LO 0x1e228 5796 #define regPCIEMSIX_VECT138_ADDR_LO_BASE_IDX 5 5797 #define regPCIEMSIX_VECT138_ADDR_HI 0x1e229 5798 #define regPCIEMSIX_VECT138_ADDR_HI_BASE_IDX 5 5799 #define regPCIEMSIX_VECT138_MSG_DATA 0x1e22a 5800 #define regPCIEMSIX_VECT138_MSG_DATA_BASE_IDX 5 5801 #define regPCIEMSIX_VECT138_CONTROL 0x1e22b 5802 #define regPCIEMSIX_VECT138_CONTROL_BASE_IDX 5 5803 #define regPCIEMSIX_VECT139_ADDR_LO 0x1e22c 5804 #define regPCIEMSIX_VECT139_ADDR_LO_BASE_IDX 5 5805 #define regPCIEMSIX_VECT139_ADDR_HI 0x1e22d 5806 #define regPCIEMSIX_VECT139_ADDR_HI_BASE_IDX 5 5807 #define regPCIEMSIX_VECT139_MSG_DATA 0x1e22e 5808 #define regPCIEMSIX_VECT139_MSG_DATA_BASE_IDX 5 5809 #define regPCIEMSIX_VECT139_CONTROL 0x1e22f 5810 #define regPCIEMSIX_VECT139_CONTROL_BASE_IDX 5 5811 #define regPCIEMSIX_VECT140_ADDR_LO 0x1e230 5812 #define regPCIEMSIX_VECT140_ADDR_LO_BASE_IDX 5 5813 #define regPCIEMSIX_VECT140_ADDR_HI 0x1e231 5814 #define regPCIEMSIX_VECT140_ADDR_HI_BASE_IDX 5 5815 #define regPCIEMSIX_VECT140_MSG_DATA 0x1e232 5816 #define regPCIEMSIX_VECT140_MSG_DATA_BASE_IDX 5 5817 #define regPCIEMSIX_VECT140_CONTROL 0x1e233 5818 #define regPCIEMSIX_VECT140_CONTROL_BASE_IDX 5 5819 #define regPCIEMSIX_VECT141_ADDR_LO 0x1e234 5820 #define regPCIEMSIX_VECT141_ADDR_LO_BASE_IDX 5 5821 #define regPCIEMSIX_VECT141_ADDR_HI 0x1e235 5822 #define regPCIEMSIX_VECT141_ADDR_HI_BASE_IDX 5 5823 #define regPCIEMSIX_VECT141_MSG_DATA 0x1e236 5824 #define regPCIEMSIX_VECT141_MSG_DATA_BASE_IDX 5 5825 #define regPCIEMSIX_VECT141_CONTROL 0x1e237 5826 #define regPCIEMSIX_VECT141_CONTROL_BASE_IDX 5 5827 #define regPCIEMSIX_VECT142_ADDR_LO 0x1e238 5828 #define regPCIEMSIX_VECT142_ADDR_LO_BASE_IDX 5 5829 #define regPCIEMSIX_VECT142_ADDR_HI 0x1e239 5830 #define regPCIEMSIX_VECT142_ADDR_HI_BASE_IDX 5 5831 #define regPCIEMSIX_VECT142_MSG_DATA 0x1e23a 5832 #define regPCIEMSIX_VECT142_MSG_DATA_BASE_IDX 5 5833 #define regPCIEMSIX_VECT142_CONTROL 0x1e23b 5834 #define regPCIEMSIX_VECT142_CONTROL_BASE_IDX 5 5835 #define regPCIEMSIX_VECT143_ADDR_LO 0x1e23c 5836 #define regPCIEMSIX_VECT143_ADDR_LO_BASE_IDX 5 5837 #define regPCIEMSIX_VECT143_ADDR_HI 0x1e23d 5838 #define regPCIEMSIX_VECT143_ADDR_HI_BASE_IDX 5 5839 #define regPCIEMSIX_VECT143_MSG_DATA 0x1e23e 5840 #define regPCIEMSIX_VECT143_MSG_DATA_BASE_IDX 5 5841 #define regPCIEMSIX_VECT143_CONTROL 0x1e23f 5842 #define regPCIEMSIX_VECT143_CONTROL_BASE_IDX 5 5843 #define regPCIEMSIX_VECT144_ADDR_LO 0x1e240 5844 #define regPCIEMSIX_VECT144_ADDR_LO_BASE_IDX 5 5845 #define regPCIEMSIX_VECT144_ADDR_HI 0x1e241 5846 #define regPCIEMSIX_VECT144_ADDR_HI_BASE_IDX 5 5847 #define regPCIEMSIX_VECT144_MSG_DATA 0x1e242 5848 #define regPCIEMSIX_VECT144_MSG_DATA_BASE_IDX 5 5849 #define regPCIEMSIX_VECT144_CONTROL 0x1e243 5850 #define regPCIEMSIX_VECT144_CONTROL_BASE_IDX 5 5851 #define regPCIEMSIX_VECT145_ADDR_LO 0x1e244 5852 #define regPCIEMSIX_VECT145_ADDR_LO_BASE_IDX 5 5853 #define regPCIEMSIX_VECT145_ADDR_HI 0x1e245 5854 #define regPCIEMSIX_VECT145_ADDR_HI_BASE_IDX 5 5855 #define regPCIEMSIX_VECT145_MSG_DATA 0x1e246 5856 #define regPCIEMSIX_VECT145_MSG_DATA_BASE_IDX 5 5857 #define regPCIEMSIX_VECT145_CONTROL 0x1e247 5858 #define regPCIEMSIX_VECT145_CONTROL_BASE_IDX 5 5859 #define regPCIEMSIX_VECT146_ADDR_LO 0x1e248 5860 #define regPCIEMSIX_VECT146_ADDR_LO_BASE_IDX 5 5861 #define regPCIEMSIX_VECT146_ADDR_HI 0x1e249 5862 #define regPCIEMSIX_VECT146_ADDR_HI_BASE_IDX 5 5863 #define regPCIEMSIX_VECT146_MSG_DATA 0x1e24a 5864 #define regPCIEMSIX_VECT146_MSG_DATA_BASE_IDX 5 5865 #define regPCIEMSIX_VECT146_CONTROL 0x1e24b 5866 #define regPCIEMSIX_VECT146_CONTROL_BASE_IDX 5 5867 #define regPCIEMSIX_VECT147_ADDR_LO 0x1e24c 5868 #define regPCIEMSIX_VECT147_ADDR_LO_BASE_IDX 5 5869 #define regPCIEMSIX_VECT147_ADDR_HI 0x1e24d 5870 #define regPCIEMSIX_VECT147_ADDR_HI_BASE_IDX 5 5871 #define regPCIEMSIX_VECT147_MSG_DATA 0x1e24e 5872 #define regPCIEMSIX_VECT147_MSG_DATA_BASE_IDX 5 5873 #define regPCIEMSIX_VECT147_CONTROL 0x1e24f 5874 #define regPCIEMSIX_VECT147_CONTROL_BASE_IDX 5 5875 #define regPCIEMSIX_VECT148_ADDR_LO 0x1e250 5876 #define regPCIEMSIX_VECT148_ADDR_LO_BASE_IDX 5 5877 #define regPCIEMSIX_VECT148_ADDR_HI 0x1e251 5878 #define regPCIEMSIX_VECT148_ADDR_HI_BASE_IDX 5 5879 #define regPCIEMSIX_VECT148_MSG_DATA 0x1e252 5880 #define regPCIEMSIX_VECT148_MSG_DATA_BASE_IDX 5 5881 #define regPCIEMSIX_VECT148_CONTROL 0x1e253 5882 #define regPCIEMSIX_VECT148_CONTROL_BASE_IDX 5 5883 #define regPCIEMSIX_VECT149_ADDR_LO 0x1e254 5884 #define regPCIEMSIX_VECT149_ADDR_LO_BASE_IDX 5 5885 #define regPCIEMSIX_VECT149_ADDR_HI 0x1e255 5886 #define regPCIEMSIX_VECT149_ADDR_HI_BASE_IDX 5 5887 #define regPCIEMSIX_VECT149_MSG_DATA 0x1e256 5888 #define regPCIEMSIX_VECT149_MSG_DATA_BASE_IDX 5 5889 #define regPCIEMSIX_VECT149_CONTROL 0x1e257 5890 #define regPCIEMSIX_VECT149_CONTROL_BASE_IDX 5 5891 #define regPCIEMSIX_VECT150_ADDR_LO 0x1e258 5892 #define regPCIEMSIX_VECT150_ADDR_LO_BASE_IDX 5 5893 #define regPCIEMSIX_VECT150_ADDR_HI 0x1e259 5894 #define regPCIEMSIX_VECT150_ADDR_HI_BASE_IDX 5 5895 #define regPCIEMSIX_VECT150_MSG_DATA 0x1e25a 5896 #define regPCIEMSIX_VECT150_MSG_DATA_BASE_IDX 5 5897 #define regPCIEMSIX_VECT150_CONTROL 0x1e25b 5898 #define regPCIEMSIX_VECT150_CONTROL_BASE_IDX 5 5899 #define regPCIEMSIX_VECT151_ADDR_LO 0x1e25c 5900 #define regPCIEMSIX_VECT151_ADDR_LO_BASE_IDX 5 5901 #define regPCIEMSIX_VECT151_ADDR_HI 0x1e25d 5902 #define regPCIEMSIX_VECT151_ADDR_HI_BASE_IDX 5 5903 #define regPCIEMSIX_VECT151_MSG_DATA 0x1e25e 5904 #define regPCIEMSIX_VECT151_MSG_DATA_BASE_IDX 5 5905 #define regPCIEMSIX_VECT151_CONTROL 0x1e25f 5906 #define regPCIEMSIX_VECT151_CONTROL_BASE_IDX 5 5907 #define regPCIEMSIX_VECT152_ADDR_LO 0x1e260 5908 #define regPCIEMSIX_VECT152_ADDR_LO_BASE_IDX 5 5909 #define regPCIEMSIX_VECT152_ADDR_HI 0x1e261 5910 #define regPCIEMSIX_VECT152_ADDR_HI_BASE_IDX 5 5911 #define regPCIEMSIX_VECT152_MSG_DATA 0x1e262 5912 #define regPCIEMSIX_VECT152_MSG_DATA_BASE_IDX 5 5913 #define regPCIEMSIX_VECT152_CONTROL 0x1e263 5914 #define regPCIEMSIX_VECT152_CONTROL_BASE_IDX 5 5915 #define regPCIEMSIX_VECT153_ADDR_LO 0x1e264 5916 #define regPCIEMSIX_VECT153_ADDR_LO_BASE_IDX 5 5917 #define regPCIEMSIX_VECT153_ADDR_HI 0x1e265 5918 #define regPCIEMSIX_VECT153_ADDR_HI_BASE_IDX 5 5919 #define regPCIEMSIX_VECT153_MSG_DATA 0x1e266 5920 #define regPCIEMSIX_VECT153_MSG_DATA_BASE_IDX 5 5921 #define regPCIEMSIX_VECT153_CONTROL 0x1e267 5922 #define regPCIEMSIX_VECT153_CONTROL_BASE_IDX 5 5923 #define regPCIEMSIX_VECT154_ADDR_LO 0x1e268 5924 #define regPCIEMSIX_VECT154_ADDR_LO_BASE_IDX 5 5925 #define regPCIEMSIX_VECT154_ADDR_HI 0x1e269 5926 #define regPCIEMSIX_VECT154_ADDR_HI_BASE_IDX 5 5927 #define regPCIEMSIX_VECT154_MSG_DATA 0x1e26a 5928 #define regPCIEMSIX_VECT154_MSG_DATA_BASE_IDX 5 5929 #define regPCIEMSIX_VECT154_CONTROL 0x1e26b 5930 #define regPCIEMSIX_VECT154_CONTROL_BASE_IDX 5 5931 #define regPCIEMSIX_VECT155_ADDR_LO 0x1e26c 5932 #define regPCIEMSIX_VECT155_ADDR_LO_BASE_IDX 5 5933 #define regPCIEMSIX_VECT155_ADDR_HI 0x1e26d 5934 #define regPCIEMSIX_VECT155_ADDR_HI_BASE_IDX 5 5935 #define regPCIEMSIX_VECT155_MSG_DATA 0x1e26e 5936 #define regPCIEMSIX_VECT155_MSG_DATA_BASE_IDX 5 5937 #define regPCIEMSIX_VECT155_CONTROL 0x1e26f 5938 #define regPCIEMSIX_VECT155_CONTROL_BASE_IDX 5 5939 #define regPCIEMSIX_VECT156_ADDR_LO 0x1e270 5940 #define regPCIEMSIX_VECT156_ADDR_LO_BASE_IDX 5 5941 #define regPCIEMSIX_VECT156_ADDR_HI 0x1e271 5942 #define regPCIEMSIX_VECT156_ADDR_HI_BASE_IDX 5 5943 #define regPCIEMSIX_VECT156_MSG_DATA 0x1e272 5944 #define regPCIEMSIX_VECT156_MSG_DATA_BASE_IDX 5 5945 #define regPCIEMSIX_VECT156_CONTROL 0x1e273 5946 #define regPCIEMSIX_VECT156_CONTROL_BASE_IDX 5 5947 #define regPCIEMSIX_VECT157_ADDR_LO 0x1e274 5948 #define regPCIEMSIX_VECT157_ADDR_LO_BASE_IDX 5 5949 #define regPCIEMSIX_VECT157_ADDR_HI 0x1e275 5950 #define regPCIEMSIX_VECT157_ADDR_HI_BASE_IDX 5 5951 #define regPCIEMSIX_VECT157_MSG_DATA 0x1e276 5952 #define regPCIEMSIX_VECT157_MSG_DATA_BASE_IDX 5 5953 #define regPCIEMSIX_VECT157_CONTROL 0x1e277 5954 #define regPCIEMSIX_VECT157_CONTROL_BASE_IDX 5 5955 #define regPCIEMSIX_VECT158_ADDR_LO 0x1e278 5956 #define regPCIEMSIX_VECT158_ADDR_LO_BASE_IDX 5 5957 #define regPCIEMSIX_VECT158_ADDR_HI 0x1e279 5958 #define regPCIEMSIX_VECT158_ADDR_HI_BASE_IDX 5 5959 #define regPCIEMSIX_VECT158_MSG_DATA 0x1e27a 5960 #define regPCIEMSIX_VECT158_MSG_DATA_BASE_IDX 5 5961 #define regPCIEMSIX_VECT158_CONTROL 0x1e27b 5962 #define regPCIEMSIX_VECT158_CONTROL_BASE_IDX 5 5963 #define regPCIEMSIX_VECT159_ADDR_LO 0x1e27c 5964 #define regPCIEMSIX_VECT159_ADDR_LO_BASE_IDX 5 5965 #define regPCIEMSIX_VECT159_ADDR_HI 0x1e27d 5966 #define regPCIEMSIX_VECT159_ADDR_HI_BASE_IDX 5 5967 #define regPCIEMSIX_VECT159_MSG_DATA 0x1e27e 5968 #define regPCIEMSIX_VECT159_MSG_DATA_BASE_IDX 5 5969 #define regPCIEMSIX_VECT159_CONTROL 0x1e27f 5970 #define regPCIEMSIX_VECT159_CONTROL_BASE_IDX 5 5971 #define regPCIEMSIX_VECT160_ADDR_LO 0x1e280 5972 #define regPCIEMSIX_VECT160_ADDR_LO_BASE_IDX 5 5973 #define regPCIEMSIX_VECT160_ADDR_HI 0x1e281 5974 #define regPCIEMSIX_VECT160_ADDR_HI_BASE_IDX 5 5975 #define regPCIEMSIX_VECT160_MSG_DATA 0x1e282 5976 #define regPCIEMSIX_VECT160_MSG_DATA_BASE_IDX 5 5977 #define regPCIEMSIX_VECT160_CONTROL 0x1e283 5978 #define regPCIEMSIX_VECT160_CONTROL_BASE_IDX 5 5979 #define regPCIEMSIX_VECT161_ADDR_LO 0x1e284 5980 #define regPCIEMSIX_VECT161_ADDR_LO_BASE_IDX 5 5981 #define regPCIEMSIX_VECT161_ADDR_HI 0x1e285 5982 #define regPCIEMSIX_VECT161_ADDR_HI_BASE_IDX 5 5983 #define regPCIEMSIX_VECT161_MSG_DATA 0x1e286 5984 #define regPCIEMSIX_VECT161_MSG_DATA_BASE_IDX 5 5985 #define regPCIEMSIX_VECT161_CONTROL 0x1e287 5986 #define regPCIEMSIX_VECT161_CONTROL_BASE_IDX 5 5987 #define regPCIEMSIX_VECT162_ADDR_LO 0x1e288 5988 #define regPCIEMSIX_VECT162_ADDR_LO_BASE_IDX 5 5989 #define regPCIEMSIX_VECT162_ADDR_HI 0x1e289 5990 #define regPCIEMSIX_VECT162_ADDR_HI_BASE_IDX 5 5991 #define regPCIEMSIX_VECT162_MSG_DATA 0x1e28a 5992 #define regPCIEMSIX_VECT162_MSG_DATA_BASE_IDX 5 5993 #define regPCIEMSIX_VECT162_CONTROL 0x1e28b 5994 #define regPCIEMSIX_VECT162_CONTROL_BASE_IDX 5 5995 #define regPCIEMSIX_VECT163_ADDR_LO 0x1e28c 5996 #define regPCIEMSIX_VECT163_ADDR_LO_BASE_IDX 5 5997 #define regPCIEMSIX_VECT163_ADDR_HI 0x1e28d 5998 #define regPCIEMSIX_VECT163_ADDR_HI_BASE_IDX 5 5999 #define regPCIEMSIX_VECT163_MSG_DATA 0x1e28e 6000 #define regPCIEMSIX_VECT163_MSG_DATA_BASE_IDX 5 6001 #define regPCIEMSIX_VECT163_CONTROL 0x1e28f 6002 #define regPCIEMSIX_VECT163_CONTROL_BASE_IDX 5 6003 #define regPCIEMSIX_VECT164_ADDR_LO 0x1e290 6004 #define regPCIEMSIX_VECT164_ADDR_LO_BASE_IDX 5 6005 #define regPCIEMSIX_VECT164_ADDR_HI 0x1e291 6006 #define regPCIEMSIX_VECT164_ADDR_HI_BASE_IDX 5 6007 #define regPCIEMSIX_VECT164_MSG_DATA 0x1e292 6008 #define regPCIEMSIX_VECT164_MSG_DATA_BASE_IDX 5 6009 #define regPCIEMSIX_VECT164_CONTROL 0x1e293 6010 #define regPCIEMSIX_VECT164_CONTROL_BASE_IDX 5 6011 #define regPCIEMSIX_VECT165_ADDR_LO 0x1e294 6012 #define regPCIEMSIX_VECT165_ADDR_LO_BASE_IDX 5 6013 #define regPCIEMSIX_VECT165_ADDR_HI 0x1e295 6014 #define regPCIEMSIX_VECT165_ADDR_HI_BASE_IDX 5 6015 #define regPCIEMSIX_VECT165_MSG_DATA 0x1e296 6016 #define regPCIEMSIX_VECT165_MSG_DATA_BASE_IDX 5 6017 #define regPCIEMSIX_VECT165_CONTROL 0x1e297 6018 #define regPCIEMSIX_VECT165_CONTROL_BASE_IDX 5 6019 #define regPCIEMSIX_VECT166_ADDR_LO 0x1e298 6020 #define regPCIEMSIX_VECT166_ADDR_LO_BASE_IDX 5 6021 #define regPCIEMSIX_VECT166_ADDR_HI 0x1e299 6022 #define regPCIEMSIX_VECT166_ADDR_HI_BASE_IDX 5 6023 #define regPCIEMSIX_VECT166_MSG_DATA 0x1e29a 6024 #define regPCIEMSIX_VECT166_MSG_DATA_BASE_IDX 5 6025 #define regPCIEMSIX_VECT166_CONTROL 0x1e29b 6026 #define regPCIEMSIX_VECT166_CONTROL_BASE_IDX 5 6027 #define regPCIEMSIX_VECT167_ADDR_LO 0x1e29c 6028 #define regPCIEMSIX_VECT167_ADDR_LO_BASE_IDX 5 6029 #define regPCIEMSIX_VECT167_ADDR_HI 0x1e29d 6030 #define regPCIEMSIX_VECT167_ADDR_HI_BASE_IDX 5 6031 #define regPCIEMSIX_VECT167_MSG_DATA 0x1e29e 6032 #define regPCIEMSIX_VECT167_MSG_DATA_BASE_IDX 5 6033 #define regPCIEMSIX_VECT167_CONTROL 0x1e29f 6034 #define regPCIEMSIX_VECT167_CONTROL_BASE_IDX 5 6035 #define regPCIEMSIX_VECT168_ADDR_LO 0x1e2a0 6036 #define regPCIEMSIX_VECT168_ADDR_LO_BASE_IDX 5 6037 #define regPCIEMSIX_VECT168_ADDR_HI 0x1e2a1 6038 #define regPCIEMSIX_VECT168_ADDR_HI_BASE_IDX 5 6039 #define regPCIEMSIX_VECT168_MSG_DATA 0x1e2a2 6040 #define regPCIEMSIX_VECT168_MSG_DATA_BASE_IDX 5 6041 #define regPCIEMSIX_VECT168_CONTROL 0x1e2a3 6042 #define regPCIEMSIX_VECT168_CONTROL_BASE_IDX 5 6043 #define regPCIEMSIX_VECT169_ADDR_LO 0x1e2a4 6044 #define regPCIEMSIX_VECT169_ADDR_LO_BASE_IDX 5 6045 #define regPCIEMSIX_VECT169_ADDR_HI 0x1e2a5 6046 #define regPCIEMSIX_VECT169_ADDR_HI_BASE_IDX 5 6047 #define regPCIEMSIX_VECT169_MSG_DATA 0x1e2a6 6048 #define regPCIEMSIX_VECT169_MSG_DATA_BASE_IDX 5 6049 #define regPCIEMSIX_VECT169_CONTROL 0x1e2a7 6050 #define regPCIEMSIX_VECT169_CONTROL_BASE_IDX 5 6051 #define regPCIEMSIX_VECT170_ADDR_LO 0x1e2a8 6052 #define regPCIEMSIX_VECT170_ADDR_LO_BASE_IDX 5 6053 #define regPCIEMSIX_VECT170_ADDR_HI 0x1e2a9 6054 #define regPCIEMSIX_VECT170_ADDR_HI_BASE_IDX 5 6055 #define regPCIEMSIX_VECT170_MSG_DATA 0x1e2aa 6056 #define regPCIEMSIX_VECT170_MSG_DATA_BASE_IDX 5 6057 #define regPCIEMSIX_VECT170_CONTROL 0x1e2ab 6058 #define regPCIEMSIX_VECT170_CONTROL_BASE_IDX 5 6059 #define regPCIEMSIX_VECT171_ADDR_LO 0x1e2ac 6060 #define regPCIEMSIX_VECT171_ADDR_LO_BASE_IDX 5 6061 #define regPCIEMSIX_VECT171_ADDR_HI 0x1e2ad 6062 #define regPCIEMSIX_VECT171_ADDR_HI_BASE_IDX 5 6063 #define regPCIEMSIX_VECT171_MSG_DATA 0x1e2ae 6064 #define regPCIEMSIX_VECT171_MSG_DATA_BASE_IDX 5 6065 #define regPCIEMSIX_VECT171_CONTROL 0x1e2af 6066 #define regPCIEMSIX_VECT171_CONTROL_BASE_IDX 5 6067 #define regPCIEMSIX_VECT172_ADDR_LO 0x1e2b0 6068 #define regPCIEMSIX_VECT172_ADDR_LO_BASE_IDX 5 6069 #define regPCIEMSIX_VECT172_ADDR_HI 0x1e2b1 6070 #define regPCIEMSIX_VECT172_ADDR_HI_BASE_IDX 5 6071 #define regPCIEMSIX_VECT172_MSG_DATA 0x1e2b2 6072 #define regPCIEMSIX_VECT172_MSG_DATA_BASE_IDX 5 6073 #define regPCIEMSIX_VECT172_CONTROL 0x1e2b3 6074 #define regPCIEMSIX_VECT172_CONTROL_BASE_IDX 5 6075 #define regPCIEMSIX_VECT173_ADDR_LO 0x1e2b4 6076 #define regPCIEMSIX_VECT173_ADDR_LO_BASE_IDX 5 6077 #define regPCIEMSIX_VECT173_ADDR_HI 0x1e2b5 6078 #define regPCIEMSIX_VECT173_ADDR_HI_BASE_IDX 5 6079 #define regPCIEMSIX_VECT173_MSG_DATA 0x1e2b6 6080 #define regPCIEMSIX_VECT173_MSG_DATA_BASE_IDX 5 6081 #define regPCIEMSIX_VECT173_CONTROL 0x1e2b7 6082 #define regPCIEMSIX_VECT173_CONTROL_BASE_IDX 5 6083 #define regPCIEMSIX_VECT174_ADDR_LO 0x1e2b8 6084 #define regPCIEMSIX_VECT174_ADDR_LO_BASE_IDX 5 6085 #define regPCIEMSIX_VECT174_ADDR_HI 0x1e2b9 6086 #define regPCIEMSIX_VECT174_ADDR_HI_BASE_IDX 5 6087 #define regPCIEMSIX_VECT174_MSG_DATA 0x1e2ba 6088 #define regPCIEMSIX_VECT174_MSG_DATA_BASE_IDX 5 6089 #define regPCIEMSIX_VECT174_CONTROL 0x1e2bb 6090 #define regPCIEMSIX_VECT174_CONTROL_BASE_IDX 5 6091 #define regPCIEMSIX_VECT175_ADDR_LO 0x1e2bc 6092 #define regPCIEMSIX_VECT175_ADDR_LO_BASE_IDX 5 6093 #define regPCIEMSIX_VECT175_ADDR_HI 0x1e2bd 6094 #define regPCIEMSIX_VECT175_ADDR_HI_BASE_IDX 5 6095 #define regPCIEMSIX_VECT175_MSG_DATA 0x1e2be 6096 #define regPCIEMSIX_VECT175_MSG_DATA_BASE_IDX 5 6097 #define regPCIEMSIX_VECT175_CONTROL 0x1e2bf 6098 #define regPCIEMSIX_VECT175_CONTROL_BASE_IDX 5 6099 #define regPCIEMSIX_VECT176_ADDR_LO 0x1e2c0 6100 #define regPCIEMSIX_VECT176_ADDR_LO_BASE_IDX 5 6101 #define regPCIEMSIX_VECT176_ADDR_HI 0x1e2c1 6102 #define regPCIEMSIX_VECT176_ADDR_HI_BASE_IDX 5 6103 #define regPCIEMSIX_VECT176_MSG_DATA 0x1e2c2 6104 #define regPCIEMSIX_VECT176_MSG_DATA_BASE_IDX 5 6105 #define regPCIEMSIX_VECT176_CONTROL 0x1e2c3 6106 #define regPCIEMSIX_VECT176_CONTROL_BASE_IDX 5 6107 #define regPCIEMSIX_VECT177_ADDR_LO 0x1e2c4 6108 #define regPCIEMSIX_VECT177_ADDR_LO_BASE_IDX 5 6109 #define regPCIEMSIX_VECT177_ADDR_HI 0x1e2c5 6110 #define regPCIEMSIX_VECT177_ADDR_HI_BASE_IDX 5 6111 #define regPCIEMSIX_VECT177_MSG_DATA 0x1e2c6 6112 #define regPCIEMSIX_VECT177_MSG_DATA_BASE_IDX 5 6113 #define regPCIEMSIX_VECT177_CONTROL 0x1e2c7 6114 #define regPCIEMSIX_VECT177_CONTROL_BASE_IDX 5 6115 #define regPCIEMSIX_VECT178_ADDR_LO 0x1e2c8 6116 #define regPCIEMSIX_VECT178_ADDR_LO_BASE_IDX 5 6117 #define regPCIEMSIX_VECT178_ADDR_HI 0x1e2c9 6118 #define regPCIEMSIX_VECT178_ADDR_HI_BASE_IDX 5 6119 #define regPCIEMSIX_VECT178_MSG_DATA 0x1e2ca 6120 #define regPCIEMSIX_VECT178_MSG_DATA_BASE_IDX 5 6121 #define regPCIEMSIX_VECT178_CONTROL 0x1e2cb 6122 #define regPCIEMSIX_VECT178_CONTROL_BASE_IDX 5 6123 #define regPCIEMSIX_VECT179_ADDR_LO 0x1e2cc 6124 #define regPCIEMSIX_VECT179_ADDR_LO_BASE_IDX 5 6125 #define regPCIEMSIX_VECT179_ADDR_HI 0x1e2cd 6126 #define regPCIEMSIX_VECT179_ADDR_HI_BASE_IDX 5 6127 #define regPCIEMSIX_VECT179_MSG_DATA 0x1e2ce 6128 #define regPCIEMSIX_VECT179_MSG_DATA_BASE_IDX 5 6129 #define regPCIEMSIX_VECT179_CONTROL 0x1e2cf 6130 #define regPCIEMSIX_VECT179_CONTROL_BASE_IDX 5 6131 #define regPCIEMSIX_VECT180_ADDR_LO 0x1e2d0 6132 #define regPCIEMSIX_VECT180_ADDR_LO_BASE_IDX 5 6133 #define regPCIEMSIX_VECT180_ADDR_HI 0x1e2d1 6134 #define regPCIEMSIX_VECT180_ADDR_HI_BASE_IDX 5 6135 #define regPCIEMSIX_VECT180_MSG_DATA 0x1e2d2 6136 #define regPCIEMSIX_VECT180_MSG_DATA_BASE_IDX 5 6137 #define regPCIEMSIX_VECT180_CONTROL 0x1e2d3 6138 #define regPCIEMSIX_VECT180_CONTROL_BASE_IDX 5 6139 #define regPCIEMSIX_VECT181_ADDR_LO 0x1e2d4 6140 #define regPCIEMSIX_VECT181_ADDR_LO_BASE_IDX 5 6141 #define regPCIEMSIX_VECT181_ADDR_HI 0x1e2d5 6142 #define regPCIEMSIX_VECT181_ADDR_HI_BASE_IDX 5 6143 #define regPCIEMSIX_VECT181_MSG_DATA 0x1e2d6 6144 #define regPCIEMSIX_VECT181_MSG_DATA_BASE_IDX 5 6145 #define regPCIEMSIX_VECT181_CONTROL 0x1e2d7 6146 #define regPCIEMSIX_VECT181_CONTROL_BASE_IDX 5 6147 #define regPCIEMSIX_VECT182_ADDR_LO 0x1e2d8 6148 #define regPCIEMSIX_VECT182_ADDR_LO_BASE_IDX 5 6149 #define regPCIEMSIX_VECT182_ADDR_HI 0x1e2d9 6150 #define regPCIEMSIX_VECT182_ADDR_HI_BASE_IDX 5 6151 #define regPCIEMSIX_VECT182_MSG_DATA 0x1e2da 6152 #define regPCIEMSIX_VECT182_MSG_DATA_BASE_IDX 5 6153 #define regPCIEMSIX_VECT182_CONTROL 0x1e2db 6154 #define regPCIEMSIX_VECT182_CONTROL_BASE_IDX 5 6155 #define regPCIEMSIX_VECT183_ADDR_LO 0x1e2dc 6156 #define regPCIEMSIX_VECT183_ADDR_LO_BASE_IDX 5 6157 #define regPCIEMSIX_VECT183_ADDR_HI 0x1e2dd 6158 #define regPCIEMSIX_VECT183_ADDR_HI_BASE_IDX 5 6159 #define regPCIEMSIX_VECT183_MSG_DATA 0x1e2de 6160 #define regPCIEMSIX_VECT183_MSG_DATA_BASE_IDX 5 6161 #define regPCIEMSIX_VECT183_CONTROL 0x1e2df 6162 #define regPCIEMSIX_VECT183_CONTROL_BASE_IDX 5 6163 #define regPCIEMSIX_VECT184_ADDR_LO 0x1e2e0 6164 #define regPCIEMSIX_VECT184_ADDR_LO_BASE_IDX 5 6165 #define regPCIEMSIX_VECT184_ADDR_HI 0x1e2e1 6166 #define regPCIEMSIX_VECT184_ADDR_HI_BASE_IDX 5 6167 #define regPCIEMSIX_VECT184_MSG_DATA 0x1e2e2 6168 #define regPCIEMSIX_VECT184_MSG_DATA_BASE_IDX 5 6169 #define regPCIEMSIX_VECT184_CONTROL 0x1e2e3 6170 #define regPCIEMSIX_VECT184_CONTROL_BASE_IDX 5 6171 #define regPCIEMSIX_VECT185_ADDR_LO 0x1e2e4 6172 #define regPCIEMSIX_VECT185_ADDR_LO_BASE_IDX 5 6173 #define regPCIEMSIX_VECT185_ADDR_HI 0x1e2e5 6174 #define regPCIEMSIX_VECT185_ADDR_HI_BASE_IDX 5 6175 #define regPCIEMSIX_VECT185_MSG_DATA 0x1e2e6 6176 #define regPCIEMSIX_VECT185_MSG_DATA_BASE_IDX 5 6177 #define regPCIEMSIX_VECT185_CONTROL 0x1e2e7 6178 #define regPCIEMSIX_VECT185_CONTROL_BASE_IDX 5 6179 #define regPCIEMSIX_VECT186_ADDR_LO 0x1e2e8 6180 #define regPCIEMSIX_VECT186_ADDR_LO_BASE_IDX 5 6181 #define regPCIEMSIX_VECT186_ADDR_HI 0x1e2e9 6182 #define regPCIEMSIX_VECT186_ADDR_HI_BASE_IDX 5 6183 #define regPCIEMSIX_VECT186_MSG_DATA 0x1e2ea 6184 #define regPCIEMSIX_VECT186_MSG_DATA_BASE_IDX 5 6185 #define regPCIEMSIX_VECT186_CONTROL 0x1e2eb 6186 #define regPCIEMSIX_VECT186_CONTROL_BASE_IDX 5 6187 #define regPCIEMSIX_VECT187_ADDR_LO 0x1e2ec 6188 #define regPCIEMSIX_VECT187_ADDR_LO_BASE_IDX 5 6189 #define regPCIEMSIX_VECT187_ADDR_HI 0x1e2ed 6190 #define regPCIEMSIX_VECT187_ADDR_HI_BASE_IDX 5 6191 #define regPCIEMSIX_VECT187_MSG_DATA 0x1e2ee 6192 #define regPCIEMSIX_VECT187_MSG_DATA_BASE_IDX 5 6193 #define regPCIEMSIX_VECT187_CONTROL 0x1e2ef 6194 #define regPCIEMSIX_VECT187_CONTROL_BASE_IDX 5 6195 #define regPCIEMSIX_VECT188_ADDR_LO 0x1e2f0 6196 #define regPCIEMSIX_VECT188_ADDR_LO_BASE_IDX 5 6197 #define regPCIEMSIX_VECT188_ADDR_HI 0x1e2f1 6198 #define regPCIEMSIX_VECT188_ADDR_HI_BASE_IDX 5 6199 #define regPCIEMSIX_VECT188_MSG_DATA 0x1e2f2 6200 #define regPCIEMSIX_VECT188_MSG_DATA_BASE_IDX 5 6201 #define regPCIEMSIX_VECT188_CONTROL 0x1e2f3 6202 #define regPCIEMSIX_VECT188_CONTROL_BASE_IDX 5 6203 #define regPCIEMSIX_VECT189_ADDR_LO 0x1e2f4 6204 #define regPCIEMSIX_VECT189_ADDR_LO_BASE_IDX 5 6205 #define regPCIEMSIX_VECT189_ADDR_HI 0x1e2f5 6206 #define regPCIEMSIX_VECT189_ADDR_HI_BASE_IDX 5 6207 #define regPCIEMSIX_VECT189_MSG_DATA 0x1e2f6 6208 #define regPCIEMSIX_VECT189_MSG_DATA_BASE_IDX 5 6209 #define regPCIEMSIX_VECT189_CONTROL 0x1e2f7 6210 #define regPCIEMSIX_VECT189_CONTROL_BASE_IDX 5 6211 #define regPCIEMSIX_VECT190_ADDR_LO 0x1e2f8 6212 #define regPCIEMSIX_VECT190_ADDR_LO_BASE_IDX 5 6213 #define regPCIEMSIX_VECT190_ADDR_HI 0x1e2f9 6214 #define regPCIEMSIX_VECT190_ADDR_HI_BASE_IDX 5 6215 #define regPCIEMSIX_VECT190_MSG_DATA 0x1e2fa 6216 #define regPCIEMSIX_VECT190_MSG_DATA_BASE_IDX 5 6217 #define regPCIEMSIX_VECT190_CONTROL 0x1e2fb 6218 #define regPCIEMSIX_VECT190_CONTROL_BASE_IDX 5 6219 #define regPCIEMSIX_VECT191_ADDR_LO 0x1e2fc 6220 #define regPCIEMSIX_VECT191_ADDR_LO_BASE_IDX 5 6221 #define regPCIEMSIX_VECT191_ADDR_HI 0x1e2fd 6222 #define regPCIEMSIX_VECT191_ADDR_HI_BASE_IDX 5 6223 #define regPCIEMSIX_VECT191_MSG_DATA 0x1e2fe 6224 #define regPCIEMSIX_VECT191_MSG_DATA_BASE_IDX 5 6225 #define regPCIEMSIX_VECT191_CONTROL 0x1e2ff 6226 #define regPCIEMSIX_VECT191_CONTROL_BASE_IDX 5 6227 #define regPCIEMSIX_VECT192_ADDR_LO 0x1e300 6228 #define regPCIEMSIX_VECT192_ADDR_LO_BASE_IDX 5 6229 #define regPCIEMSIX_VECT192_ADDR_HI 0x1e301 6230 #define regPCIEMSIX_VECT192_ADDR_HI_BASE_IDX 5 6231 #define regPCIEMSIX_VECT192_MSG_DATA 0x1e302 6232 #define regPCIEMSIX_VECT192_MSG_DATA_BASE_IDX 5 6233 #define regPCIEMSIX_VECT192_CONTROL 0x1e303 6234 #define regPCIEMSIX_VECT192_CONTROL_BASE_IDX 5 6235 #define regPCIEMSIX_VECT193_ADDR_LO 0x1e304 6236 #define regPCIEMSIX_VECT193_ADDR_LO_BASE_IDX 5 6237 #define regPCIEMSIX_VECT193_ADDR_HI 0x1e305 6238 #define regPCIEMSIX_VECT193_ADDR_HI_BASE_IDX 5 6239 #define regPCIEMSIX_VECT193_MSG_DATA 0x1e306 6240 #define regPCIEMSIX_VECT193_MSG_DATA_BASE_IDX 5 6241 #define regPCIEMSIX_VECT193_CONTROL 0x1e307 6242 #define regPCIEMSIX_VECT193_CONTROL_BASE_IDX 5 6243 #define regPCIEMSIX_VECT194_ADDR_LO 0x1e308 6244 #define regPCIEMSIX_VECT194_ADDR_LO_BASE_IDX 5 6245 #define regPCIEMSIX_VECT194_ADDR_HI 0x1e309 6246 #define regPCIEMSIX_VECT194_ADDR_HI_BASE_IDX 5 6247 #define regPCIEMSIX_VECT194_MSG_DATA 0x1e30a 6248 #define regPCIEMSIX_VECT194_MSG_DATA_BASE_IDX 5 6249 #define regPCIEMSIX_VECT194_CONTROL 0x1e30b 6250 #define regPCIEMSIX_VECT194_CONTROL_BASE_IDX 5 6251 #define regPCIEMSIX_VECT195_ADDR_LO 0x1e30c 6252 #define regPCIEMSIX_VECT195_ADDR_LO_BASE_IDX 5 6253 #define regPCIEMSIX_VECT195_ADDR_HI 0x1e30d 6254 #define regPCIEMSIX_VECT195_ADDR_HI_BASE_IDX 5 6255 #define regPCIEMSIX_VECT195_MSG_DATA 0x1e30e 6256 #define regPCIEMSIX_VECT195_MSG_DATA_BASE_IDX 5 6257 #define regPCIEMSIX_VECT195_CONTROL 0x1e30f 6258 #define regPCIEMSIX_VECT195_CONTROL_BASE_IDX 5 6259 #define regPCIEMSIX_VECT196_ADDR_LO 0x1e310 6260 #define regPCIEMSIX_VECT196_ADDR_LO_BASE_IDX 5 6261 #define regPCIEMSIX_VECT196_ADDR_HI 0x1e311 6262 #define regPCIEMSIX_VECT196_ADDR_HI_BASE_IDX 5 6263 #define regPCIEMSIX_VECT196_MSG_DATA 0x1e312 6264 #define regPCIEMSIX_VECT196_MSG_DATA_BASE_IDX 5 6265 #define regPCIEMSIX_VECT196_CONTROL 0x1e313 6266 #define regPCIEMSIX_VECT196_CONTROL_BASE_IDX 5 6267 #define regPCIEMSIX_VECT197_ADDR_LO 0x1e314 6268 #define regPCIEMSIX_VECT197_ADDR_LO_BASE_IDX 5 6269 #define regPCIEMSIX_VECT197_ADDR_HI 0x1e315 6270 #define regPCIEMSIX_VECT197_ADDR_HI_BASE_IDX 5 6271 #define regPCIEMSIX_VECT197_MSG_DATA 0x1e316 6272 #define regPCIEMSIX_VECT197_MSG_DATA_BASE_IDX 5 6273 #define regPCIEMSIX_VECT197_CONTROL 0x1e317 6274 #define regPCIEMSIX_VECT197_CONTROL_BASE_IDX 5 6275 #define regPCIEMSIX_VECT198_ADDR_LO 0x1e318 6276 #define regPCIEMSIX_VECT198_ADDR_LO_BASE_IDX 5 6277 #define regPCIEMSIX_VECT198_ADDR_HI 0x1e319 6278 #define regPCIEMSIX_VECT198_ADDR_HI_BASE_IDX 5 6279 #define regPCIEMSIX_VECT198_MSG_DATA 0x1e31a 6280 #define regPCIEMSIX_VECT198_MSG_DATA_BASE_IDX 5 6281 #define regPCIEMSIX_VECT198_CONTROL 0x1e31b 6282 #define regPCIEMSIX_VECT198_CONTROL_BASE_IDX 5 6283 #define regPCIEMSIX_VECT199_ADDR_LO 0x1e31c 6284 #define regPCIEMSIX_VECT199_ADDR_LO_BASE_IDX 5 6285 #define regPCIEMSIX_VECT199_ADDR_HI 0x1e31d 6286 #define regPCIEMSIX_VECT199_ADDR_HI_BASE_IDX 5 6287 #define regPCIEMSIX_VECT199_MSG_DATA 0x1e31e 6288 #define regPCIEMSIX_VECT199_MSG_DATA_BASE_IDX 5 6289 #define regPCIEMSIX_VECT199_CONTROL 0x1e31f 6290 #define regPCIEMSIX_VECT199_CONTROL_BASE_IDX 5 6291 #define regPCIEMSIX_VECT200_ADDR_LO 0x1e320 6292 #define regPCIEMSIX_VECT200_ADDR_LO_BASE_IDX 5 6293 #define regPCIEMSIX_VECT200_ADDR_HI 0x1e321 6294 #define regPCIEMSIX_VECT200_ADDR_HI_BASE_IDX 5 6295 #define regPCIEMSIX_VECT200_MSG_DATA 0x1e322 6296 #define regPCIEMSIX_VECT200_MSG_DATA_BASE_IDX 5 6297 #define regPCIEMSIX_VECT200_CONTROL 0x1e323 6298 #define regPCIEMSIX_VECT200_CONTROL_BASE_IDX 5 6299 #define regPCIEMSIX_VECT201_ADDR_LO 0x1e324 6300 #define regPCIEMSIX_VECT201_ADDR_LO_BASE_IDX 5 6301 #define regPCIEMSIX_VECT201_ADDR_HI 0x1e325 6302 #define regPCIEMSIX_VECT201_ADDR_HI_BASE_IDX 5 6303 #define regPCIEMSIX_VECT201_MSG_DATA 0x1e326 6304 #define regPCIEMSIX_VECT201_MSG_DATA_BASE_IDX 5 6305 #define regPCIEMSIX_VECT201_CONTROL 0x1e327 6306 #define regPCIEMSIX_VECT201_CONTROL_BASE_IDX 5 6307 #define regPCIEMSIX_VECT202_ADDR_LO 0x1e328 6308 #define regPCIEMSIX_VECT202_ADDR_LO_BASE_IDX 5 6309 #define regPCIEMSIX_VECT202_ADDR_HI 0x1e329 6310 #define regPCIEMSIX_VECT202_ADDR_HI_BASE_IDX 5 6311 #define regPCIEMSIX_VECT202_MSG_DATA 0x1e32a 6312 #define regPCIEMSIX_VECT202_MSG_DATA_BASE_IDX 5 6313 #define regPCIEMSIX_VECT202_CONTROL 0x1e32b 6314 #define regPCIEMSIX_VECT202_CONTROL_BASE_IDX 5 6315 #define regPCIEMSIX_VECT203_ADDR_LO 0x1e32c 6316 #define regPCIEMSIX_VECT203_ADDR_LO_BASE_IDX 5 6317 #define regPCIEMSIX_VECT203_ADDR_HI 0x1e32d 6318 #define regPCIEMSIX_VECT203_ADDR_HI_BASE_IDX 5 6319 #define regPCIEMSIX_VECT203_MSG_DATA 0x1e32e 6320 #define regPCIEMSIX_VECT203_MSG_DATA_BASE_IDX 5 6321 #define regPCIEMSIX_VECT203_CONTROL 0x1e32f 6322 #define regPCIEMSIX_VECT203_CONTROL_BASE_IDX 5 6323 #define regPCIEMSIX_VECT204_ADDR_LO 0x1e330 6324 #define regPCIEMSIX_VECT204_ADDR_LO_BASE_IDX 5 6325 #define regPCIEMSIX_VECT204_ADDR_HI 0x1e331 6326 #define regPCIEMSIX_VECT204_ADDR_HI_BASE_IDX 5 6327 #define regPCIEMSIX_VECT204_MSG_DATA 0x1e332 6328 #define regPCIEMSIX_VECT204_MSG_DATA_BASE_IDX 5 6329 #define regPCIEMSIX_VECT204_CONTROL 0x1e333 6330 #define regPCIEMSIX_VECT204_CONTROL_BASE_IDX 5 6331 #define regPCIEMSIX_VECT205_ADDR_LO 0x1e334 6332 #define regPCIEMSIX_VECT205_ADDR_LO_BASE_IDX 5 6333 #define regPCIEMSIX_VECT205_ADDR_HI 0x1e335 6334 #define regPCIEMSIX_VECT205_ADDR_HI_BASE_IDX 5 6335 #define regPCIEMSIX_VECT205_MSG_DATA 0x1e336 6336 #define regPCIEMSIX_VECT205_MSG_DATA_BASE_IDX 5 6337 #define regPCIEMSIX_VECT205_CONTROL 0x1e337 6338 #define regPCIEMSIX_VECT205_CONTROL_BASE_IDX 5 6339 #define regPCIEMSIX_VECT206_ADDR_LO 0x1e338 6340 #define regPCIEMSIX_VECT206_ADDR_LO_BASE_IDX 5 6341 #define regPCIEMSIX_VECT206_ADDR_HI 0x1e339 6342 #define regPCIEMSIX_VECT206_ADDR_HI_BASE_IDX 5 6343 #define regPCIEMSIX_VECT206_MSG_DATA 0x1e33a 6344 #define regPCIEMSIX_VECT206_MSG_DATA_BASE_IDX 5 6345 #define regPCIEMSIX_VECT206_CONTROL 0x1e33b 6346 #define regPCIEMSIX_VECT206_CONTROL_BASE_IDX 5 6347 #define regPCIEMSIX_VECT207_ADDR_LO 0x1e33c 6348 #define regPCIEMSIX_VECT207_ADDR_LO_BASE_IDX 5 6349 #define regPCIEMSIX_VECT207_ADDR_HI 0x1e33d 6350 #define regPCIEMSIX_VECT207_ADDR_HI_BASE_IDX 5 6351 #define regPCIEMSIX_VECT207_MSG_DATA 0x1e33e 6352 #define regPCIEMSIX_VECT207_MSG_DATA_BASE_IDX 5 6353 #define regPCIEMSIX_VECT207_CONTROL 0x1e33f 6354 #define regPCIEMSIX_VECT207_CONTROL_BASE_IDX 5 6355 #define regPCIEMSIX_VECT208_ADDR_LO 0x1e340 6356 #define regPCIEMSIX_VECT208_ADDR_LO_BASE_IDX 5 6357 #define regPCIEMSIX_VECT208_ADDR_HI 0x1e341 6358 #define regPCIEMSIX_VECT208_ADDR_HI_BASE_IDX 5 6359 #define regPCIEMSIX_VECT208_MSG_DATA 0x1e342 6360 #define regPCIEMSIX_VECT208_MSG_DATA_BASE_IDX 5 6361 #define regPCIEMSIX_VECT208_CONTROL 0x1e343 6362 #define regPCIEMSIX_VECT208_CONTROL_BASE_IDX 5 6363 #define regPCIEMSIX_VECT209_ADDR_LO 0x1e344 6364 #define regPCIEMSIX_VECT209_ADDR_LO_BASE_IDX 5 6365 #define regPCIEMSIX_VECT209_ADDR_HI 0x1e345 6366 #define regPCIEMSIX_VECT209_ADDR_HI_BASE_IDX 5 6367 #define regPCIEMSIX_VECT209_MSG_DATA 0x1e346 6368 #define regPCIEMSIX_VECT209_MSG_DATA_BASE_IDX 5 6369 #define regPCIEMSIX_VECT209_CONTROL 0x1e347 6370 #define regPCIEMSIX_VECT209_CONTROL_BASE_IDX 5 6371 #define regPCIEMSIX_VECT210_ADDR_LO 0x1e348 6372 #define regPCIEMSIX_VECT210_ADDR_LO_BASE_IDX 5 6373 #define regPCIEMSIX_VECT210_ADDR_HI 0x1e349 6374 #define regPCIEMSIX_VECT210_ADDR_HI_BASE_IDX 5 6375 #define regPCIEMSIX_VECT210_MSG_DATA 0x1e34a 6376 #define regPCIEMSIX_VECT210_MSG_DATA_BASE_IDX 5 6377 #define regPCIEMSIX_VECT210_CONTROL 0x1e34b 6378 #define regPCIEMSIX_VECT210_CONTROL_BASE_IDX 5 6379 #define regPCIEMSIX_VECT211_ADDR_LO 0x1e34c 6380 #define regPCIEMSIX_VECT211_ADDR_LO_BASE_IDX 5 6381 #define regPCIEMSIX_VECT211_ADDR_HI 0x1e34d 6382 #define regPCIEMSIX_VECT211_ADDR_HI_BASE_IDX 5 6383 #define regPCIEMSIX_VECT211_MSG_DATA 0x1e34e 6384 #define regPCIEMSIX_VECT211_MSG_DATA_BASE_IDX 5 6385 #define regPCIEMSIX_VECT211_CONTROL 0x1e34f 6386 #define regPCIEMSIX_VECT211_CONTROL_BASE_IDX 5 6387 #define regPCIEMSIX_VECT212_ADDR_LO 0x1e350 6388 #define regPCIEMSIX_VECT212_ADDR_LO_BASE_IDX 5 6389 #define regPCIEMSIX_VECT212_ADDR_HI 0x1e351 6390 #define regPCIEMSIX_VECT212_ADDR_HI_BASE_IDX 5 6391 #define regPCIEMSIX_VECT212_MSG_DATA 0x1e352 6392 #define regPCIEMSIX_VECT212_MSG_DATA_BASE_IDX 5 6393 #define regPCIEMSIX_VECT212_CONTROL 0x1e353 6394 #define regPCIEMSIX_VECT212_CONTROL_BASE_IDX 5 6395 #define regPCIEMSIX_VECT213_ADDR_LO 0x1e354 6396 #define regPCIEMSIX_VECT213_ADDR_LO_BASE_IDX 5 6397 #define regPCIEMSIX_VECT213_ADDR_HI 0x1e355 6398 #define regPCIEMSIX_VECT213_ADDR_HI_BASE_IDX 5 6399 #define regPCIEMSIX_VECT213_MSG_DATA 0x1e356 6400 #define regPCIEMSIX_VECT213_MSG_DATA_BASE_IDX 5 6401 #define regPCIEMSIX_VECT213_CONTROL 0x1e357 6402 #define regPCIEMSIX_VECT213_CONTROL_BASE_IDX 5 6403 #define regPCIEMSIX_VECT214_ADDR_LO 0x1e358 6404 #define regPCIEMSIX_VECT214_ADDR_LO_BASE_IDX 5 6405 #define regPCIEMSIX_VECT214_ADDR_HI 0x1e359 6406 #define regPCIEMSIX_VECT214_ADDR_HI_BASE_IDX 5 6407 #define regPCIEMSIX_VECT214_MSG_DATA 0x1e35a 6408 #define regPCIEMSIX_VECT214_MSG_DATA_BASE_IDX 5 6409 #define regPCIEMSIX_VECT214_CONTROL 0x1e35b 6410 #define regPCIEMSIX_VECT214_CONTROL_BASE_IDX 5 6411 #define regPCIEMSIX_VECT215_ADDR_LO 0x1e35c 6412 #define regPCIEMSIX_VECT215_ADDR_LO_BASE_IDX 5 6413 #define regPCIEMSIX_VECT215_ADDR_HI 0x1e35d 6414 #define regPCIEMSIX_VECT215_ADDR_HI_BASE_IDX 5 6415 #define regPCIEMSIX_VECT215_MSG_DATA 0x1e35e 6416 #define regPCIEMSIX_VECT215_MSG_DATA_BASE_IDX 5 6417 #define regPCIEMSIX_VECT215_CONTROL 0x1e35f 6418 #define regPCIEMSIX_VECT215_CONTROL_BASE_IDX 5 6419 #define regPCIEMSIX_VECT216_ADDR_LO 0x1e360 6420 #define regPCIEMSIX_VECT216_ADDR_LO_BASE_IDX 5 6421 #define regPCIEMSIX_VECT216_ADDR_HI 0x1e361 6422 #define regPCIEMSIX_VECT216_ADDR_HI_BASE_IDX 5 6423 #define regPCIEMSIX_VECT216_MSG_DATA 0x1e362 6424 #define regPCIEMSIX_VECT216_MSG_DATA_BASE_IDX 5 6425 #define regPCIEMSIX_VECT216_CONTROL 0x1e363 6426 #define regPCIEMSIX_VECT216_CONTROL_BASE_IDX 5 6427 #define regPCIEMSIX_VECT217_ADDR_LO 0x1e364 6428 #define regPCIEMSIX_VECT217_ADDR_LO_BASE_IDX 5 6429 #define regPCIEMSIX_VECT217_ADDR_HI 0x1e365 6430 #define regPCIEMSIX_VECT217_ADDR_HI_BASE_IDX 5 6431 #define regPCIEMSIX_VECT217_MSG_DATA 0x1e366 6432 #define regPCIEMSIX_VECT217_MSG_DATA_BASE_IDX 5 6433 #define regPCIEMSIX_VECT217_CONTROL 0x1e367 6434 #define regPCIEMSIX_VECT217_CONTROL_BASE_IDX 5 6435 #define regPCIEMSIX_VECT218_ADDR_LO 0x1e368 6436 #define regPCIEMSIX_VECT218_ADDR_LO_BASE_IDX 5 6437 #define regPCIEMSIX_VECT218_ADDR_HI 0x1e369 6438 #define regPCIEMSIX_VECT218_ADDR_HI_BASE_IDX 5 6439 #define regPCIEMSIX_VECT218_MSG_DATA 0x1e36a 6440 #define regPCIEMSIX_VECT218_MSG_DATA_BASE_IDX 5 6441 #define regPCIEMSIX_VECT218_CONTROL 0x1e36b 6442 #define regPCIEMSIX_VECT218_CONTROL_BASE_IDX 5 6443 #define regPCIEMSIX_VECT219_ADDR_LO 0x1e36c 6444 #define regPCIEMSIX_VECT219_ADDR_LO_BASE_IDX 5 6445 #define regPCIEMSIX_VECT219_ADDR_HI 0x1e36d 6446 #define regPCIEMSIX_VECT219_ADDR_HI_BASE_IDX 5 6447 #define regPCIEMSIX_VECT219_MSG_DATA 0x1e36e 6448 #define regPCIEMSIX_VECT219_MSG_DATA_BASE_IDX 5 6449 #define regPCIEMSIX_VECT219_CONTROL 0x1e36f 6450 #define regPCIEMSIX_VECT219_CONTROL_BASE_IDX 5 6451 #define regPCIEMSIX_VECT220_ADDR_LO 0x1e370 6452 #define regPCIEMSIX_VECT220_ADDR_LO_BASE_IDX 5 6453 #define regPCIEMSIX_VECT220_ADDR_HI 0x1e371 6454 #define regPCIEMSIX_VECT220_ADDR_HI_BASE_IDX 5 6455 #define regPCIEMSIX_VECT220_MSG_DATA 0x1e372 6456 #define regPCIEMSIX_VECT220_MSG_DATA_BASE_IDX 5 6457 #define regPCIEMSIX_VECT220_CONTROL 0x1e373 6458 #define regPCIEMSIX_VECT220_CONTROL_BASE_IDX 5 6459 #define regPCIEMSIX_VECT221_ADDR_LO 0x1e374 6460 #define regPCIEMSIX_VECT221_ADDR_LO_BASE_IDX 5 6461 #define regPCIEMSIX_VECT221_ADDR_HI 0x1e375 6462 #define regPCIEMSIX_VECT221_ADDR_HI_BASE_IDX 5 6463 #define regPCIEMSIX_VECT221_MSG_DATA 0x1e376 6464 #define regPCIEMSIX_VECT221_MSG_DATA_BASE_IDX 5 6465 #define regPCIEMSIX_VECT221_CONTROL 0x1e377 6466 #define regPCIEMSIX_VECT221_CONTROL_BASE_IDX 5 6467 #define regPCIEMSIX_VECT222_ADDR_LO 0x1e378 6468 #define regPCIEMSIX_VECT222_ADDR_LO_BASE_IDX 5 6469 #define regPCIEMSIX_VECT222_ADDR_HI 0x1e379 6470 #define regPCIEMSIX_VECT222_ADDR_HI_BASE_IDX 5 6471 #define regPCIEMSIX_VECT222_MSG_DATA 0x1e37a 6472 #define regPCIEMSIX_VECT222_MSG_DATA_BASE_IDX 5 6473 #define regPCIEMSIX_VECT222_CONTROL 0x1e37b 6474 #define regPCIEMSIX_VECT222_CONTROL_BASE_IDX 5 6475 #define regPCIEMSIX_VECT223_ADDR_LO 0x1e37c 6476 #define regPCIEMSIX_VECT223_ADDR_LO_BASE_IDX 5 6477 #define regPCIEMSIX_VECT223_ADDR_HI 0x1e37d 6478 #define regPCIEMSIX_VECT223_ADDR_HI_BASE_IDX 5 6479 #define regPCIEMSIX_VECT223_MSG_DATA 0x1e37e 6480 #define regPCIEMSIX_VECT223_MSG_DATA_BASE_IDX 5 6481 #define regPCIEMSIX_VECT223_CONTROL 0x1e37f 6482 #define regPCIEMSIX_VECT223_CONTROL_BASE_IDX 5 6483 #define regPCIEMSIX_VECT224_ADDR_LO 0x1e380 6484 #define regPCIEMSIX_VECT224_ADDR_LO_BASE_IDX 5 6485 #define regPCIEMSIX_VECT224_ADDR_HI 0x1e381 6486 #define regPCIEMSIX_VECT224_ADDR_HI_BASE_IDX 5 6487 #define regPCIEMSIX_VECT224_MSG_DATA 0x1e382 6488 #define regPCIEMSIX_VECT224_MSG_DATA_BASE_IDX 5 6489 #define regPCIEMSIX_VECT224_CONTROL 0x1e383 6490 #define regPCIEMSIX_VECT224_CONTROL_BASE_IDX 5 6491 #define regPCIEMSIX_VECT225_ADDR_LO 0x1e384 6492 #define regPCIEMSIX_VECT225_ADDR_LO_BASE_IDX 5 6493 #define regPCIEMSIX_VECT225_ADDR_HI 0x1e385 6494 #define regPCIEMSIX_VECT225_ADDR_HI_BASE_IDX 5 6495 #define regPCIEMSIX_VECT225_MSG_DATA 0x1e386 6496 #define regPCIEMSIX_VECT225_MSG_DATA_BASE_IDX 5 6497 #define regPCIEMSIX_VECT225_CONTROL 0x1e387 6498 #define regPCIEMSIX_VECT225_CONTROL_BASE_IDX 5 6499 #define regPCIEMSIX_VECT226_ADDR_LO 0x1e388 6500 #define regPCIEMSIX_VECT226_ADDR_LO_BASE_IDX 5 6501 #define regPCIEMSIX_VECT226_ADDR_HI 0x1e389 6502 #define regPCIEMSIX_VECT226_ADDR_HI_BASE_IDX 5 6503 #define regPCIEMSIX_VECT226_MSG_DATA 0x1e38a 6504 #define regPCIEMSIX_VECT226_MSG_DATA_BASE_IDX 5 6505 #define regPCIEMSIX_VECT226_CONTROL 0x1e38b 6506 #define regPCIEMSIX_VECT226_CONTROL_BASE_IDX 5 6507 #define regPCIEMSIX_VECT227_ADDR_LO 0x1e38c 6508 #define regPCIEMSIX_VECT227_ADDR_LO_BASE_IDX 5 6509 #define regPCIEMSIX_VECT227_ADDR_HI 0x1e38d 6510 #define regPCIEMSIX_VECT227_ADDR_HI_BASE_IDX 5 6511 #define regPCIEMSIX_VECT227_MSG_DATA 0x1e38e 6512 #define regPCIEMSIX_VECT227_MSG_DATA_BASE_IDX 5 6513 #define regPCIEMSIX_VECT227_CONTROL 0x1e38f 6514 #define regPCIEMSIX_VECT227_CONTROL_BASE_IDX 5 6515 #define regPCIEMSIX_VECT228_ADDR_LO 0x1e390 6516 #define regPCIEMSIX_VECT228_ADDR_LO_BASE_IDX 5 6517 #define regPCIEMSIX_VECT228_ADDR_HI 0x1e391 6518 #define regPCIEMSIX_VECT228_ADDR_HI_BASE_IDX 5 6519 #define regPCIEMSIX_VECT228_MSG_DATA 0x1e392 6520 #define regPCIEMSIX_VECT228_MSG_DATA_BASE_IDX 5 6521 #define regPCIEMSIX_VECT228_CONTROL 0x1e393 6522 #define regPCIEMSIX_VECT228_CONTROL_BASE_IDX 5 6523 #define regPCIEMSIX_VECT229_ADDR_LO 0x1e394 6524 #define regPCIEMSIX_VECT229_ADDR_LO_BASE_IDX 5 6525 #define regPCIEMSIX_VECT229_ADDR_HI 0x1e395 6526 #define regPCIEMSIX_VECT229_ADDR_HI_BASE_IDX 5 6527 #define regPCIEMSIX_VECT229_MSG_DATA 0x1e396 6528 #define regPCIEMSIX_VECT229_MSG_DATA_BASE_IDX 5 6529 #define regPCIEMSIX_VECT229_CONTROL 0x1e397 6530 #define regPCIEMSIX_VECT229_CONTROL_BASE_IDX 5 6531 #define regPCIEMSIX_VECT230_ADDR_LO 0x1e398 6532 #define regPCIEMSIX_VECT230_ADDR_LO_BASE_IDX 5 6533 #define regPCIEMSIX_VECT230_ADDR_HI 0x1e399 6534 #define regPCIEMSIX_VECT230_ADDR_HI_BASE_IDX 5 6535 #define regPCIEMSIX_VECT230_MSG_DATA 0x1e39a 6536 #define regPCIEMSIX_VECT230_MSG_DATA_BASE_IDX 5 6537 #define regPCIEMSIX_VECT230_CONTROL 0x1e39b 6538 #define regPCIEMSIX_VECT230_CONTROL_BASE_IDX 5 6539 #define regPCIEMSIX_VECT231_ADDR_LO 0x1e39c 6540 #define regPCIEMSIX_VECT231_ADDR_LO_BASE_IDX 5 6541 #define regPCIEMSIX_VECT231_ADDR_HI 0x1e39d 6542 #define regPCIEMSIX_VECT231_ADDR_HI_BASE_IDX 5 6543 #define regPCIEMSIX_VECT231_MSG_DATA 0x1e39e 6544 #define regPCIEMSIX_VECT231_MSG_DATA_BASE_IDX 5 6545 #define regPCIEMSIX_VECT231_CONTROL 0x1e39f 6546 #define regPCIEMSIX_VECT231_CONTROL_BASE_IDX 5 6547 #define regPCIEMSIX_VECT232_ADDR_LO 0x1e3a0 6548 #define regPCIEMSIX_VECT232_ADDR_LO_BASE_IDX 5 6549 #define regPCIEMSIX_VECT232_ADDR_HI 0x1e3a1 6550 #define regPCIEMSIX_VECT232_ADDR_HI_BASE_IDX 5 6551 #define regPCIEMSIX_VECT232_MSG_DATA 0x1e3a2 6552 #define regPCIEMSIX_VECT232_MSG_DATA_BASE_IDX 5 6553 #define regPCIEMSIX_VECT232_CONTROL 0x1e3a3 6554 #define regPCIEMSIX_VECT232_CONTROL_BASE_IDX 5 6555 #define regPCIEMSIX_VECT233_ADDR_LO 0x1e3a4 6556 #define regPCIEMSIX_VECT233_ADDR_LO_BASE_IDX 5 6557 #define regPCIEMSIX_VECT233_ADDR_HI 0x1e3a5 6558 #define regPCIEMSIX_VECT233_ADDR_HI_BASE_IDX 5 6559 #define regPCIEMSIX_VECT233_MSG_DATA 0x1e3a6 6560 #define regPCIEMSIX_VECT233_MSG_DATA_BASE_IDX 5 6561 #define regPCIEMSIX_VECT233_CONTROL 0x1e3a7 6562 #define regPCIEMSIX_VECT233_CONTROL_BASE_IDX 5 6563 #define regPCIEMSIX_VECT234_ADDR_LO 0x1e3a8 6564 #define regPCIEMSIX_VECT234_ADDR_LO_BASE_IDX 5 6565 #define regPCIEMSIX_VECT234_ADDR_HI 0x1e3a9 6566 #define regPCIEMSIX_VECT234_ADDR_HI_BASE_IDX 5 6567 #define regPCIEMSIX_VECT234_MSG_DATA 0x1e3aa 6568 #define regPCIEMSIX_VECT234_MSG_DATA_BASE_IDX 5 6569 #define regPCIEMSIX_VECT234_CONTROL 0x1e3ab 6570 #define regPCIEMSIX_VECT234_CONTROL_BASE_IDX 5 6571 #define regPCIEMSIX_VECT235_ADDR_LO 0x1e3ac 6572 #define regPCIEMSIX_VECT235_ADDR_LO_BASE_IDX 5 6573 #define regPCIEMSIX_VECT235_ADDR_HI 0x1e3ad 6574 #define regPCIEMSIX_VECT235_ADDR_HI_BASE_IDX 5 6575 #define regPCIEMSIX_VECT235_MSG_DATA 0x1e3ae 6576 #define regPCIEMSIX_VECT235_MSG_DATA_BASE_IDX 5 6577 #define regPCIEMSIX_VECT235_CONTROL 0x1e3af 6578 #define regPCIEMSIX_VECT235_CONTROL_BASE_IDX 5 6579 #define regPCIEMSIX_VECT236_ADDR_LO 0x1e3b0 6580 #define regPCIEMSIX_VECT236_ADDR_LO_BASE_IDX 5 6581 #define regPCIEMSIX_VECT236_ADDR_HI 0x1e3b1 6582 #define regPCIEMSIX_VECT236_ADDR_HI_BASE_IDX 5 6583 #define regPCIEMSIX_VECT236_MSG_DATA 0x1e3b2 6584 #define regPCIEMSIX_VECT236_MSG_DATA_BASE_IDX 5 6585 #define regPCIEMSIX_VECT236_CONTROL 0x1e3b3 6586 #define regPCIEMSIX_VECT236_CONTROL_BASE_IDX 5 6587 #define regPCIEMSIX_VECT237_ADDR_LO 0x1e3b4 6588 #define regPCIEMSIX_VECT237_ADDR_LO_BASE_IDX 5 6589 #define regPCIEMSIX_VECT237_ADDR_HI 0x1e3b5 6590 #define regPCIEMSIX_VECT237_ADDR_HI_BASE_IDX 5 6591 #define regPCIEMSIX_VECT237_MSG_DATA 0x1e3b6 6592 #define regPCIEMSIX_VECT237_MSG_DATA_BASE_IDX 5 6593 #define regPCIEMSIX_VECT237_CONTROL 0x1e3b7 6594 #define regPCIEMSIX_VECT237_CONTROL_BASE_IDX 5 6595 #define regPCIEMSIX_VECT238_ADDR_LO 0x1e3b8 6596 #define regPCIEMSIX_VECT238_ADDR_LO_BASE_IDX 5 6597 #define regPCIEMSIX_VECT238_ADDR_HI 0x1e3b9 6598 #define regPCIEMSIX_VECT238_ADDR_HI_BASE_IDX 5 6599 #define regPCIEMSIX_VECT238_MSG_DATA 0x1e3ba 6600 #define regPCIEMSIX_VECT238_MSG_DATA_BASE_IDX 5 6601 #define regPCIEMSIX_VECT238_CONTROL 0x1e3bb 6602 #define regPCIEMSIX_VECT238_CONTROL_BASE_IDX 5 6603 #define regPCIEMSIX_VECT239_ADDR_LO 0x1e3bc 6604 #define regPCIEMSIX_VECT239_ADDR_LO_BASE_IDX 5 6605 #define regPCIEMSIX_VECT239_ADDR_HI 0x1e3bd 6606 #define regPCIEMSIX_VECT239_ADDR_HI_BASE_IDX 5 6607 #define regPCIEMSIX_VECT239_MSG_DATA 0x1e3be 6608 #define regPCIEMSIX_VECT239_MSG_DATA_BASE_IDX 5 6609 #define regPCIEMSIX_VECT239_CONTROL 0x1e3bf 6610 #define regPCIEMSIX_VECT239_CONTROL_BASE_IDX 5 6611 #define regPCIEMSIX_VECT240_ADDR_LO 0x1e3c0 6612 #define regPCIEMSIX_VECT240_ADDR_LO_BASE_IDX 5 6613 #define regPCIEMSIX_VECT240_ADDR_HI 0x1e3c1 6614 #define regPCIEMSIX_VECT240_ADDR_HI_BASE_IDX 5 6615 #define regPCIEMSIX_VECT240_MSG_DATA 0x1e3c2 6616 #define regPCIEMSIX_VECT240_MSG_DATA_BASE_IDX 5 6617 #define regPCIEMSIX_VECT240_CONTROL 0x1e3c3 6618 #define regPCIEMSIX_VECT240_CONTROL_BASE_IDX 5 6619 #define regPCIEMSIX_VECT241_ADDR_LO 0x1e3c4 6620 #define regPCIEMSIX_VECT241_ADDR_LO_BASE_IDX 5 6621 #define regPCIEMSIX_VECT241_ADDR_HI 0x1e3c5 6622 #define regPCIEMSIX_VECT241_ADDR_HI_BASE_IDX 5 6623 #define regPCIEMSIX_VECT241_MSG_DATA 0x1e3c6 6624 #define regPCIEMSIX_VECT241_MSG_DATA_BASE_IDX 5 6625 #define regPCIEMSIX_VECT241_CONTROL 0x1e3c7 6626 #define regPCIEMSIX_VECT241_CONTROL_BASE_IDX 5 6627 #define regPCIEMSIX_VECT242_ADDR_LO 0x1e3c8 6628 #define regPCIEMSIX_VECT242_ADDR_LO_BASE_IDX 5 6629 #define regPCIEMSIX_VECT242_ADDR_HI 0x1e3c9 6630 #define regPCIEMSIX_VECT242_ADDR_HI_BASE_IDX 5 6631 #define regPCIEMSIX_VECT242_MSG_DATA 0x1e3ca 6632 #define regPCIEMSIX_VECT242_MSG_DATA_BASE_IDX 5 6633 #define regPCIEMSIX_VECT242_CONTROL 0x1e3cb 6634 #define regPCIEMSIX_VECT242_CONTROL_BASE_IDX 5 6635 #define regPCIEMSIX_VECT243_ADDR_LO 0x1e3cc 6636 #define regPCIEMSIX_VECT243_ADDR_LO_BASE_IDX 5 6637 #define regPCIEMSIX_VECT243_ADDR_HI 0x1e3cd 6638 #define regPCIEMSIX_VECT243_ADDR_HI_BASE_IDX 5 6639 #define regPCIEMSIX_VECT243_MSG_DATA 0x1e3ce 6640 #define regPCIEMSIX_VECT243_MSG_DATA_BASE_IDX 5 6641 #define regPCIEMSIX_VECT243_CONTROL 0x1e3cf 6642 #define regPCIEMSIX_VECT243_CONTROL_BASE_IDX 5 6643 #define regPCIEMSIX_VECT244_ADDR_LO 0x1e3d0 6644 #define regPCIEMSIX_VECT244_ADDR_LO_BASE_IDX 5 6645 #define regPCIEMSIX_VECT244_ADDR_HI 0x1e3d1 6646 #define regPCIEMSIX_VECT244_ADDR_HI_BASE_IDX 5 6647 #define regPCIEMSIX_VECT244_MSG_DATA 0x1e3d2 6648 #define regPCIEMSIX_VECT244_MSG_DATA_BASE_IDX 5 6649 #define regPCIEMSIX_VECT244_CONTROL 0x1e3d3 6650 #define regPCIEMSIX_VECT244_CONTROL_BASE_IDX 5 6651 #define regPCIEMSIX_VECT245_ADDR_LO 0x1e3d4 6652 #define regPCIEMSIX_VECT245_ADDR_LO_BASE_IDX 5 6653 #define regPCIEMSIX_VECT245_ADDR_HI 0x1e3d5 6654 #define regPCIEMSIX_VECT245_ADDR_HI_BASE_IDX 5 6655 #define regPCIEMSIX_VECT245_MSG_DATA 0x1e3d6 6656 #define regPCIEMSIX_VECT245_MSG_DATA_BASE_IDX 5 6657 #define regPCIEMSIX_VECT245_CONTROL 0x1e3d7 6658 #define regPCIEMSIX_VECT245_CONTROL_BASE_IDX 5 6659 #define regPCIEMSIX_VECT246_ADDR_LO 0x1e3d8 6660 #define regPCIEMSIX_VECT246_ADDR_LO_BASE_IDX 5 6661 #define regPCIEMSIX_VECT246_ADDR_HI 0x1e3d9 6662 #define regPCIEMSIX_VECT246_ADDR_HI_BASE_IDX 5 6663 #define regPCIEMSIX_VECT246_MSG_DATA 0x1e3da 6664 #define regPCIEMSIX_VECT246_MSG_DATA_BASE_IDX 5 6665 #define regPCIEMSIX_VECT246_CONTROL 0x1e3db 6666 #define regPCIEMSIX_VECT246_CONTROL_BASE_IDX 5 6667 #define regPCIEMSIX_VECT247_ADDR_LO 0x1e3dc 6668 #define regPCIEMSIX_VECT247_ADDR_LO_BASE_IDX 5 6669 #define regPCIEMSIX_VECT247_ADDR_HI 0x1e3dd 6670 #define regPCIEMSIX_VECT247_ADDR_HI_BASE_IDX 5 6671 #define regPCIEMSIX_VECT247_MSG_DATA 0x1e3de 6672 #define regPCIEMSIX_VECT247_MSG_DATA_BASE_IDX 5 6673 #define regPCIEMSIX_VECT247_CONTROL 0x1e3df 6674 #define regPCIEMSIX_VECT247_CONTROL_BASE_IDX 5 6675 #define regPCIEMSIX_VECT248_ADDR_LO 0x1e3e0 6676 #define regPCIEMSIX_VECT248_ADDR_LO_BASE_IDX 5 6677 #define regPCIEMSIX_VECT248_ADDR_HI 0x1e3e1 6678 #define regPCIEMSIX_VECT248_ADDR_HI_BASE_IDX 5 6679 #define regPCIEMSIX_VECT248_MSG_DATA 0x1e3e2 6680 #define regPCIEMSIX_VECT248_MSG_DATA_BASE_IDX 5 6681 #define regPCIEMSIX_VECT248_CONTROL 0x1e3e3 6682 #define regPCIEMSIX_VECT248_CONTROL_BASE_IDX 5 6683 #define regPCIEMSIX_VECT249_ADDR_LO 0x1e3e4 6684 #define regPCIEMSIX_VECT249_ADDR_LO_BASE_IDX 5 6685 #define regPCIEMSIX_VECT249_ADDR_HI 0x1e3e5 6686 #define regPCIEMSIX_VECT249_ADDR_HI_BASE_IDX 5 6687 #define regPCIEMSIX_VECT249_MSG_DATA 0x1e3e6 6688 #define regPCIEMSIX_VECT249_MSG_DATA_BASE_IDX 5 6689 #define regPCIEMSIX_VECT249_CONTROL 0x1e3e7 6690 #define regPCIEMSIX_VECT249_CONTROL_BASE_IDX 5 6691 #define regPCIEMSIX_VECT250_ADDR_LO 0x1e3e8 6692 #define regPCIEMSIX_VECT250_ADDR_LO_BASE_IDX 5 6693 #define regPCIEMSIX_VECT250_ADDR_HI 0x1e3e9 6694 #define regPCIEMSIX_VECT250_ADDR_HI_BASE_IDX 5 6695 #define regPCIEMSIX_VECT250_MSG_DATA 0x1e3ea 6696 #define regPCIEMSIX_VECT250_MSG_DATA_BASE_IDX 5 6697 #define regPCIEMSIX_VECT250_CONTROL 0x1e3eb 6698 #define regPCIEMSIX_VECT250_CONTROL_BASE_IDX 5 6699 #define regPCIEMSIX_VECT251_ADDR_LO 0x1e3ec 6700 #define regPCIEMSIX_VECT251_ADDR_LO_BASE_IDX 5 6701 #define regPCIEMSIX_VECT251_ADDR_HI 0x1e3ed 6702 #define regPCIEMSIX_VECT251_ADDR_HI_BASE_IDX 5 6703 #define regPCIEMSIX_VECT251_MSG_DATA 0x1e3ee 6704 #define regPCIEMSIX_VECT251_MSG_DATA_BASE_IDX 5 6705 #define regPCIEMSIX_VECT251_CONTROL 0x1e3ef 6706 #define regPCIEMSIX_VECT251_CONTROL_BASE_IDX 5 6707 #define regPCIEMSIX_VECT252_ADDR_LO 0x1e3f0 6708 #define regPCIEMSIX_VECT252_ADDR_LO_BASE_IDX 5 6709 #define regPCIEMSIX_VECT252_ADDR_HI 0x1e3f1 6710 #define regPCIEMSIX_VECT252_ADDR_HI_BASE_IDX 5 6711 #define regPCIEMSIX_VECT252_MSG_DATA 0x1e3f2 6712 #define regPCIEMSIX_VECT252_MSG_DATA_BASE_IDX 5 6713 #define regPCIEMSIX_VECT252_CONTROL 0x1e3f3 6714 #define regPCIEMSIX_VECT252_CONTROL_BASE_IDX 5 6715 #define regPCIEMSIX_VECT253_ADDR_LO 0x1e3f4 6716 #define regPCIEMSIX_VECT253_ADDR_LO_BASE_IDX 5 6717 #define regPCIEMSIX_VECT253_ADDR_HI 0x1e3f5 6718 #define regPCIEMSIX_VECT253_ADDR_HI_BASE_IDX 5 6719 #define regPCIEMSIX_VECT253_MSG_DATA 0x1e3f6 6720 #define regPCIEMSIX_VECT253_MSG_DATA_BASE_IDX 5 6721 #define regPCIEMSIX_VECT253_CONTROL 0x1e3f7 6722 #define regPCIEMSIX_VECT253_CONTROL_BASE_IDX 5 6723 #define regPCIEMSIX_VECT254_ADDR_LO 0x1e3f8 6724 #define regPCIEMSIX_VECT254_ADDR_LO_BASE_IDX 5 6725 #define regPCIEMSIX_VECT254_ADDR_HI 0x1e3f9 6726 #define regPCIEMSIX_VECT254_ADDR_HI_BASE_IDX 5 6727 #define regPCIEMSIX_VECT254_MSG_DATA 0x1e3fa 6728 #define regPCIEMSIX_VECT254_MSG_DATA_BASE_IDX 5 6729 #define regPCIEMSIX_VECT254_CONTROL 0x1e3fb 6730 #define regPCIEMSIX_VECT254_CONTROL_BASE_IDX 5 6731 #define regPCIEMSIX_VECT255_ADDR_LO 0x1e3fc 6732 #define regPCIEMSIX_VECT255_ADDR_LO_BASE_IDX 5 6733 #define regPCIEMSIX_VECT255_ADDR_HI 0x1e3fd 6734 #define regPCIEMSIX_VECT255_ADDR_HI_BASE_IDX 5 6735 #define regPCIEMSIX_VECT255_MSG_DATA 0x1e3fe 6736 #define regPCIEMSIX_VECT255_MSG_DATA_BASE_IDX 5 6737 #define regPCIEMSIX_VECT255_CONTROL 0x1e3ff 6738 #define regPCIEMSIX_VECT255_CONTROL_BASE_IDX 5 6739 6740 6741 // addressBlock: nbif_rcc_pfc_usb_RCCPFCDEC 6742 // base address: 0x10134400 6743 #define regRCC_PFC_USB_RCC_PFC_LTR_CNTL 0xd140 6744 #define regRCC_PFC_USB_RCC_PFC_LTR_CNTL_BASE_IDX 5 6745 #define regRCC_PFC_USB_RCC_PFC_PME_RESTORE 0xd141 6746 #define regRCC_PFC_USB_RCC_PFC_PME_RESTORE_BASE_IDX 5 6747 #define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0 0xd142 6748 #define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0_BASE_IDX 5 6749 #define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_1 0xd143 6750 #define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_1_BASE_IDX 5 6751 #define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_2 0xd144 6752 #define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_2_BASE_IDX 5 6753 #define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_3 0xd145 6754 #define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_3_BASE_IDX 5 6755 #define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_4 0xd146 6756 #define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_4_BASE_IDX 5 6757 #define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_5 0xd147 6758 #define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_5_BASE_IDX 5 6759 #define regRCC_PFC_USB_RCC_PFC_AUXPWR_CNTL 0xd148 6760 #define regRCC_PFC_USB_RCC_PFC_AUXPWR_CNTL_BASE_IDX 5 6761 6762 6763 // addressBlock: nbif_rcc_pfc_pd_controller_RCCPFCDEC 6764 // base address: 0x10134600 6765 #define regRCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL 0xd1c0 6766 #define regRCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL_BASE_IDX 5 6767 #define regRCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE 0xd1c1 6768 #define regRCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE_BASE_IDX 5 6769 #define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0 0xd1c2 6770 #define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0_BASE_IDX 5 6771 #define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_1 0xd1c3 6772 #define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_1_BASE_IDX 5 6773 #define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_2 0xd1c4 6774 #define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_2_BASE_IDX 5 6775 #define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_3 0xd1c5 6776 #define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_3_BASE_IDX 5 6777 #define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_4 0xd1c6 6778 #define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_4_BASE_IDX 5 6779 #define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_5 0xd1c7 6780 #define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_5_BASE_IDX 5 6781 #define regRCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL 0xd1c8 6782 #define regRCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL_BASE_IDX 5 6783 6784 6785 // addressBlock: nbif_pciemsix_0_usb_MSIXPDEC 6786 // base address: 0x10179000 6787 #define regPCIEMSIX_PBA_0 0x1e400 6788 #define regPCIEMSIX_PBA_0_BASE_IDX 5 6789 #define regPCIEMSIX_PBA_1 0x1e401 6790 #define regPCIEMSIX_PBA_1_BASE_IDX 5 6791 #define regPCIEMSIX_PBA_2 0x1e402 6792 #define regPCIEMSIX_PBA_2_BASE_IDX 5 6793 #define regPCIEMSIX_PBA_3 0x1e403 6794 #define regPCIEMSIX_PBA_3_BASE_IDX 5 6795 #define regPCIEMSIX_PBA_4 0x1e404 6796 #define regPCIEMSIX_PBA_4_BASE_IDX 5 6797 #define regPCIEMSIX_PBA_5 0x1e405 6798 #define regPCIEMSIX_PBA_5_BASE_IDX 5 6799 #define regPCIEMSIX_PBA_6 0x1e406 6800 #define regPCIEMSIX_PBA_6_BASE_IDX 5 6801 #define regPCIEMSIX_PBA_7 0x1e407 6802 #define regPCIEMSIX_PBA_7_BASE_IDX 5 6803 6804 6805 // addressBlock: nbif_rcc_shadow_reg_shadowdec 6806 // base address: 0x10130000 6807 #define regSHADOW_COMMAND 0xc001 6808 #define regSHADOW_COMMAND_BASE_IDX 5 6809 #define regSHADOW_BASE_ADDR_1 0xc004 6810 #define regSHADOW_BASE_ADDR_1_BASE_IDX 5 6811 #define regSHADOW_BASE_ADDR_2 0xc005 6812 #define regSHADOW_BASE_ADDR_2_BASE_IDX 5 6813 #define regSHADOW_IRQ_BRIDGE_CNTL 0xc00f 6814 #define regSHADOW_IRQ_BRIDGE_CNTL_BASE_IDX 5 6815 #define regSUC_INDEX 0xc038 6816 #define regSUC_INDEX_BASE_IDX 5 6817 #define regSUC_DATA 0xc039 6818 #define regSUC_DATA_BASE_IDX 5 6819 6820 6821 // addressBlock: nbif_bif_swus_SUMDEC 6822 // base address: 0x1013b000 6823 #define regSUM_INDEX 0xec38 6824 #define regSUM_INDEX_BASE_IDX 5 6825 #define regSUM_DATA 0xec39 6826 #define regSUM_DATA_BASE_IDX 5 6827 #define regSUM_INDEX_HI 0xec3b 6828 #define regSUM_INDEX_HI_BASE_IDX 5 6829 6830 6831 // addressBlock: nbif_rcc_strap_rcc_strap_internal 6832 // base address: 0x10100000 6833 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0 0xc400 6834 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0_BASE_IDX 5 6835 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1 0xc401 6836 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1_BASE_IDX 5 6837 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2 0xc402 6838 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2_BASE_IDX 5 6839 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3 0xc403 6840 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3_BASE_IDX 5 6841 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4 0xc404 6842 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4_BASE_IDX 5 6843 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5 0xc405 6844 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5_BASE_IDX 5 6845 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6 0xc406 6846 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6_BASE_IDX 5 6847 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7 0xc407 6848 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7_BASE_IDX 5 6849 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8 0xc408 6850 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8_BASE_IDX 5 6851 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9 0xc409 6852 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9_BASE_IDX 5 6853 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10 0xc40a 6854 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10_BASE_IDX 5 6855 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11 0xc40b 6856 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11_BASE_IDX 5 6857 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12 0xc40c 6858 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12_BASE_IDX 5 6859 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13 0xc40d 6860 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13_BASE_IDX 5 6861 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14 0xc40e 6862 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14_BASE_IDX 5 6863 #define regRCC_DEV1_PORT_STRAP0 0xc480 6864 #define regRCC_DEV1_PORT_STRAP0_BASE_IDX 5 6865 #define regRCC_DEV1_PORT_STRAP1 0xc481 6866 #define regRCC_DEV1_PORT_STRAP1_BASE_IDX 5 6867 #define regRCC_DEV1_PORT_STRAP2 0xc482 6868 #define regRCC_DEV1_PORT_STRAP2_BASE_IDX 5 6869 #define regRCC_DEV1_PORT_STRAP3 0xc483 6870 #define regRCC_DEV1_PORT_STRAP3_BASE_IDX 5 6871 #define regRCC_DEV1_PORT_STRAP4 0xc484 6872 #define regRCC_DEV1_PORT_STRAP4_BASE_IDX 5 6873 #define regRCC_DEV1_PORT_STRAP5 0xc485 6874 #define regRCC_DEV1_PORT_STRAP5_BASE_IDX 5 6875 #define regRCC_DEV1_PORT_STRAP6 0xc486 6876 #define regRCC_DEV1_PORT_STRAP6_BASE_IDX 5 6877 #define regRCC_DEV1_PORT_STRAP7 0xc487 6878 #define regRCC_DEV1_PORT_STRAP7_BASE_IDX 5 6879 #define regRCC_DEV1_PORT_STRAP8 0xc488 6880 #define regRCC_DEV1_PORT_STRAP8_BASE_IDX 5 6881 #define regRCC_DEV1_PORT_STRAP9 0xc489 6882 #define regRCC_DEV1_PORT_STRAP9_BASE_IDX 5 6883 #define regRCC_DEV1_PORT_STRAP10 0xc48a 6884 #define regRCC_DEV1_PORT_STRAP10_BASE_IDX 5 6885 #define regRCC_DEV1_PORT_STRAP11 0xc48b 6886 #define regRCC_DEV1_PORT_STRAP11_BASE_IDX 5 6887 #define regRCC_DEV1_PORT_STRAP12 0xc48c 6888 #define regRCC_DEV1_PORT_STRAP12_BASE_IDX 5 6889 #define regRCC_DEV1_PORT_STRAP13 0xc48d 6890 #define regRCC_DEV1_PORT_STRAP13_BASE_IDX 5 6891 #define regRCC_DEV1_PORT_STRAP14 0xc48e 6892 #define regRCC_DEV1_PORT_STRAP14_BASE_IDX 5 6893 #define regRCC_DEV2_PORT_STRAP0 0xc500 6894 #define regRCC_DEV2_PORT_STRAP0_BASE_IDX 5 6895 #define regRCC_DEV2_PORT_STRAP1 0xc501 6896 #define regRCC_DEV2_PORT_STRAP1_BASE_IDX 5 6897 #define regRCC_DEV2_PORT_STRAP2 0xc502 6898 #define regRCC_DEV2_PORT_STRAP2_BASE_IDX 5 6899 #define regRCC_DEV2_PORT_STRAP3 0xc503 6900 #define regRCC_DEV2_PORT_STRAP3_BASE_IDX 5 6901 #define regRCC_DEV2_PORT_STRAP4 0xc504 6902 #define regRCC_DEV2_PORT_STRAP4_BASE_IDX 5 6903 #define regRCC_DEV2_PORT_STRAP5 0xc505 6904 #define regRCC_DEV2_PORT_STRAP5_BASE_IDX 5 6905 #define regRCC_DEV2_PORT_STRAP6 0xc506 6906 #define regRCC_DEV2_PORT_STRAP6_BASE_IDX 5 6907 #define regRCC_DEV2_PORT_STRAP7 0xc507 6908 #define regRCC_DEV2_PORT_STRAP7_BASE_IDX 5 6909 #define regRCC_DEV2_PORT_STRAP8 0xc508 6910 #define regRCC_DEV2_PORT_STRAP8_BASE_IDX 5 6911 #define regRCC_DEV2_PORT_STRAP9 0xc509 6912 #define regRCC_DEV2_PORT_STRAP9_BASE_IDX 5 6913 #define regRCC_DEV2_PORT_STRAP10 0xc50a 6914 #define regRCC_DEV2_PORT_STRAP10_BASE_IDX 5 6915 #define regRCC_DEV2_PORT_STRAP11 0xc50b 6916 #define regRCC_DEV2_PORT_STRAP11_BASE_IDX 5 6917 #define regRCC_DEV2_PORT_STRAP12 0xc50c 6918 #define regRCC_DEV2_PORT_STRAP12_BASE_IDX 5 6919 #define regRCC_DEV2_PORT_STRAP13 0xc50d 6920 #define regRCC_DEV2_PORT_STRAP13_BASE_IDX 5 6921 #define regRCC_DEV2_PORT_STRAP14 0xc50e 6922 #define regRCC_DEV2_PORT_STRAP14_BASE_IDX 5 6923 #define regRCC_STRAP1_RCC_BIF_STRAP0 0xc600 6924 #define regRCC_STRAP1_RCC_BIF_STRAP0_BASE_IDX 5 6925 #define regRCC_STRAP1_RCC_BIF_STRAP1 0xc601 6926 #define regRCC_STRAP1_RCC_BIF_STRAP1_BASE_IDX 5 6927 #define regRCC_STRAP1_RCC_BIF_STRAP2 0xc602 6928 #define regRCC_STRAP1_RCC_BIF_STRAP2_BASE_IDX 5 6929 #define regRCC_STRAP1_RCC_BIF_STRAP3 0xc603 6930 #define regRCC_STRAP1_RCC_BIF_STRAP3_BASE_IDX 5 6931 #define regRCC_STRAP1_RCC_BIF_STRAP4 0xc604 6932 #define regRCC_STRAP1_RCC_BIF_STRAP4_BASE_IDX 5 6933 #define regRCC_STRAP1_RCC_BIF_STRAP5 0xc605 6934 #define regRCC_STRAP1_RCC_BIF_STRAP5_BASE_IDX 5 6935 #define regRCC_STRAP1_RCC_BIF_STRAP6 0xc606 6936 #define regRCC_STRAP1_RCC_BIF_STRAP6_BASE_IDX 5 6937 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0 0xd000 6938 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_BASE_IDX 5 6939 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1 0xd001 6940 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_BASE_IDX 5 6941 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2 0xd002 6942 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_BASE_IDX 5 6943 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3 0xd003 6944 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_BASE_IDX 5 6945 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4 0xd004 6946 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_BASE_IDX 5 6947 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5 0xd005 6948 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_BASE_IDX 5 6949 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8 0xd008 6950 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_BASE_IDX 5 6951 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9 0xd009 6952 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_BASE_IDX 5 6953 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13 0xd00d 6954 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_BASE_IDX 5 6955 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14 0xd00e 6956 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14_BASE_IDX 5 6957 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15 0xd00f 6958 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15_BASE_IDX 5 6959 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16 0xd010 6960 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16_BASE_IDX 5 6961 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17 0xd011 6962 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17_BASE_IDX 5 6963 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18 0xd012 6964 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18_BASE_IDX 5 6965 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0 0xd080 6966 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_BASE_IDX 5 6967 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2 0xd082 6968 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_BASE_IDX 5 6969 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3 0xd083 6970 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_BASE_IDX 5 6971 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4 0xd084 6972 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_BASE_IDX 5 6973 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5 0xd085 6974 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_BASE_IDX 5 6975 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6 0xd086 6976 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_BASE_IDX 5 6977 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7 0xd087 6978 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_BASE_IDX 5 6979 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20 0xd094 6980 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20_BASE_IDX 5 6981 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21 0xd095 6982 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21_BASE_IDX 5 6983 #define regRCC_DEV0_EPF2_STRAP0 0xd100 6984 #define regRCC_DEV0_EPF2_STRAP0_BASE_IDX 5 6985 #define regRCC_DEV0_EPF2_STRAP2 0xd102 6986 #define regRCC_DEV0_EPF2_STRAP2_BASE_IDX 5 6987 #define regRCC_DEV0_EPF2_STRAP3 0xd103 6988 #define regRCC_DEV0_EPF2_STRAP3_BASE_IDX 5 6989 #define regRCC_DEV0_EPF2_STRAP4 0xd104 6990 #define regRCC_DEV0_EPF2_STRAP4_BASE_IDX 5 6991 #define regRCC_DEV0_EPF2_STRAP5 0xd105 6992 #define regRCC_DEV0_EPF2_STRAP5_BASE_IDX 5 6993 #define regRCC_DEV0_EPF2_STRAP6 0xd106 6994 #define regRCC_DEV0_EPF2_STRAP6_BASE_IDX 5 6995 #define regRCC_DEV0_EPF2_STRAP7 0xd107 6996 #define regRCC_DEV0_EPF2_STRAP7_BASE_IDX 5 6997 #define regRCC_DEV0_EPF2_STRAP10 0xd10a 6998 #define regRCC_DEV0_EPF2_STRAP10_BASE_IDX 5 6999 #define regRCC_DEV0_EPF2_STRAP11 0xd10b 7000 #define regRCC_DEV0_EPF2_STRAP11_BASE_IDX 5 7001 #define regRCC_DEV0_EPF2_STRAP12 0xd10c 7002 #define regRCC_DEV0_EPF2_STRAP12_BASE_IDX 5 7003 #define regRCC_DEV0_EPF2_STRAP13 0xd10d 7004 #define regRCC_DEV0_EPF2_STRAP13_BASE_IDX 5 7005 #define regRCC_DEV0_EPF2_STRAP14 0xd10e 7006 #define regRCC_DEV0_EPF2_STRAP14_BASE_IDX 5 7007 #define regRCC_DEV0_EPF2_STRAP20 0xd114 7008 #define regRCC_DEV0_EPF2_STRAP20_BASE_IDX 5 7009 #define regRCC_DEV0_EPF3_STRAP0 0xd180 7010 #define regRCC_DEV0_EPF3_STRAP0_BASE_IDX 5 7011 #define regRCC_DEV0_EPF3_STRAP2 0xd182 7012 #define regRCC_DEV0_EPF3_STRAP2_BASE_IDX 5 7013 #define regRCC_DEV0_EPF3_STRAP3 0xd183 7014 #define regRCC_DEV0_EPF3_STRAP3_BASE_IDX 5 7015 #define regRCC_DEV0_EPF3_STRAP4 0xd184 7016 #define regRCC_DEV0_EPF3_STRAP4_BASE_IDX 5 7017 #define regRCC_DEV0_EPF3_STRAP5 0xd185 7018 #define regRCC_DEV0_EPF3_STRAP5_BASE_IDX 5 7019 #define regRCC_DEV0_EPF3_STRAP6 0xd186 7020 #define regRCC_DEV0_EPF3_STRAP6_BASE_IDX 5 7021 #define regRCC_DEV0_EPF3_STRAP7 0xd187 7022 #define regRCC_DEV0_EPF3_STRAP7_BASE_IDX 5 7023 #define regRCC_DEV0_EPF3_STRAP10 0xd18a 7024 #define regRCC_DEV0_EPF3_STRAP10_BASE_IDX 5 7025 #define regRCC_DEV0_EPF3_STRAP11 0xd18b 7026 #define regRCC_DEV0_EPF3_STRAP11_BASE_IDX 5 7027 #define regRCC_DEV0_EPF3_STRAP12 0xd18c 7028 #define regRCC_DEV0_EPF3_STRAP12_BASE_IDX 5 7029 #define regRCC_DEV0_EPF3_STRAP13 0xd18d 7030 #define regRCC_DEV0_EPF3_STRAP13_BASE_IDX 5 7031 #define regRCC_DEV0_EPF3_STRAP14 0xd18e 7032 #define regRCC_DEV0_EPF3_STRAP14_BASE_IDX 5 7033 #define regRCC_DEV0_EPF3_STRAP20 0xd194 7034 #define regRCC_DEV0_EPF3_STRAP20_BASE_IDX 5 7035 #define regRCC_DEV0_EPF4_STRAP0 0xd200 7036 #define regRCC_DEV0_EPF4_STRAP0_BASE_IDX 5 7037 #define regRCC_DEV0_EPF4_STRAP2 0xd202 7038 #define regRCC_DEV0_EPF4_STRAP2_BASE_IDX 5 7039 #define regRCC_DEV0_EPF4_STRAP3 0xd203 7040 #define regRCC_DEV0_EPF4_STRAP3_BASE_IDX 5 7041 #define regRCC_DEV0_EPF4_STRAP4 0xd204 7042 #define regRCC_DEV0_EPF4_STRAP4_BASE_IDX 5 7043 #define regRCC_DEV0_EPF4_STRAP5 0xd205 7044 #define regRCC_DEV0_EPF4_STRAP5_BASE_IDX 5 7045 #define regRCC_DEV0_EPF4_STRAP6 0xd206 7046 #define regRCC_DEV0_EPF4_STRAP6_BASE_IDX 5 7047 #define regRCC_DEV0_EPF4_STRAP7 0xd207 7048 #define regRCC_DEV0_EPF4_STRAP7_BASE_IDX 5 7049 #define regRCC_DEV0_EPF4_STRAP13 0xd20d 7050 #define regRCC_DEV0_EPF4_STRAP13_BASE_IDX 5 7051 #define regRCC_DEV0_EPF4_STRAP14 0xd20e 7052 #define regRCC_DEV0_EPF4_STRAP14_BASE_IDX 5 7053 #define regRCC_DEV0_EPF5_STRAP0 0xd280 7054 #define regRCC_DEV0_EPF5_STRAP0_BASE_IDX 5 7055 #define regRCC_DEV0_EPF5_STRAP2 0xd282 7056 #define regRCC_DEV0_EPF5_STRAP2_BASE_IDX 5 7057 #define regRCC_DEV0_EPF5_STRAP3 0xd283 7058 #define regRCC_DEV0_EPF5_STRAP3_BASE_IDX 5 7059 #define regRCC_DEV0_EPF5_STRAP4 0xd284 7060 #define regRCC_DEV0_EPF5_STRAP4_BASE_IDX 5 7061 #define regRCC_DEV0_EPF5_STRAP5 0xd285 7062 #define regRCC_DEV0_EPF5_STRAP5_BASE_IDX 5 7063 #define regRCC_DEV0_EPF5_STRAP6 0xd286 7064 #define regRCC_DEV0_EPF5_STRAP6_BASE_IDX 5 7065 #define regRCC_DEV0_EPF5_STRAP7 0xd287 7066 #define regRCC_DEV0_EPF5_STRAP7_BASE_IDX 5 7067 #define regRCC_DEV0_EPF5_STRAP13 0xd28d 7068 #define regRCC_DEV0_EPF5_STRAP13_BASE_IDX 5 7069 #define regRCC_DEV0_EPF5_STRAP14 0xd28e 7070 #define regRCC_DEV0_EPF5_STRAP14_BASE_IDX 5 7071 #define regRCC_DEV0_EPF6_STRAP0 0xd300 7072 #define regRCC_DEV0_EPF6_STRAP0_BASE_IDX 5 7073 #define regRCC_DEV0_EPF6_STRAP2 0xd302 7074 #define regRCC_DEV0_EPF6_STRAP2_BASE_IDX 5 7075 #define regRCC_DEV0_EPF6_STRAP3 0xd303 7076 #define regRCC_DEV0_EPF6_STRAP3_BASE_IDX 5 7077 #define regRCC_DEV0_EPF6_STRAP4 0xd304 7078 #define regRCC_DEV0_EPF6_STRAP4_BASE_IDX 5 7079 #define regRCC_DEV0_EPF6_STRAP5 0xd305 7080 #define regRCC_DEV0_EPF6_STRAP5_BASE_IDX 5 7081 #define regRCC_DEV0_EPF6_STRAP6 0xd306 7082 #define regRCC_DEV0_EPF6_STRAP6_BASE_IDX 5 7083 #define regRCC_DEV0_EPF6_STRAP13 0xd30d 7084 #define regRCC_DEV0_EPF6_STRAP13_BASE_IDX 5 7085 #define regRCC_DEV0_EPF6_STRAP14 0xd30e 7086 #define regRCC_DEV0_EPF6_STRAP14_BASE_IDX 5 7087 #define regRCC_DEV0_EPF7_STRAP0 0xd380 7088 #define regRCC_DEV0_EPF7_STRAP0_BASE_IDX 5 7089 #define regRCC_DEV0_EPF7_STRAP2 0xd382 7090 #define regRCC_DEV0_EPF7_STRAP2_BASE_IDX 5 7091 #define regRCC_DEV0_EPF7_STRAP3 0xd383 7092 #define regRCC_DEV0_EPF7_STRAP3_BASE_IDX 5 7093 #define regRCC_DEV0_EPF7_STRAP4 0xd384 7094 #define regRCC_DEV0_EPF7_STRAP4_BASE_IDX 5 7095 #define regRCC_DEV0_EPF7_STRAP5 0xd385 7096 #define regRCC_DEV0_EPF7_STRAP5_BASE_IDX 5 7097 #define regRCC_DEV0_EPF7_STRAP6 0xd386 7098 #define regRCC_DEV0_EPF7_STRAP6_BASE_IDX 5 7099 #define regRCC_DEV0_EPF7_STRAP13 0xd38d 7100 #define regRCC_DEV0_EPF7_STRAP13_BASE_IDX 5 7101 #define regRCC_DEV0_EPF7_STRAP14 0xd38e 7102 #define regRCC_DEV0_EPF7_STRAP14_BASE_IDX 5 7103 #define regRCC_DEV1_EPF0_STRAP0 0xd400 7104 #define regRCC_DEV1_EPF0_STRAP0_BASE_IDX 5 7105 #define regRCC_DEV1_EPF0_STRAP2 0xd402 7106 #define regRCC_DEV1_EPF0_STRAP2_BASE_IDX 5 7107 #define regRCC_DEV1_EPF0_STRAP3 0xd403 7108 #define regRCC_DEV1_EPF0_STRAP3_BASE_IDX 5 7109 #define regRCC_DEV1_EPF0_STRAP4 0xd404 7110 #define regRCC_DEV1_EPF0_STRAP4_BASE_IDX 5 7111 #define regRCC_DEV1_EPF0_STRAP5 0xd405 7112 #define regRCC_DEV1_EPF0_STRAP5_BASE_IDX 5 7113 #define regRCC_DEV1_EPF0_STRAP6 0xd406 7114 #define regRCC_DEV1_EPF0_STRAP6_BASE_IDX 5 7115 #define regRCC_DEV1_EPF0_STRAP13 0xd40d 7116 #define regRCC_DEV1_EPF0_STRAP13_BASE_IDX 5 7117 #define regRCC_DEV1_EPF0_STRAP14 0xd40e 7118 #define regRCC_DEV1_EPF0_STRAP14_BASE_IDX 5 7119 #define regRCC_DEV1_EPF1_STRAP0 0xd480 7120 #define regRCC_DEV1_EPF1_STRAP0_BASE_IDX 5 7121 #define regRCC_DEV1_EPF1_STRAP2 0xd482 7122 #define regRCC_DEV1_EPF1_STRAP2_BASE_IDX 5 7123 #define regRCC_DEV1_EPF1_STRAP3 0xd483 7124 #define regRCC_DEV1_EPF1_STRAP3_BASE_IDX 5 7125 #define regRCC_DEV1_EPF1_STRAP4 0xd484 7126 #define regRCC_DEV1_EPF1_STRAP4_BASE_IDX 5 7127 #define regRCC_DEV1_EPF1_STRAP5 0xd485 7128 #define regRCC_DEV1_EPF1_STRAP5_BASE_IDX 5 7129 #define regRCC_DEV1_EPF1_STRAP6 0xd486 7130 #define regRCC_DEV1_EPF1_STRAP6_BASE_IDX 5 7131 #define regRCC_DEV1_EPF1_STRAP13 0xd48d 7132 #define regRCC_DEV1_EPF1_STRAP13_BASE_IDX 5 7133 #define regRCC_DEV1_EPF1_STRAP14 0xd48e 7134 #define regRCC_DEV1_EPF1_STRAP14_BASE_IDX 5 7135 #define regRCC_DEV1_EPF2_STRAP0 0xd500 7136 #define regRCC_DEV1_EPF2_STRAP0_BASE_IDX 5 7137 #define regRCC_DEV1_EPF2_STRAP2 0xd502 7138 #define regRCC_DEV1_EPF2_STRAP2_BASE_IDX 5 7139 #define regRCC_DEV1_EPF2_STRAP3 0xd503 7140 #define regRCC_DEV1_EPF2_STRAP3_BASE_IDX 5 7141 #define regRCC_DEV1_EPF2_STRAP4 0xd504 7142 #define regRCC_DEV1_EPF2_STRAP4_BASE_IDX 5 7143 #define regRCC_DEV1_EPF2_STRAP5 0xd505 7144 #define regRCC_DEV1_EPF2_STRAP5_BASE_IDX 5 7145 #define regRCC_DEV1_EPF2_STRAP13 0xd50d 7146 #define regRCC_DEV1_EPF2_STRAP13_BASE_IDX 5 7147 #define regRCC_DEV1_EPF2_STRAP14 0xd50e 7148 #define regRCC_DEV1_EPF2_STRAP14_BASE_IDX 5 7149 #define regRCC_DEV1_EPF3_STRAP0 0xd580 7150 #define regRCC_DEV1_EPF3_STRAP0_BASE_IDX 5 7151 #define regRCC_DEV1_EPF3_STRAP2 0xd582 7152 #define regRCC_DEV1_EPF3_STRAP2_BASE_IDX 5 7153 #define regRCC_DEV1_EPF3_STRAP3 0xd583 7154 #define regRCC_DEV1_EPF3_STRAP3_BASE_IDX 5 7155 #define regRCC_DEV1_EPF3_STRAP4 0xd584 7156 #define regRCC_DEV1_EPF3_STRAP4_BASE_IDX 5 7157 #define regRCC_DEV1_EPF3_STRAP5 0xd585 7158 #define regRCC_DEV1_EPF3_STRAP5_BASE_IDX 5 7159 #define regRCC_DEV1_EPF3_STRAP13 0xd58d 7160 #define regRCC_DEV1_EPF3_STRAP13_BASE_IDX 5 7161 #define regRCC_DEV1_EPF3_STRAP14 0xd58e 7162 #define regRCC_DEV1_EPF3_STRAP14_BASE_IDX 5 7163 #define regRCC_DEV1_EPF4_STRAP0 0xd600 7164 #define regRCC_DEV1_EPF4_STRAP0_BASE_IDX 5 7165 #define regRCC_DEV1_EPF4_STRAP2 0xd602 7166 #define regRCC_DEV1_EPF4_STRAP2_BASE_IDX 5 7167 #define regRCC_DEV1_EPF4_STRAP3 0xd603 7168 #define regRCC_DEV1_EPF4_STRAP3_BASE_IDX 5 7169 #define regRCC_DEV1_EPF4_STRAP4 0xd604 7170 #define regRCC_DEV1_EPF4_STRAP4_BASE_IDX 5 7171 #define regRCC_DEV1_EPF4_STRAP5 0xd605 7172 #define regRCC_DEV1_EPF4_STRAP5_BASE_IDX 5 7173 #define regRCC_DEV1_EPF4_STRAP13 0xd60d 7174 #define regRCC_DEV1_EPF4_STRAP13_BASE_IDX 5 7175 #define regRCC_DEV1_EPF4_STRAP14 0xd60e 7176 #define regRCC_DEV1_EPF4_STRAP14_BASE_IDX 5 7177 #define regRCC_DEV1_EPF5_STRAP0 0xd680 7178 #define regRCC_DEV1_EPF5_STRAP0_BASE_IDX 5 7179 #define regRCC_DEV1_EPF5_STRAP2 0xd682 7180 #define regRCC_DEV1_EPF5_STRAP2_BASE_IDX 5 7181 #define regRCC_DEV1_EPF5_STRAP3 0xd683 7182 #define regRCC_DEV1_EPF5_STRAP3_BASE_IDX 5 7183 #define regRCC_DEV1_EPF5_STRAP4 0xd684 7184 #define regRCC_DEV1_EPF5_STRAP4_BASE_IDX 5 7185 #define regRCC_DEV1_EPF5_STRAP5 0xd685 7186 #define regRCC_DEV1_EPF5_STRAP5_BASE_IDX 5 7187 #define regRCC_DEV1_EPF5_STRAP13 0xd68d 7188 #define regRCC_DEV1_EPF5_STRAP13_BASE_IDX 5 7189 #define regRCC_DEV1_EPF5_STRAP14 0xd68e 7190 #define regRCC_DEV1_EPF5_STRAP14_BASE_IDX 5 7191 #define regRCC_DEV2_EPF0_STRAP0 0xd800 7192 #define regRCC_DEV2_EPF0_STRAP0_BASE_IDX 5 7193 #define regRCC_DEV2_EPF0_STRAP2 0xd802 7194 #define regRCC_DEV2_EPF0_STRAP2_BASE_IDX 5 7195 #define regRCC_DEV2_EPF0_STRAP3 0xd803 7196 #define regRCC_DEV2_EPF0_STRAP3_BASE_IDX 5 7197 #define regRCC_DEV2_EPF0_STRAP4 0xd804 7198 #define regRCC_DEV2_EPF0_STRAP4_BASE_IDX 5 7199 #define regRCC_DEV2_EPF0_STRAP5 0xd805 7200 #define regRCC_DEV2_EPF0_STRAP5_BASE_IDX 5 7201 #define regRCC_DEV2_EPF0_STRAP6 0xd806 7202 #define regRCC_DEV2_EPF0_STRAP6_BASE_IDX 5 7203 #define regRCC_DEV2_EPF0_STRAP7 0xd807 7204 #define regRCC_DEV2_EPF0_STRAP7_BASE_IDX 5 7205 #define regRCC_DEV2_EPF0_STRAP13 0xd80d 7206 #define regRCC_DEV2_EPF0_STRAP13_BASE_IDX 5 7207 #define regRCC_DEV2_EPF0_STRAP14 0xd80e 7208 #define regRCC_DEV2_EPF0_STRAP14_BASE_IDX 5 7209 #define regRCC_DEV2_EPF1_STRAP0 0xd880 7210 #define regRCC_DEV2_EPF1_STRAP0_BASE_IDX 5 7211 #define regRCC_DEV2_EPF1_STRAP2 0xd882 7212 #define regRCC_DEV2_EPF1_STRAP2_BASE_IDX 5 7213 #define regRCC_DEV2_EPF1_STRAP3 0xd883 7214 #define regRCC_DEV2_EPF1_STRAP3_BASE_IDX 5 7215 #define regRCC_DEV2_EPF1_STRAP4 0xd884 7216 #define regRCC_DEV2_EPF1_STRAP4_BASE_IDX 5 7217 #define regRCC_DEV2_EPF1_STRAP5 0xd885 7218 #define regRCC_DEV2_EPF1_STRAP5_BASE_IDX 5 7219 #define regRCC_DEV2_EPF1_STRAP6 0xd886 7220 #define regRCC_DEV2_EPF1_STRAP6_BASE_IDX 5 7221 #define regRCC_DEV2_EPF1_STRAP13 0xd88d 7222 #define regRCC_DEV2_EPF1_STRAP13_BASE_IDX 5 7223 #define regRCC_DEV2_EPF1_STRAP14 0xd88e 7224 #define regRCC_DEV2_EPF1_STRAP14_BASE_IDX 5 7225 #define regRCC_DEV2_EPF2_STRAP0 0xd900 7226 #define regRCC_DEV2_EPF2_STRAP0_BASE_IDX 5 7227 #define regRCC_DEV2_EPF2_STRAP2 0xd902 7228 #define regRCC_DEV2_EPF2_STRAP2_BASE_IDX 5 7229 #define regRCC_DEV2_EPF2_STRAP3 0xd903 7230 #define regRCC_DEV2_EPF2_STRAP3_BASE_IDX 5 7231 #define regRCC_DEV2_EPF2_STRAP4 0xd904 7232 #define regRCC_DEV2_EPF2_STRAP4_BASE_IDX 5 7233 #define regRCC_DEV2_EPF2_STRAP5 0xd905 7234 #define regRCC_DEV2_EPF2_STRAP5_BASE_IDX 5 7235 #define regRCC_DEV2_EPF2_STRAP6 0xd906 7236 #define regRCC_DEV2_EPF2_STRAP6_BASE_IDX 5 7237 #define regRCC_DEV2_EPF2_STRAP13 0xd90d 7238 #define regRCC_DEV2_EPF2_STRAP13_BASE_IDX 5 7239 #define regRCC_DEV2_EPF2_STRAP14 0xd90e 7240 #define regRCC_DEV2_EPF2_STRAP14_BASE_IDX 5 7241 7242 7243 // addressBlock: nbif_bif_rst_bif_rst_regblk 7244 // base address: 0x10100000 7245 #define regHARD_RST_CTRL 0xe000 7246 #define regHARD_RST_CTRL_BASE_IDX 5 7247 #define regRSMU_SOFT_RST_CTRL 0xe001 7248 #define regRSMU_SOFT_RST_CTRL_BASE_IDX 5 7249 #define regSELF_SOFT_RST 0xe002 7250 #define regSELF_SOFT_RST_BASE_IDX 5 7251 #define regBIF_GFX_DRV_VPU_RST 0xe003 7252 #define regBIF_GFX_DRV_VPU_RST_BASE_IDX 5 7253 #define regBIF_RST_MISC_CTRL 0xe004 7254 #define regBIF_RST_MISC_CTRL_BASE_IDX 5 7255 #define regBIF_RST_MISC_CTRL2 0xe005 7256 #define regBIF_RST_MISC_CTRL2_BASE_IDX 5 7257 #define regBIF_RST_MISC_CTRL3 0xe006 7258 #define regBIF_RST_MISC_CTRL3_BASE_IDX 5 7259 #define regDEV0_PF0_FLR_RST_CTRL 0xe008 7260 #define regDEV0_PF0_FLR_RST_CTRL_BASE_IDX 5 7261 #define regDEV0_PF1_FLR_RST_CTRL 0xe009 7262 #define regDEV0_PF1_FLR_RST_CTRL_BASE_IDX 5 7263 #define regDEV0_PF2_FLR_RST_CTRL 0xe00a 7264 #define regDEV0_PF2_FLR_RST_CTRL_BASE_IDX 5 7265 #define regDEV0_PF3_FLR_RST_CTRL 0xe00b 7266 #define regDEV0_PF3_FLR_RST_CTRL_BASE_IDX 5 7267 #define regDEV0_PF4_FLR_RST_CTRL 0xe00c 7268 #define regDEV0_PF4_FLR_RST_CTRL_BASE_IDX 5 7269 #define regDEV0_PF5_FLR_RST_CTRL 0xe00d 7270 #define regDEV0_PF5_FLR_RST_CTRL_BASE_IDX 5 7271 #define regDEV0_PF6_FLR_RST_CTRL 0xe00e 7272 #define regDEV0_PF6_FLR_RST_CTRL_BASE_IDX 5 7273 #define regBIF_INST_RESET_INTR_STS 0xe010 7274 #define regBIF_INST_RESET_INTR_STS_BASE_IDX 5 7275 #define regBIF_PF_FLR_INTR_STS 0xe011 7276 #define regBIF_PF_FLR_INTR_STS_BASE_IDX 5 7277 #define regBIF_D3HOTD0_INTR_STS 0xe012 7278 #define regBIF_D3HOTD0_INTR_STS_BASE_IDX 5 7279 #define regBIF_POWER_INTR_STS 0xe014 7280 #define regBIF_POWER_INTR_STS_BASE_IDX 5 7281 #define regBIF_PF_DSTATE_INTR_STS 0xe015 7282 #define regBIF_PF_DSTATE_INTR_STS_BASE_IDX 5 7283 #define regSELF_SOFT_RST_2 0xe016 7284 #define regSELF_SOFT_RST_2_BASE_IDX 5 7285 #define regBIF_INST_RESET_INTR_MASK 0xe020 7286 #define regBIF_INST_RESET_INTR_MASK_BASE_IDX 5 7287 #define regBIF_PF_FLR_INTR_MASK 0xe021 7288 #define regBIF_PF_FLR_INTR_MASK_BASE_IDX 5 7289 #define regBIF_D3HOTD0_INTR_MASK 0xe022 7290 #define regBIF_D3HOTD0_INTR_MASK_BASE_IDX 5 7291 #define regBIF_POWER_INTR_MASK 0xe024 7292 #define regBIF_POWER_INTR_MASK_BASE_IDX 5 7293 #define regBIF_PF_DSTATE_INTR_MASK 0xe025 7294 #define regBIF_PF_DSTATE_INTR_MASK_BASE_IDX 5 7295 #define regBIF_PF_FLR_RST 0xe040 7296 #define regBIF_PF_FLR_RST_BASE_IDX 5 7297 #define regBIF_DEV0_PF0_DSTATE_VALUE 0xe050 7298 #define regBIF_DEV0_PF0_DSTATE_VALUE_BASE_IDX 5 7299 #define regBIF_DEV0_PF1_DSTATE_VALUE 0xe051 7300 #define regBIF_DEV0_PF1_DSTATE_VALUE_BASE_IDX 5 7301 #define regBIF_DEV0_PF2_DSTATE_VALUE 0xe052 7302 #define regBIF_DEV0_PF2_DSTATE_VALUE_BASE_IDX 5 7303 #define regBIF_DEV0_PF3_DSTATE_VALUE 0xe053 7304 #define regBIF_DEV0_PF3_DSTATE_VALUE_BASE_IDX 5 7305 #define regBIF_DEV0_PF4_DSTATE_VALUE 0xe054 7306 #define regBIF_DEV0_PF4_DSTATE_VALUE_BASE_IDX 5 7307 #define regBIF_DEV0_PF5_DSTATE_VALUE 0xe055 7308 #define regBIF_DEV0_PF5_DSTATE_VALUE_BASE_IDX 5 7309 #define regBIF_DEV0_PF6_DSTATE_VALUE 0xe056 7310 #define regBIF_DEV0_PF6_DSTATE_VALUE_BASE_IDX 5 7311 #define regDEV0_PF0_D3HOTD0_RST_CTRL 0xe078 7312 #define regDEV0_PF0_D3HOTD0_RST_CTRL_BASE_IDX 5 7313 #define regDEV0_PF1_D3HOTD0_RST_CTRL 0xe079 7314 #define regDEV0_PF1_D3HOTD0_RST_CTRL_BASE_IDX 5 7315 #define regDEV0_PF2_D3HOTD0_RST_CTRL 0xe07a 7316 #define regDEV0_PF2_D3HOTD0_RST_CTRL_BASE_IDX 5 7317 #define regDEV0_PF3_D3HOTD0_RST_CTRL 0xe07b 7318 #define regDEV0_PF3_D3HOTD0_RST_CTRL_BASE_IDX 5 7319 #define regDEV0_PF4_D3HOTD0_RST_CTRL 0xe07c 7320 #define regDEV0_PF4_D3HOTD0_RST_CTRL_BASE_IDX 5 7321 #define regDEV0_PF5_D3HOTD0_RST_CTRL 0xe07d 7322 #define regDEV0_PF5_D3HOTD0_RST_CTRL_BASE_IDX 5 7323 #define regDEV0_PF6_D3HOTD0_RST_CTRL 0xe07e 7324 #define regDEV0_PF6_D3HOTD0_RST_CTRL_BASE_IDX 5 7325 #define regBIF_PORT0_DSTATE_VALUE 0xe230 7326 #define regBIF_PORT0_DSTATE_VALUE_BASE_IDX 5 7327 #define regBIF_USB_SHUB_RS_RESET_CNTL 0xe231 7328 #define regBIF_USB_SHUB_RS_RESET_CNTL_BASE_IDX 5 7329 7330 7331 // addressBlock: nbif_bif_misc_bif_misc_regblk 7332 // base address: 0x10100000 7333 #define regREGS_ROM_OFFSET_CTRL 0xcc23 7334 #define regREGS_ROM_OFFSET_CTRL_BASE_IDX 5 7335 #define regNBIF_STRAP_BIOS_CNTL 0xcc81 7336 #define regNBIF_STRAP_BIOS_CNTL_BASE_IDX 5 7337 #define regMISC_SCRATCH 0xe800 7338 #define regMISC_SCRATCH_BASE_IDX 5 7339 #define regINTR_LINE_POLARITY 0xe801 7340 #define regINTR_LINE_POLARITY_BASE_IDX 5 7341 #define regINTR_LINE_ENABLE 0xe802 7342 #define regINTR_LINE_ENABLE_BASE_IDX 5 7343 #define regOUTSTANDING_VC_ALLOC 0xe803 7344 #define regOUTSTANDING_VC_ALLOC_BASE_IDX 5 7345 #define regBIFC_MISC_CTRL0 0xe804 7346 #define regBIFC_MISC_CTRL0_BASE_IDX 5 7347 #define regBIFC_MISC_CTRL1 0xe805 7348 #define regBIFC_MISC_CTRL1_BASE_IDX 5 7349 #define regBIFC_BME_ERR_LOG_LB 0xe806 7350 #define regBIFC_BME_ERR_LOG_LB_BASE_IDX 5 7351 #define regBIFC_LC_TIMER_CTRL 0xe807 7352 #define regBIFC_LC_TIMER_CTRL_BASE_IDX 5 7353 #define regBIFC_RCCBIH_BME_ERR_LOG0 0xe808 7354 #define regBIFC_RCCBIH_BME_ERR_LOG0_BASE_IDX 5 7355 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 0xe80a 7356 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_BASE_IDX 5 7357 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 0xe80b 7358 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_BASE_IDX 5 7359 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 0xe80c 7360 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_BASE_IDX 5 7361 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 0xe80d 7362 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_BASE_IDX 5 7363 #define regBIFC_DMA_ATTR_CNTL2_DEV0 0xe81a 7364 #define regBIFC_DMA_ATTR_CNTL2_DEV0_BASE_IDX 5 7365 #define regBIFC_MISC_CTRL2 0xe822 7366 #define regBIFC_MISC_CTRL2_BASE_IDX 5 7367 #define regBME_DUMMY_CNTL_0 0xe825 7368 #define regBME_DUMMY_CNTL_0_BASE_IDX 5 7369 #define regBIFC_THT_CNTL 0xe827 7370 #define regBIFC_THT_CNTL_BASE_IDX 5 7371 #define regBIFC_HSTARB_CNTL 0xe828 7372 #define regBIFC_HSTARB_CNTL_BASE_IDX 5 7373 #define regBIFC_GSI_CNTL 0xe829 7374 #define regBIFC_GSI_CNTL_BASE_IDX 5 7375 #define regBIFC_PCIEFUNC_CNTL 0xe82a 7376 #define regBIFC_PCIEFUNC_CNTL_BASE_IDX 5 7377 #define regBIFC_PASID_CHECK_DIS 0xe82b 7378 #define regBIFC_PASID_CHECK_DIS_BASE_IDX 5 7379 #define regBIFC_SDP_CNTL_0 0xe82c 7380 #define regBIFC_SDP_CNTL_0_BASE_IDX 5 7381 #define regBIFC_SDP_CNTL_1 0xe82d 7382 #define regBIFC_SDP_CNTL_1_BASE_IDX 5 7383 #define regBIFC_PASID_STS 0xe82e 7384 #define regBIFC_PASID_STS_BASE_IDX 5 7385 #define regBIFC_ATHUB_ACT_CNTL 0xe82f 7386 #define regBIFC_ATHUB_ACT_CNTL_BASE_IDX 5 7387 #define regBIFC_PERF_CNTL_0 0xe830 7388 #define regBIFC_PERF_CNTL_0_BASE_IDX 5 7389 #define regBIFC_PERF_CNTL_1 0xe831 7390 #define regBIFC_PERF_CNTL_1_BASE_IDX 5 7391 #define regBIFC_PERF_CNT_MMIO_RD_L32BIT 0xe832 7392 #define regBIFC_PERF_CNT_MMIO_RD_L32BIT_BASE_IDX 5 7393 #define regBIFC_PERF_CNT_MMIO_WR_L32BIT 0xe833 7394 #define regBIFC_PERF_CNT_MMIO_WR_L32BIT_BASE_IDX 5 7395 #define regBIFC_PERF_CNT_DMA_RD_L32BIT 0xe834 7396 #define regBIFC_PERF_CNT_DMA_RD_L32BIT_BASE_IDX 5 7397 #define regBIFC_PERF_CNT_DMA_WR_L32BIT 0xe835 7398 #define regBIFC_PERF_CNT_DMA_WR_L32BIT_BASE_IDX 5 7399 #define regNBIF_REGIF_ERRSET_CTRL 0xe836 7400 #define regNBIF_REGIF_ERRSET_CTRL_BASE_IDX 5 7401 #define regBIFC_SDP_CNTL_2 0xe837 7402 #define regBIFC_SDP_CNTL_2_BASE_IDX 5 7403 #define regNBIF_PGMST_CTRL 0xe838 7404 #define regNBIF_PGMST_CTRL_BASE_IDX 5 7405 #define regNBIF_PGSLV_CTRL 0xe839 7406 #define regNBIF_PGSLV_CTRL_BASE_IDX 5 7407 #define regNBIF_PG_MISC_CTRL 0xe83a 7408 #define regNBIF_PG_MISC_CTRL_BASE_IDX 5 7409 #define regSMN_MST_EP_CNTL3 0xe83c 7410 #define regSMN_MST_EP_CNTL3_BASE_IDX 5 7411 #define regSMN_MST_EP_CNTL4 0xe83d 7412 #define regSMN_MST_EP_CNTL4_BASE_IDX 5 7413 #define regSMN_MST_CNTL1 0xe83e 7414 #define regSMN_MST_CNTL1_BASE_IDX 5 7415 #define regSMN_MST_EP_CNTL5 0xe83f 7416 #define regSMN_MST_EP_CNTL5_BASE_IDX 5 7417 #define regBIF_SELFRING_BUFFER_VID 0xe840 7418 #define regBIF_SELFRING_BUFFER_VID_BASE_IDX 5 7419 #define regBIF_SELFRING_VECTOR_CNTL 0xe841 7420 #define regBIF_SELFRING_VECTOR_CNTL_BASE_IDX 5 7421 #define regNBIF_STRAP_WRITE_CTRL 0xe845 7422 #define regNBIF_STRAP_WRITE_CTRL_BASE_IDX 5 7423 #define regNBIF_INTX_DSTATE_MISC_CNTL 0xe846 7424 #define regNBIF_INTX_DSTATE_MISC_CNTL_BASE_IDX 5 7425 #define regNBIF_PENDING_MISC_CNTL 0xe847 7426 #define regNBIF_PENDING_MISC_CNTL_BASE_IDX 5 7427 #define regBIF_GMI_WRR_WEIGHT 0xe848 7428 #define regBIF_GMI_WRR_WEIGHT_BASE_IDX 5 7429 #define regBIF_GMI_WRR_WEIGHT2 0xe849 7430 #define regBIF_GMI_WRR_WEIGHT2_BASE_IDX 5 7431 #define regBIF_GMI_WRR_WEIGHT3 0xe84a 7432 #define regBIF_GMI_WRR_WEIGHT3_BASE_IDX 5 7433 #define regNBIF_PWRBRK_REQUEST 0xe84c 7434 #define regNBIF_PWRBRK_REQUEST_BASE_IDX 5 7435 #define regBIF_ATOMIC_ERR_LOG_DEV0_F0 0xe850 7436 #define regBIF_ATOMIC_ERR_LOG_DEV0_F0_BASE_IDX 5 7437 #define regBIF_ATOMIC_ERR_LOG_DEV0_F1 0xe851 7438 #define regBIF_ATOMIC_ERR_LOG_DEV0_F1_BASE_IDX 5 7439 #define regBIF_ATOMIC_ERR_LOG_DEV0_F2 0xe852 7440 #define regBIF_ATOMIC_ERR_LOG_DEV0_F2_BASE_IDX 5 7441 #define regBIF_ATOMIC_ERR_LOG_DEV0_F3 0xe853 7442 #define regBIF_ATOMIC_ERR_LOG_DEV0_F3_BASE_IDX 5 7443 #define regBIF_ATOMIC_ERR_LOG_DEV0_F4 0xe854 7444 #define regBIF_ATOMIC_ERR_LOG_DEV0_F4_BASE_IDX 5 7445 #define regBIF_ATOMIC_ERR_LOG_DEV0_F5 0xe855 7446 #define regBIF_ATOMIC_ERR_LOG_DEV0_F5_BASE_IDX 5 7447 #define regBIF_ATOMIC_ERR_LOG_DEV0_F6 0xe856 7448 #define regBIF_ATOMIC_ERR_LOG_DEV0_F6_BASE_IDX 5 7449 #define regBIF_DMA_MP4_ERR_LOG 0xe870 7450 #define regBIF_DMA_MP4_ERR_LOG_BASE_IDX 5 7451 #define regBIF_PASID_ERR_LOG 0xe871 7452 #define regBIF_PASID_ERR_LOG_BASE_IDX 5 7453 #define regBIF_PASID_ERR_CLR 0xe872 7454 #define regBIF_PASID_ERR_CLR_BASE_IDX 5 7455 #define regNBIF_VWIRE_CTRL 0xe880 7456 #define regNBIF_VWIRE_CTRL_BASE_IDX 5 7457 #define regNBIF_SMN_VWR_VCHG_DIS_CTRL 0xe881 7458 #define regNBIF_SMN_VWR_VCHG_DIS_CTRL_BASE_IDX 5 7459 #define regNBIF_SMN_VWR_VCHG_RST_CTRL0 0xe882 7460 #define regNBIF_SMN_VWR_VCHG_RST_CTRL0_BASE_IDX 5 7461 #define regNBIF_SMN_VWR_VCHG_TRIG 0xe884 7462 #define regNBIF_SMN_VWR_VCHG_TRIG_BASE_IDX 5 7463 #define regNBIF_SMN_VWR_WTRIG_CNTL 0xe885 7464 #define regNBIF_SMN_VWR_WTRIG_CNTL_BASE_IDX 5 7465 #define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1 0xe886 7466 #define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1_BASE_IDX 5 7467 #define regNBIF_MGCG_CTRL_LCLK 0xe887 7468 #define regNBIF_MGCG_CTRL_LCLK_BASE_IDX 5 7469 #define regNBIF_DS_CTRL_LCLK 0xe888 7470 #define regNBIF_DS_CTRL_LCLK_BASE_IDX 5 7471 #define regSMN_MST_CNTL0 0xe889 7472 #define regSMN_MST_CNTL0_BASE_IDX 5 7473 #define regSMN_MST_EP_CNTL1 0xe88a 7474 #define regSMN_MST_EP_CNTL1_BASE_IDX 5 7475 #define regSMN_MST_EP_CNTL2 0xe88b 7476 #define regSMN_MST_EP_CNTL2_BASE_IDX 5 7477 #define regNBIF_SDP_VWR_VCHG_DIS_CTRL 0xe88c 7478 #define regNBIF_SDP_VWR_VCHG_DIS_CTRL_BASE_IDX 5 7479 #define regNBIF_SDP_VWR_VCHG_RST_CTRL0 0xe88d 7480 #define regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX 5 7481 #define regNBIF_SDP_VWR_VCHG_RST_CTRL1 0xe88e 7482 #define regNBIF_SDP_VWR_VCHG_RST_CTRL1_BASE_IDX 5 7483 #define regNBIF_SDP_VWR_VCHG_TRIG 0xe88f 7484 #define regNBIF_SDP_VWR_VCHG_TRIG_BASE_IDX 5 7485 #define regNBIF_SHUB_TODET_CTRL 0xe898 7486 #define regNBIF_SHUB_TODET_CTRL_BASE_IDX 5 7487 #define regNBIF_SHUB_TODET_CLIENT_CTRL 0xe899 7488 #define regNBIF_SHUB_TODET_CLIENT_CTRL_BASE_IDX 5 7489 #define regNBIF_SHUB_TODET_CLIENT_STATUS 0xe89a 7490 #define regNBIF_SHUB_TODET_CLIENT_STATUS_BASE_IDX 5 7491 #define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL 0xe89b 7492 #define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL_BASE_IDX 5 7493 #define regNBIF_SHUB_TODET_CLIENT_CTRL2 0xe89c 7494 #define regNBIF_SHUB_TODET_CLIENT_CTRL2_BASE_IDX 5 7495 #define regNBIF_SHUB_TODET_CLIENT_STATUS2 0xe89d 7496 #define regNBIF_SHUB_TODET_CLIENT_STATUS2_BASE_IDX 5 7497 #define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2 0xe89e 7498 #define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2_BASE_IDX 5 7499 #define regBIFC_BME_ERR_LOG_HB 0xe8ab 7500 #define regBIFC_BME_ERR_LOG_HB_BASE_IDX 5 7501 #define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC 0xe8c0 7502 #define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC_BASE_IDX 5 7503 #define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC 0xe8c1 7504 #define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC_BASE_IDX 5 7505 #define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC 0xe8c2 7506 #define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX 5 7507 #define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC 0xe8c3 7508 #define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX 5 7509 #define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC 0xe8c4 7510 #define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC_BASE_IDX 5 7511 #define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC 0xe8c5 7512 #define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC_BASE_IDX 5 7513 #define regDISCON_HYSTERESIS_HEAD_CTRL 0xe8c6 7514 #define regDISCON_HYSTERESIS_HEAD_CTRL_BASE_IDX 5 7515 #define regBIFC_EARLY_WAKEUP_CNTL 0xe8d2 7516 #define regBIFC_EARLY_WAKEUP_CNTL_BASE_IDX 5 7517 #define regBIFC_PERF_CNT_MMIO_RD_H16BIT 0xe8f0 7518 #define regBIFC_PERF_CNT_MMIO_RD_H16BIT_BASE_IDX 5 7519 #define regBIFC_PERF_CNT_MMIO_WR_H16BIT 0xe8f1 7520 #define regBIFC_PERF_CNT_MMIO_WR_H16BIT_BASE_IDX 5 7521 #define regBIFC_PERF_CNT_DMA_RD_H16BIT 0xe8f2 7522 #define regBIFC_PERF_CNT_DMA_RD_H16BIT_BASE_IDX 5 7523 #define regBIFC_PERF_CNT_DMA_WR_H16BIT 0xe8f3 7524 #define regBIFC_PERF_CNT_DMA_WR_H16BIT_BASE_IDX 5 7525 #define regNBIF_PERF_COM_COUNT_ENABLE 0xe8f4 7526 #define regNBIF_PERF_COM_COUNT_ENABLE_BASE_IDX 5 7527 #define regNBIF_BX_PERF_CNT_FSM 0xe8ff 7528 #define regNBIF_BX_PERF_CNT_FSM_BASE_IDX 5 7529 #define regNBIF_COM_COUNT_VALUE 0xe908 7530 #define regNBIF_COM_COUNT_VALUE_BASE_IDX 5 7531 #define regBIFC_A2S_SDP_PORT_CTRL 0xeb00 7532 #define regBIFC_A2S_SDP_PORT_CTRL_BASE_IDX 5 7533 #define regBIFC_A2S_CNTL_SW0 0xeb01 7534 #define regBIFC_A2S_CNTL_SW0_BASE_IDX 5 7535 #define regBIFC_A2S_MISC_CNTL 0xeb02 7536 #define regBIFC_A2S_MISC_CNTL_BASE_IDX 5 7537 #define regBIFC_A2S_TAG_ALLOC_0 0xeb03 7538 #define regBIFC_A2S_TAG_ALLOC_0_BASE_IDX 5 7539 #define regBIFC_A2S_TAG_ALLOC_1 0xeb04 7540 #define regBIFC_A2S_TAG_ALLOC_1_BASE_IDX 5 7541 7542 7543 // addressBlock: nbif_bif_ras_bif_ras_regblk 7544 // base address: 0x10100000 7545 #define regBIFL_RAS_CENTRAL_CNTL 0xe400 7546 #define regBIFL_RAS_CENTRAL_CNTL_BASE_IDX 5 7547 #define regBIFL_RAS_CENTRAL_STATUS 0xe410 7548 #define regBIFL_RAS_CENTRAL_STATUS_BASE_IDX 5 7549 #define regBIFL_RAS_LEAF0_CTRL 0xe420 7550 #define regBIFL_RAS_LEAF0_CTRL_BASE_IDX 5 7551 #define regBIFL_RAS_LEAF1_CTRL 0xe421 7552 #define regBIFL_RAS_LEAF1_CTRL_BASE_IDX 5 7553 #define regBIFL_RAS_LEAF2_CTRL 0xe422 7554 #define regBIFL_RAS_LEAF2_CTRL_BASE_IDX 5 7555 #define regBIFL_RAS_LEAF3_CTRL 0xe423 7556 #define regBIFL_RAS_LEAF3_CTRL_BASE_IDX 5 7557 #define regBIFL_RAS_LEAF0_STATUS 0xe430 7558 #define regBIFL_RAS_LEAF0_STATUS_BASE_IDX 5 7559 #define regBIFL_RAS_LEAF1_STATUS 0xe431 7560 #define regBIFL_RAS_LEAF1_STATUS_BASE_IDX 5 7561 #define regBIFL_RAS_LEAF2_STATUS 0xe432 7562 #define regBIFL_RAS_LEAF2_STATUS_BASE_IDX 5 7563 #define regBIFL_RAS_LEAF3_STATUS 0xe433 7564 #define regBIFL_RAS_LEAF3_STATUS_BASE_IDX 5 7565 #define regBIFL_IOHUB_RAS_IH_CNTL 0xe7fe 7566 #define regBIFL_IOHUB_RAS_IH_CNTL_BASE_IDX 5 7567 #define regBIFL_RAS_VWR_FROM_IOHUB 0xe7ff 7568 #define regBIFL_RAS_VWR_FROM_IOHUB_BASE_IDX 5 7569 7570 7571 // addressBlock: nbif_rcc_dwn_dev0_BIFDEC1 7572 // base address: 0x10120000 7573 #define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED 0x8d80 7574 #define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED_BASE_IDX 5 7575 #define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH 0x8d81 7576 #define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH_BASE_IDX 5 7577 #define regRCC_DWN_DEV0_2_DN_PCIE_CNTL 0x8d83 7578 #define regRCC_DWN_DEV0_2_DN_PCIE_CNTL_BASE_IDX 5 7579 #define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL 0x8d84 7580 #define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL_BASE_IDX 5 7581 #define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 0x8d85 7582 #define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2_BASE_IDX 5 7583 #define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL 0x8d86 7584 #define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL_BASE_IDX 5 7585 #define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL 0x8d87 7586 #define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL_BASE_IDX 5 7587 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0 0x8d88 7588 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0_BASE_IDX 5 7589 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC 0x8d89 7590 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC_BASE_IDX 5 7591 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2 0x8d8a 7592 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2_BASE_IDX 5 7593 7594 7595 // addressBlock: nbif_rcc_dwnp_dev0_BIFDEC1 7596 // base address: 0x10120000 7597 #define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL 0x8d8c 7598 #define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL_BASE_IDX 5 7599 #define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL 0x8d8d 7600 #define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL_BASE_IDX 5 7601 #define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL 0x8d8e 7602 #define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL_BASE_IDX 5 7603 #define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2 0x8d8f 7604 #define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2_BASE_IDX 5 7605 #define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC 0x8d90 7606 #define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC_BASE_IDX 5 7607 #define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP 0x8d91 7608 #define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP_BASE_IDX 5 7609 7610 7611 // addressBlock: nbif_rcc_ep_dev0_BIFDEC1 7612 // base address: 0x10120000 7613 #define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH 0x8d61 7614 #define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH_BASE_IDX 5 7615 #define regRCC_EP_DEV0_2_EP_PCIE_CNTL 0x8d63 7616 #define regRCC_EP_DEV0_2_EP_PCIE_CNTL_BASE_IDX 5 7617 #define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL 0x8d64 7618 #define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL_BASE_IDX 5 7619 #define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS 0x8d65 7620 #define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS_BASE_IDX 5 7621 #define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 0x8d66 7622 #define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2_BASE_IDX 5 7623 #define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL 0x8d67 7624 #define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL_BASE_IDX 5 7625 #define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL 0x8d68 7626 #define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL_BASE_IDX 5 7627 #define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL 0x8d6a 7628 #define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL_BASE_IDX 5 7629 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x8d6b 7630 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 7631 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x8d6b 7632 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 7633 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x8d6b 7634 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 7635 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x8d6b 7636 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 7637 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x8d6c 7638 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 7639 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x8d6c 7640 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 7641 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x8d6c 7642 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 7643 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x8d6c 7644 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 7645 #define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC 0x8d6d 7646 #define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC_BASE_IDX 5 7647 #define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2 0x8d6e 7648 #define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2_BASE_IDX 5 7649 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP 0x8d70 7650 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP_BASE_IDX 5 7651 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x8d71 7652 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 5 7653 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL 0x8d71 7654 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL_BASE_IDX 5 7655 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x8d71 7656 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 7657 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x8d72 7658 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 7659 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x8d72 7660 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 7661 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x8d72 7662 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 7663 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x8d72 7664 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 7665 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x8d73 7666 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 7667 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x8d73 7668 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 7669 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x8d73 7670 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 7671 #define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL 0x8d73 7672 #define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL_BASE_IDX 5 7673 #define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED 0x8d74 7674 #define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED_BASE_IDX 5 7675 #define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL 0x8d76 7676 #define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL_BASE_IDX 5 7677 #define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID 0x8d77 7678 #define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 5 7679 #define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL 0x8d78 7680 #define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL_BASE_IDX 5 7681 #define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL 0x8d79 7682 #define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL_BASE_IDX 5 7683 #define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL 0x8d7a 7684 #define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 5 7685 7686 7687 // addressBlock: nbif_rcc_dev0_BIFDEC1 7688 // base address: 0x10120000 7689 #define regRCC_DEV0_1_RCC_ERR_INT_CNTL 0x8da6 7690 #define regRCC_DEV0_1_RCC_ERR_INT_CNTL_BASE_IDX 5 7691 #define regRCC_DEV0_1_RCC_BACO_CNTL_MISC 0x8da7 7692 #define regRCC_DEV0_1_RCC_BACO_CNTL_MISC_BASE_IDX 5 7693 #define regRCC_DEV0_1_RCC_RESET_EN 0x8da8 7694 #define regRCC_DEV0_1_RCC_RESET_EN_BASE_IDX 5 7695 #define regRCC_DEV0_2_RCC_VDM_SUPPORT 0x8da9 7696 #define regRCC_DEV0_2_RCC_VDM_SUPPORT_BASE_IDX 5 7697 #define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0 0x8daa 7698 #define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 5 7699 #define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1 0x8dab 7700 #define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 5 7701 #define regRCC_DEV0_1_RCC_GPUIOV_REGION 0x8dac 7702 #define regRCC_DEV0_1_RCC_GPUIOV_REGION_BASE_IDX 5 7703 #define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN 0x8dad 7704 #define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN_BASE_IDX 5 7705 #define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL 0x8dae 7706 #define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 5 7707 #define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x8daf 7708 #define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 5 7709 #define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE 0x8daf 7710 #define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 5 7711 #define regRCC_DEV0_1_RCC_PEER_REG_RANGE0 0x8dde 7712 #define regRCC_DEV0_1_RCC_PEER_REG_RANGE0_BASE_IDX 5 7713 #define regRCC_DEV0_1_RCC_PEER_REG_RANGE1 0x8ddf 7714 #define regRCC_DEV0_1_RCC_PEER_REG_RANGE1_BASE_IDX 5 7715 #define regRCC_DEV0_2_RCC_BUS_CNTL 0x8de1 7716 #define regRCC_DEV0_2_RCC_BUS_CNTL_BASE_IDX 5 7717 #define regRCC_DEV0_1_RCC_CONFIG_CNTL 0x8de2 7718 #define regRCC_DEV0_1_RCC_CONFIG_CNTL_BASE_IDX 5 7719 #define regRCC_DEV0_1_RCC_CONFIG_F0_BASE 0x8de6 7720 #define regRCC_DEV0_1_RCC_CONFIG_F0_BASE_BASE_IDX 5 7721 #define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE 0x8de7 7722 #define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE_BASE_IDX 5 7723 #define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE 0x8de8 7724 #define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 5 7725 #define regRCC_DEV0_1_RCC_XDMA_LO 0x8de9 7726 #define regRCC_DEV0_1_RCC_XDMA_LO_BASE_IDX 5 7727 #define regRCC_DEV0_1_RCC_XDMA_HI 0x8dea 7728 #define regRCC_DEV0_1_RCC_XDMA_HI_BASE_IDX 5 7729 #define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC 0x8deb 7730 #define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC_BASE_IDX 5 7731 #define regRCC_DEV0_1_RCC_BUSNUM_CNTL1 0x8dec 7732 #define regRCC_DEV0_1_RCC_BUSNUM_CNTL1_BASE_IDX 5 7733 #define regRCC_DEV0_1_RCC_BUSNUM_LIST0 0x8ded 7734 #define regRCC_DEV0_1_RCC_BUSNUM_LIST0_BASE_IDX 5 7735 #define regRCC_DEV0_1_RCC_BUSNUM_LIST1 0x8dee 7736 #define regRCC_DEV0_1_RCC_BUSNUM_LIST1_BASE_IDX 5 7737 #define regRCC_DEV0_1_RCC_BUSNUM_CNTL2 0x8def 7738 #define regRCC_DEV0_1_RCC_BUSNUM_CNTL2_BASE_IDX 5 7739 #define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM 0x8df0 7740 #define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 5 7741 #define regRCC_DEV0_1_RCC_HOST_BUSNUM 0x8df1 7742 #define regRCC_DEV0_1_RCC_HOST_BUSNUM_BASE_IDX 5 7743 #define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI 0x8df2 7744 #define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 5 7745 #define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO 0x8df3 7746 #define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 5 7747 #define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI 0x8df4 7748 #define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 5 7749 #define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO 0x8df5 7750 #define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 5 7751 #define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI 0x8df6 7752 #define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 5 7753 #define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO 0x8df7 7754 #define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 5 7755 #define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI 0x8df8 7756 #define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 5 7757 #define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO 0x8df9 7758 #define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 5 7759 #define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0 0x8dfa 7760 #define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0_BASE_IDX 5 7761 #define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1 0x8dfb 7762 #define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1_BASE_IDX 5 7763 #define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL 0x8dfd 7764 #define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL_BASE_IDX 5 7765 #define regRCC_DEV0_2_RCC_CMN_LINK_CNTL 0x8dfe 7766 #define regRCC_DEV0_2_RCC_CMN_LINK_CNTL_BASE_IDX 5 7767 #define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE 0x8dff 7768 #define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 5 7769 #define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL 0x8e00 7770 #define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL_BASE_IDX 5 7771 #define regRCC_DEV0_2_RCC_MH_ARB_CNTL 0x8e01 7772 #define regRCC_DEV0_2_RCC_MH_ARB_CNTL_BASE_IDX 5 7773 7774 7775 // addressBlock: nbif_bif_bx_SYSDEC 7776 // base address: 0x10120000 7777 #define regBIF_BX1_PCIE_INDEX 0x800c 7778 #define regBIF_BX1_PCIE_INDEX_BASE_IDX 5 7779 #define regBIF_BX1_PCIE_DATA 0x800d 7780 #define regBIF_BX1_PCIE_DATA_BASE_IDX 5 7781 #define regBIF_BX1_PCIE_INDEX2 0x800e 7782 #define regBIF_BX1_PCIE_INDEX2_BASE_IDX 5 7783 #define regBIF_BX1_PCIE_DATA2 0x800f 7784 #define regBIF_BX1_PCIE_DATA2_BASE_IDX 5 7785 #define regBIF_BX1_PCIE_INDEX_HI 0x8010 7786 #define regBIF_BX1_PCIE_INDEX_HI_BASE_IDX 5 7787 #define regBIF_BX1_PCIE_INDEX2_HI 0x8011 7788 #define regBIF_BX1_PCIE_INDEX2_HI_BASE_IDX 5 7789 #define regBIF_BX1_SBIOS_SCRATCH_0 0x8048 7790 #define regBIF_BX1_SBIOS_SCRATCH_0_BASE_IDX 5 7791 #define regBIF_BX1_SBIOS_SCRATCH_1 0x8049 7792 #define regBIF_BX1_SBIOS_SCRATCH_1_BASE_IDX 5 7793 #define regBIF_BX1_SBIOS_SCRATCH_2 0x804a 7794 #define regBIF_BX1_SBIOS_SCRATCH_2_BASE_IDX 5 7795 #define regBIF_BX1_SBIOS_SCRATCH_3 0x804b 7796 #define regBIF_BX1_SBIOS_SCRATCH_3_BASE_IDX 5 7797 #define regBIF_BX1_BIOS_SCRATCH_0 0x804c 7798 #define regBIF_BX1_BIOS_SCRATCH_0_BASE_IDX 5 7799 #define regBIF_BX1_BIOS_SCRATCH_1 0x804d 7800 #define regBIF_BX1_BIOS_SCRATCH_1_BASE_IDX 5 7801 #define regBIF_BX1_BIOS_SCRATCH_2 0x804e 7802 #define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX 5 7803 #define regBIF_BX1_BIOS_SCRATCH_3 0x804f 7804 #define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX 5 7805 #define regBIF_BX1_BIOS_SCRATCH_4 0x8050 7806 #define regBIF_BX1_BIOS_SCRATCH_4_BASE_IDX 5 7807 #define regBIF_BX1_BIOS_SCRATCH_5 0x8051 7808 #define regBIF_BX1_BIOS_SCRATCH_5_BASE_IDX 5 7809 #define regBIF_BX1_BIOS_SCRATCH_6 0x8052 7810 #define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX 5 7811 #define regBIF_BX1_BIOS_SCRATCH_7 0x8053 7812 #define regBIF_BX1_BIOS_SCRATCH_7_BASE_IDX 5 7813 #define regBIF_BX1_BIOS_SCRATCH_8 0x8054 7814 #define regBIF_BX1_BIOS_SCRATCH_8_BASE_IDX 5 7815 #define regBIF_BX1_BIOS_SCRATCH_9 0x8055 7816 #define regBIF_BX1_BIOS_SCRATCH_9_BASE_IDX 5 7817 #define regBIF_BX1_BIOS_SCRATCH_10 0x8056 7818 #define regBIF_BX1_BIOS_SCRATCH_10_BASE_IDX 5 7819 #define regBIF_BX1_BIOS_SCRATCH_11 0x8057 7820 #define regBIF_BX1_BIOS_SCRATCH_11_BASE_IDX 5 7821 #define regBIF_BX1_BIOS_SCRATCH_12 0x8058 7822 #define regBIF_BX1_BIOS_SCRATCH_12_BASE_IDX 5 7823 #define regBIF_BX1_BIOS_SCRATCH_13 0x8059 7824 #define regBIF_BX1_BIOS_SCRATCH_13_BASE_IDX 5 7825 #define regBIF_BX1_BIOS_SCRATCH_14 0x805a 7826 #define regBIF_BX1_BIOS_SCRATCH_14_BASE_IDX 5 7827 #define regBIF_BX1_BIOS_SCRATCH_15 0x805b 7828 #define regBIF_BX1_BIOS_SCRATCH_15_BASE_IDX 5 7829 #define regBIF_BX1_BIF_RLC_INTR_CNTL 0x8060 7830 #define regBIF_BX1_BIF_RLC_INTR_CNTL_BASE_IDX 5 7831 #define regBIF_BX1_BIF_VCE_INTR_CNTL 0x8061 7832 #define regBIF_BX1_BIF_VCE_INTR_CNTL_BASE_IDX 5 7833 #define regBIF_BX1_BIF_UVD_INTR_CNTL 0x8062 7834 #define regBIF_BX1_BIF_UVD_INTR_CNTL_BASE_IDX 5 7835 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0 0x8080 7836 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 5 7837 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 0x8081 7838 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 5 7839 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1 0x8082 7840 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 5 7841 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 0x8083 7842 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 5 7843 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2 0x8084 7844 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 5 7845 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 0x8085 7846 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 5 7847 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3 0x8086 7848 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 5 7849 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 0x8087 7850 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 5 7851 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4 0x8088 7852 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 5 7853 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 0x8089 7854 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 5 7855 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5 0x808a 7856 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 5 7857 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 0x808b 7858 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 5 7859 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6 0x808c 7860 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 5 7861 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 0x808d 7862 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 5 7863 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7 0x808e 7864 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 5 7865 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 0x808f 7866 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 5 7867 #define regBIF_BX1_GFX_MMIOREG_CAM_CNTL 0x8090 7868 #define regBIF_BX1_GFX_MMIOREG_CAM_CNTL_BASE_IDX 5 7869 #define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL 0x8091 7870 #define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 5 7871 #define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL 0x8092 7872 #define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 5 7873 #define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x8093 7874 #define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 5 7875 #define regBIF_BX1_DRIVER_SCRATCH_0 0x8094 7876 #define regBIF_BX1_DRIVER_SCRATCH_0_BASE_IDX 5 7877 #define regBIF_BX1_DRIVER_SCRATCH_1 0x8095 7878 #define regBIF_BX1_DRIVER_SCRATCH_1_BASE_IDX 5 7879 #define regBIF_BX1_DRIVER_SCRATCH_2 0x8096 7880 #define regBIF_BX1_DRIVER_SCRATCH_2_BASE_IDX 5 7881 #define regBIF_BX1_DRIVER_SCRATCH_3 0x8097 7882 #define regBIF_BX1_DRIVER_SCRATCH_3_BASE_IDX 5 7883 #define regBIF_BX1_DRIVER_SCRATCH_4 0x8098 7884 #define regBIF_BX1_DRIVER_SCRATCH_4_BASE_IDX 5 7885 #define regBIF_BX1_DRIVER_SCRATCH_5 0x8099 7886 #define regBIF_BX1_DRIVER_SCRATCH_5_BASE_IDX 5 7887 #define regBIF_BX1_DRIVER_SCRATCH_6 0x809a 7888 #define regBIF_BX1_DRIVER_SCRATCH_6_BASE_IDX 5 7889 #define regBIF_BX1_DRIVER_SCRATCH_7 0x809b 7890 #define regBIF_BX1_DRIVER_SCRATCH_7_BASE_IDX 5 7891 #define regBIF_BX1_DRIVER_SCRATCH_8 0x809c 7892 #define regBIF_BX1_DRIVER_SCRATCH_8_BASE_IDX 5 7893 #define regBIF_BX1_DRIVER_SCRATCH_9 0x809d 7894 #define regBIF_BX1_DRIVER_SCRATCH_9_BASE_IDX 5 7895 #define regBIF_BX1_DRIVER_SCRATCH_10 0x809e 7896 #define regBIF_BX1_DRIVER_SCRATCH_10_BASE_IDX 5 7897 #define regBIF_BX1_DRIVER_SCRATCH_11 0x809f 7898 #define regBIF_BX1_DRIVER_SCRATCH_11_BASE_IDX 5 7899 #define regBIF_BX1_DRIVER_SCRATCH_12 0x80a0 7900 #define regBIF_BX1_DRIVER_SCRATCH_12_BASE_IDX 5 7901 #define regBIF_BX1_DRIVER_SCRATCH_13 0x80a1 7902 #define regBIF_BX1_DRIVER_SCRATCH_13_BASE_IDX 5 7903 #define regBIF_BX1_DRIVER_SCRATCH_14 0x80a2 7904 #define regBIF_BX1_DRIVER_SCRATCH_14_BASE_IDX 5 7905 #define regBIF_BX1_DRIVER_SCRATCH_15 0x80a3 7906 #define regBIF_BX1_DRIVER_SCRATCH_15_BASE_IDX 5 7907 #define regBIF_BX1_FW_SCRATCH_0 0x80a4 7908 #define regBIF_BX1_FW_SCRATCH_0_BASE_IDX 5 7909 #define regBIF_BX1_FW_SCRATCH_1 0x80a5 7910 #define regBIF_BX1_FW_SCRATCH_1_BASE_IDX 5 7911 #define regBIF_BX1_FW_SCRATCH_2 0x80a6 7912 #define regBIF_BX1_FW_SCRATCH_2_BASE_IDX 5 7913 #define regBIF_BX1_FW_SCRATCH_3 0x80a7 7914 #define regBIF_BX1_FW_SCRATCH_3_BASE_IDX 5 7915 #define regBIF_BX1_FW_SCRATCH_4 0x80a8 7916 #define regBIF_BX1_FW_SCRATCH_4_BASE_IDX 5 7917 #define regBIF_BX1_FW_SCRATCH_5 0x80a9 7918 #define regBIF_BX1_FW_SCRATCH_5_BASE_IDX 5 7919 #define regBIF_BX1_FW_SCRATCH_6 0x80aa 7920 #define regBIF_BX1_FW_SCRATCH_6_BASE_IDX 5 7921 #define regBIF_BX1_FW_SCRATCH_7 0x80ab 7922 #define regBIF_BX1_FW_SCRATCH_7_BASE_IDX 5 7923 #define regBIF_BX1_FW_SCRATCH_8 0x80ac 7924 #define regBIF_BX1_FW_SCRATCH_8_BASE_IDX 5 7925 #define regBIF_BX1_FW_SCRATCH_9 0x80ad 7926 #define regBIF_BX1_FW_SCRATCH_9_BASE_IDX 5 7927 #define regBIF_BX1_FW_SCRATCH_10 0x80ae 7928 #define regBIF_BX1_FW_SCRATCH_10_BASE_IDX 5 7929 #define regBIF_BX1_FW_SCRATCH_11 0x80af 7930 #define regBIF_BX1_FW_SCRATCH_11_BASE_IDX 5 7931 #define regBIF_BX1_FW_SCRATCH_12 0x80b0 7932 #define regBIF_BX1_FW_SCRATCH_12_BASE_IDX 5 7933 #define regBIF_BX1_FW_SCRATCH_13 0x80b1 7934 #define regBIF_BX1_FW_SCRATCH_13_BASE_IDX 5 7935 #define regBIF_BX1_FW_SCRATCH_14 0x80b2 7936 #define regBIF_BX1_FW_SCRATCH_14_BASE_IDX 5 7937 #define regBIF_BX1_FW_SCRATCH_15 0x80b3 7938 #define regBIF_BX1_FW_SCRATCH_15_BASE_IDX 5 7939 #define regBIF_BX1_SBIOS_SCRATCH_4 0x80b4 7940 #define regBIF_BX1_SBIOS_SCRATCH_4_BASE_IDX 5 7941 #define regBIF_BX1_SBIOS_SCRATCH_5 0x80b5 7942 #define regBIF_BX1_SBIOS_SCRATCH_5_BASE_IDX 5 7943 #define regBIF_BX1_SBIOS_SCRATCH_6 0x80b6 7944 #define regBIF_BX1_SBIOS_SCRATCH_6_BASE_IDX 5 7945 #define regBIF_BX1_SBIOS_SCRATCH_7 0x80b7 7946 #define regBIF_BX1_SBIOS_SCRATCH_7_BASE_IDX 5 7947 #define regBIF_BX1_SBIOS_SCRATCH_8 0x80b8 7948 #define regBIF_BX1_SBIOS_SCRATCH_8_BASE_IDX 5 7949 #define regBIF_BX1_SBIOS_SCRATCH_9 0x80b9 7950 #define regBIF_BX1_SBIOS_SCRATCH_9_BASE_IDX 5 7951 #define regBIF_BX1_SBIOS_SCRATCH_10 0x80ba 7952 #define regBIF_BX1_SBIOS_SCRATCH_10_BASE_IDX 5 7953 #define regBIF_BX1_SBIOS_SCRATCH_11 0x80bb 7954 #define regBIF_BX1_SBIOS_SCRATCH_11_BASE_IDX 5 7955 #define regBIF_BX1_SBIOS_SCRATCH_12 0x80bc 7956 #define regBIF_BX1_SBIOS_SCRATCH_12_BASE_IDX 5 7957 #define regBIF_BX1_SBIOS_SCRATCH_13 0x80bd 7958 #define regBIF_BX1_SBIOS_SCRATCH_13_BASE_IDX 5 7959 #define regBIF_BX1_SBIOS_SCRATCH_14 0x80be 7960 #define regBIF_BX1_SBIOS_SCRATCH_14_BASE_IDX 5 7961 #define regBIF_BX1_SBIOS_SCRATCH_15 0x80bf 7962 #define regBIF_BX1_SBIOS_SCRATCH_15_BASE_IDX 5 7963 7964 7965 // addressBlock: nbif_bif_bx_pf_SYSPFVFDEC 7966 // base address: 0x10120000 7967 #define regBIF_BX_PF1_MM_INDEX 0x8000 7968 #define regBIF_BX_PF1_MM_INDEX_BASE_IDX 5 7969 #define regBIF_BX_PF1_MM_DATA 0x8001 7970 #define regBIF_BX_PF1_MM_DATA_BASE_IDX 5 7971 #define regBIF_BX_PF1_MM_INDEX_HI 0x8006 7972 #define regBIF_BX_PF1_MM_INDEX_HI_BASE_IDX 5 7973 #define regBIF_BX_PF1_RSMU_INDEX 0x8014 7974 #define regBIF_BX_PF1_RSMU_INDEX_BASE_IDX 5 7975 #define regBIF_BX_PF1_RSMU_DATA 0x8015 7976 #define regBIF_BX_PF1_RSMU_DATA_BASE_IDX 5 7977 7978 7979 // addressBlock: nbif_bif_bx_BIFDEC1 7980 // base address: 0x10120000 7981 #define regBIF_BX1_CC_BIF_BX_STRAP0 0x8e02 7982 #define regBIF_BX1_CC_BIF_BX_STRAP0_BASE_IDX 5 7983 #define regBIF_BX1_CC_BIF_BX_PINSTRAP0 0x8e04 7984 #define regBIF_BX1_CC_BIF_BX_PINSTRAP0_BASE_IDX 5 7985 #define regBIF_BX1_BIF_MM_INDACCESS_CNTL 0x8e06 7986 #define regBIF_BX1_BIF_MM_INDACCESS_CNTL_BASE_IDX 5 7987 #define regBIF_BX1_BUS_CNTL 0x8e07 7988 #define regBIF_BX1_BUS_CNTL_BASE_IDX 5 7989 #define regBIF_BX1_BIF_SCRATCH0 0x8e08 7990 #define regBIF_BX1_BIF_SCRATCH0_BASE_IDX 5 7991 #define regBIF_BX1_BIF_SCRATCH1 0x8e09 7992 #define regBIF_BX1_BIF_SCRATCH1_BASE_IDX 5 7993 #define regBIF_BX1_BX_RESET_EN 0x8e0d 7994 #define regBIF_BX1_BX_RESET_EN_BASE_IDX 5 7995 #define regBIF_BX1_MM_CFGREGS_CNTL 0x8e0e 7996 #define regBIF_BX1_MM_CFGREGS_CNTL_BASE_IDX 5 7997 #define regBIF_BX1_BX_RESET_CNTL 0x8e10 7998 #define regBIF_BX1_BX_RESET_CNTL_BASE_IDX 5 7999 #define regBIF_BX1_INTERRUPT_CNTL 0x8e11 8000 #define regBIF_BX1_INTERRUPT_CNTL_BASE_IDX 5 8001 #define regBIF_BX1_INTERRUPT_CNTL2 0x8e12 8002 #define regBIF_BX1_INTERRUPT_CNTL2_BASE_IDX 5 8003 #define regBIF_BX1_CLKREQB_PAD_CNTL 0x8e18 8004 #define regBIF_BX1_CLKREQB_PAD_CNTL_BASE_IDX 5 8005 #define regBIF_BX1_BIF_FEATURES_CONTROL_MISC 0x8e1b 8006 #define regBIF_BX1_BIF_FEATURES_CONTROL_MISC_BASE_IDX 5 8007 #define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC 0x8e1c 8008 #define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 5 8009 #define regBIF_BX1_BIF_DOORBELL_CNTL 0x8e1d 8010 #define regBIF_BX1_BIF_DOORBELL_CNTL_BASE_IDX 5 8011 #define regBIF_BX1_BIF_DOORBELL_INT_CNTL 0x8e1e 8012 #define regBIF_BX1_BIF_DOORBELL_INT_CNTL_BASE_IDX 5 8013 #define regBIF_BX1_BIF_FB_EN 0x8e20 8014 #define regBIF_BX1_BIF_FB_EN_BASE_IDX 5 8015 #define regBIF_BX1_BIF_INTR_CNTL 0x8e21 8016 #define regBIF_BX1_BIF_INTR_CNTL_BASE_IDX 5 8017 #define regBIF_BX1_BIF_MST_TRANS_PENDING_VF 0x8e29 8018 #define regBIF_BX1_BIF_MST_TRANS_PENDING_VF_BASE_IDX 5 8019 #define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF 0x8e2a 8020 #define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 5 8021 #define regBIF_BX1_BACO_CNTL 0x8e2b 8022 #define regBIF_BX1_BACO_CNTL_BASE_IDX 5 8023 #define regBIF_BX1_BIF_BACO_EXIT_TIME0 0x8e2c 8024 #define regBIF_BX1_BIF_BACO_EXIT_TIME0_BASE_IDX 5 8025 #define regBIF_BX1_BIF_BACO_EXIT_TIMER1 0x8e2d 8026 #define regBIF_BX1_BIF_BACO_EXIT_TIMER1_BASE_IDX 5 8027 #define regBIF_BX1_BIF_BACO_EXIT_TIMER2 0x8e2e 8028 #define regBIF_BX1_BIF_BACO_EXIT_TIMER2_BASE_IDX 5 8029 #define regBIF_BX1_BIF_BACO_EXIT_TIMER3 0x8e2f 8030 #define regBIF_BX1_BIF_BACO_EXIT_TIMER3_BASE_IDX 5 8031 #define regBIF_BX1_BIF_BACO_EXIT_TIMER4 0x8e30 8032 #define regBIF_BX1_BIF_BACO_EXIT_TIMER4_BASE_IDX 5 8033 #define regBIF_BX1_MEM_TYPE_CNTL 0x8e31 8034 #define regBIF_BX1_MEM_TYPE_CNTL_BASE_IDX 5 8035 #define regBIF_BX1_VF_REGWR_EN 0x8e44 8036 #define regBIF_BX1_VF_REGWR_EN_BASE_IDX 5 8037 #define regBIF_BX1_VF_DOORBELL_EN 0x8e45 8038 #define regBIF_BX1_VF_DOORBELL_EN_BASE_IDX 5 8039 #define regBIF_BX1_VF_FB_EN 0x8e46 8040 #define regBIF_BX1_VF_FB_EN_BASE_IDX 5 8041 #define regBIF_BX1_VF_REGWR_STATUS 0x8e47 8042 #define regBIF_BX1_VF_REGWR_STATUS_BASE_IDX 5 8043 #define regBIF_BX1_VF_DOORBELL_STATUS 0x8e48 8044 #define regBIF_BX1_VF_DOORBELL_STATUS_BASE_IDX 5 8045 #define regBIF_BX1_VF_FB_STATUS 0x8e49 8046 #define regBIF_BX1_VF_FB_STATUS_BASE_IDX 5 8047 #define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL 0x8e4d 8048 #define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 5 8049 #define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL 0x8e4e 8050 #define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 5 8051 #define regBIF_BX1_BIF_RB_CNTL 0x8e4f 8052 #define regBIF_BX1_BIF_RB_CNTL_BASE_IDX 5 8053 #define regBIF_BX1_BIF_RB_BASE 0x8e50 8054 #define regBIF_BX1_BIF_RB_BASE_BASE_IDX 5 8055 #define regBIF_BX1_BIF_RB_RPTR 0x8e51 8056 #define regBIF_BX1_BIF_RB_RPTR_BASE_IDX 5 8057 #define regBIF_BX1_BIF_RB_WPTR 0x8e52 8058 #define regBIF_BX1_BIF_RB_WPTR_BASE_IDX 5 8059 #define regBIF_BX1_BIF_RB_WPTR_ADDR_HI 0x8e53 8060 #define regBIF_BX1_BIF_RB_WPTR_ADDR_HI_BASE_IDX 5 8061 #define regBIF_BX1_BIF_RB_WPTR_ADDR_LO 0x8e54 8062 #define regBIF_BX1_BIF_RB_WPTR_ADDR_LO_BASE_IDX 5 8063 #define regBIF_BX1_MAILBOX_INDEX 0x8e55 8064 #define regBIF_BX1_MAILBOX_INDEX_BASE_IDX 5 8065 #define regBIF_BX1_BIF_MP1_INTR_CTRL 0x8e62 8066 #define regBIF_BX1_BIF_MP1_INTR_CTRL_BASE_IDX 5 8067 #define regBIF_BX1_BIF_PERSTB_PAD_CNTL 0x8e65 8068 #define regBIF_BX1_BIF_PERSTB_PAD_CNTL_BASE_IDX 5 8069 #define regBIF_BX1_BIF_PX_EN_PAD_CNTL 0x8e66 8070 #define regBIF_BX1_BIF_PX_EN_PAD_CNTL_BASE_IDX 5 8071 #define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL 0x8e67 8072 #define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 5 8073 #define regBIF_BX1_BIF_CLKREQB_PAD_CNTL 0x8e68 8074 #define regBIF_BX1_BIF_CLKREQB_PAD_CNTL_BASE_IDX 5 8075 #define regBIF_BX1_BIF_PWRBRK_PAD_CNTL 0x8e69 8076 #define regBIF_BX1_BIF_PWRBRK_PAD_CNTL_BASE_IDX 5 8077 #define regBIF_BX1_BIF_WAKEB_PAD_CNTL 0x8e6d 8078 #define regBIF_BX1_BIF_WAKEB_PAD_CNTL_BASE_IDX 5 8079 #define regBIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL 0x8e6e 8080 #define regBIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL_BASE_IDX 5 8081 #define regBIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL 0x8e70 8082 #define regBIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL_BASE_IDX 5 8083 #define regBIF_BX1_BIF_S5_MEM_POWER_CTRL0 0x8e71 8084 #define regBIF_BX1_BIF_S5_MEM_POWER_CTRL0_BASE_IDX 5 8085 #define regBIF_BX1_BIF_S5_MEM_POWER_CTRL1 0x8e72 8086 #define regBIF_BX1_BIF_S5_MEM_POWER_CTRL1_BASE_IDX 5 8087 #define regBIF_BX1_BIF_S5_DUMMY_REGS 0x8e73 8088 #define regBIF_BX1_BIF_S5_DUMMY_REGS_BASE_IDX 5 8089 8090 8091 // addressBlock: nbif_bif_bx_pf_BIFPFVFDEC1 8092 // base address: 0x10120000 8093 #define regBIF_BX_PF1_BIF_BME_STATUS 0x8e0b 8094 #define regBIF_BX_PF1_BIF_BME_STATUS_BASE_IDX 5 8095 #define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG 0x8e0c 8096 #define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 8097 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 8098 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 8099 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 8100 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 8101 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 8102 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 8103 #define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 8104 #define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 8105 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 8106 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 8107 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 8108 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 8109 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a 8110 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 8111 #define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ 0x8e26 8112 #define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_BASE_IDX 5 8113 #define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE 0x8e27 8114 #define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_BASE_IDX 5 8115 #define regBIF_BX_PF1_BIF_TRANS_PENDING 0x8e28 8116 #define regBIF_BX_PF1_BIF_TRANS_PENDING_BASE_IDX 5 8117 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 0x8e56 8118 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 8119 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 0x8e57 8120 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 8121 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 0x8e58 8122 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 8123 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 0x8e59 8124 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 8125 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 0x8e5a 8126 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 8127 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 0x8e5b 8128 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 8129 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 0x8e5c 8130 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 8131 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 0x8e5d 8132 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 8133 #define regBIF_BX_PF1_MAILBOX_CONTROL 0x8e5e 8134 #define regBIF_BX_PF1_MAILBOX_CONTROL_BASE_IDX 5 8135 #define regBIF_BX_PF1_MAILBOX_INT_CNTL 0x8e5f 8136 #define regBIF_BX_PF1_MAILBOX_INT_CNTL_BASE_IDX 5 8137 #define regBIF_BX_PF1_BIF_VMHV_MAILBOX 0x8e60 8138 #define regBIF_BX_PF1_BIF_VMHV_MAILBOX_BASE_IDX 5 8139 8140 8141 // addressBlock: nbif_rcc_strap_BIFDEC1:1 8142 // base address: 0x10120000 8143 #define regRCC_STRAP2_RCC_BIF_STRAP0 0x8d20 8144 #define regRCC_STRAP2_RCC_BIF_STRAP0_BASE_IDX 5 8145 #define regRCC_STRAP2_RCC_BIF_STRAP1 0x8d21 8146 #define regRCC_STRAP2_RCC_BIF_STRAP1_BASE_IDX 5 8147 #define regRCC_STRAP2_RCC_BIF_STRAP2 0x8d25 8148 #define regRCC_STRAP2_RCC_BIF_STRAP2_BASE_IDX 5 8149 #define regRCC_STRAP2_RCC_BIF_STRAP3 0x8d26 8150 #define regRCC_STRAP2_RCC_BIF_STRAP3_BASE_IDX 5 8151 #define regRCC_STRAP2_RCC_BIF_STRAP4 0x8d27 8152 #define regRCC_STRAP2_RCC_BIF_STRAP4_BASE_IDX 5 8153 #define regRCC_STRAP2_RCC_BIF_STRAP5 0x8d28 8154 #define regRCC_STRAP2_RCC_BIF_STRAP5_BASE_IDX 5 8155 #define regRCC_STRAP2_RCC_BIF_STRAP6 0x8d29 8156 #define regRCC_STRAP2_RCC_BIF_STRAP6_BASE_IDX 5 8157 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0 0x8d2d 8158 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0_BASE_IDX 5 8159 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1 0x8d2e 8160 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1_BASE_IDX 5 8161 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10 0x8d2f 8162 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10_BASE_IDX 5 8163 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11 0x8d30 8164 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11_BASE_IDX 5 8165 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12 0x8d31 8166 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12_BASE_IDX 5 8167 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13 0x8d32 8168 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13_BASE_IDX 5 8169 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14 0x8d33 8170 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14_BASE_IDX 5 8171 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2 0x8d34 8172 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2_BASE_IDX 5 8173 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3 0x8d35 8174 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3_BASE_IDX 5 8175 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4 0x8d36 8176 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4_BASE_IDX 5 8177 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5 0x8d37 8178 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5_BASE_IDX 5 8179 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6 0x8d38 8180 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6_BASE_IDX 5 8181 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7 0x8d39 8182 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7_BASE_IDX 5 8183 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8 0x8d3a 8184 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8_BASE_IDX 5 8185 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9 0x8d3b 8186 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9_BASE_IDX 5 8187 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0 0x8d3c 8188 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_BASE_IDX 5 8189 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1 0x8d3d 8190 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1_BASE_IDX 5 8191 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13 0x8d3e 8192 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13_BASE_IDX 5 8193 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14 0x8d3f 8194 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14_BASE_IDX 5 8195 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15 0x8d40 8196 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15_BASE_IDX 5 8197 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16 0x8d41 8198 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16_BASE_IDX 5 8199 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17 0x8d42 8200 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17_BASE_IDX 5 8201 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18 0x8d43 8202 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18_BASE_IDX 5 8203 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2 0x8d44 8204 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2_BASE_IDX 5 8205 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3 0x8d46 8206 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3_BASE_IDX 5 8207 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4 0x8d47 8208 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4_BASE_IDX 5 8209 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5 0x8d48 8210 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5_BASE_IDX 5 8211 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8 0x8d49 8212 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8_BASE_IDX 5 8213 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9 0x8d4a 8214 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9_BASE_IDX 5 8215 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0 0x8d4b 8216 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0_BASE_IDX 5 8217 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2 0x8d56 8218 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2_BASE_IDX 5 8219 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20 0x8d57 8220 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20_BASE_IDX 5 8221 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21 0x8d58 8222 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21_BASE_IDX 5 8223 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3 0x8d59 8224 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3_BASE_IDX 5 8225 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4 0x8d5a 8226 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4_BASE_IDX 5 8227 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5 0x8d5b 8228 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5_BASE_IDX 5 8229 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6 0x8d5c 8230 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6_BASE_IDX 5 8231 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7 0x8d5d 8232 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7_BASE_IDX 5 8233 8234 8235 // addressBlock: nbif_gdc_dma_sion_SIONDEC 8236 // base address: 0x1400000 8237 #define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0 0x4f7400 8238 #define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX 3 8239 #define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1 0x4f7401 8240 #define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX 3 8241 #define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0 0x4f7402 8242 #define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX 3 8243 #define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1 0x4f7403 8244 #define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX 3 8245 #define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0 0x4f7404 8246 #define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX 3 8247 #define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1 0x4f7405 8248 #define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX 3 8249 #define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0 0x4f7406 8250 #define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX 3 8251 #define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1 0x4f7407 8252 #define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX 3 8253 #define regGDC_DMA_SION_CL0_Req_BurstTarget_REG0 0x4f7408 8254 #define regGDC_DMA_SION_CL0_Req_BurstTarget_REG0_BASE_IDX 3 8255 #define regGDC_DMA_SION_CL0_Req_BurstTarget_REG1 0x4f7409 8256 #define regGDC_DMA_SION_CL0_Req_BurstTarget_REG1_BASE_IDX 3 8257 #define regGDC_DMA_SION_CL0_Req_TimeSlot_REG0 0x4f740a 8258 #define regGDC_DMA_SION_CL0_Req_TimeSlot_REG0_BASE_IDX 3 8259 #define regGDC_DMA_SION_CL0_Req_TimeSlot_REG1 0x4f740b 8260 #define regGDC_DMA_SION_CL0_Req_TimeSlot_REG1_BASE_IDX 3 8261 #define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0 0x4f740c 8262 #define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 8263 #define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1 0x4f740d 8264 #define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 8265 #define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0 0x4f740e 8266 #define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX 3 8267 #define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1 0x4f740f 8268 #define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX 3 8269 #define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0 0x4f7410 8270 #define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 8271 #define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1 0x4f7411 8272 #define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 8273 #define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0 0x4f7412 8274 #define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 8275 #define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1 0x4f7413 8276 #define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 8277 #define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0 0x4f7414 8278 #define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX 3 8279 #define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1 0x4f7415 8280 #define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX 3 8281 #define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0 0x4f7416 8282 #define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX 3 8283 #define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1 0x4f7417 8284 #define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX 3 8285 #define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0 0x4f7418 8286 #define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX 3 8287 #define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1 0x4f7419 8288 #define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX 3 8289 #define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0 0x4f741a 8290 #define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX 3 8291 #define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1 0x4f741b 8292 #define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX 3 8293 #define regGDC_DMA_SION_CL1_Req_BurstTarget_REG0 0x4f741c 8294 #define regGDC_DMA_SION_CL1_Req_BurstTarget_REG0_BASE_IDX 3 8295 #define regGDC_DMA_SION_CL1_Req_BurstTarget_REG1 0x4f741d 8296 #define regGDC_DMA_SION_CL1_Req_BurstTarget_REG1_BASE_IDX 3 8297 #define regGDC_DMA_SION_CL1_Req_TimeSlot_REG0 0x4f741e 8298 #define regGDC_DMA_SION_CL1_Req_TimeSlot_REG0_BASE_IDX 3 8299 #define regGDC_DMA_SION_CL1_Req_TimeSlot_REG1 0x4f741f 8300 #define regGDC_DMA_SION_CL1_Req_TimeSlot_REG1_BASE_IDX 3 8301 #define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0 0x4f7420 8302 #define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 8303 #define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1 0x4f7421 8304 #define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 8305 #define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0 0x4f7422 8306 #define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX 3 8307 #define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1 0x4f7423 8308 #define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX 3 8309 #define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0 0x4f7424 8310 #define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 8311 #define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1 0x4f7425 8312 #define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 8313 #define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0 0x4f7426 8314 #define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 8315 #define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1 0x4f7427 8316 #define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 8317 #define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0 0x4f7428 8318 #define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0_BASE_IDX 3 8319 #define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1 0x4f7429 8320 #define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1_BASE_IDX 3 8321 #define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0 0x4f742a 8322 #define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0_BASE_IDX 3 8323 #define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1 0x4f742b 8324 #define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1_BASE_IDX 3 8325 #define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0 0x4f742c 8326 #define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0_BASE_IDX 3 8327 #define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1 0x4f742d 8328 #define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1_BASE_IDX 3 8329 #define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0 0x4f742e 8330 #define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0_BASE_IDX 3 8331 #define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1 0x4f742f 8332 #define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1_BASE_IDX 3 8333 #define regGDC_DMA_SION_CL2_Req_BurstTarget_REG0 0x4f7430 8334 #define regGDC_DMA_SION_CL2_Req_BurstTarget_REG0_BASE_IDX 3 8335 #define regGDC_DMA_SION_CL2_Req_BurstTarget_REG1 0x4f7431 8336 #define regGDC_DMA_SION_CL2_Req_BurstTarget_REG1_BASE_IDX 3 8337 #define regGDC_DMA_SION_CL2_Req_TimeSlot_REG0 0x4f7432 8338 #define regGDC_DMA_SION_CL2_Req_TimeSlot_REG0_BASE_IDX 3 8339 #define regGDC_DMA_SION_CL2_Req_TimeSlot_REG1 0x4f7433 8340 #define regGDC_DMA_SION_CL2_Req_TimeSlot_REG1_BASE_IDX 3 8341 #define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0 0x4f7434 8342 #define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 8343 #define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1 0x4f7435 8344 #define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 8345 #define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0 0x4f7436 8346 #define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0_BASE_IDX 3 8347 #define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1 0x4f7437 8348 #define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1_BASE_IDX 3 8349 #define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0 0x4f7438 8350 #define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 8351 #define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1 0x4f7439 8352 #define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 8353 #define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0 0x4f743a 8354 #define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 8355 #define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1 0x4f743b 8356 #define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 8357 #define regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0 0x4f743c 8358 #define regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0_BASE_IDX 3 8359 #define regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1 0x4f743d 8360 #define regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1_BASE_IDX 3 8361 #define regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0 0x4f743e 8362 #define regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0_BASE_IDX 3 8363 #define regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1 0x4f743f 8364 #define regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1_BASE_IDX 3 8365 #define regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0 0x4f7440 8366 #define regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0_BASE_IDX 3 8367 #define regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1 0x4f7441 8368 #define regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1_BASE_IDX 3 8369 #define regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0 0x4f7442 8370 #define regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0_BASE_IDX 3 8371 #define regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1 0x4f7443 8372 #define regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1_BASE_IDX 3 8373 #define regGDC_DMA_SION_CL3_Req_BurstTarget_REG0 0x4f7444 8374 #define regGDC_DMA_SION_CL3_Req_BurstTarget_REG0_BASE_IDX 3 8375 #define regGDC_DMA_SION_CL3_Req_BurstTarget_REG1 0x4f7445 8376 #define regGDC_DMA_SION_CL3_Req_BurstTarget_REG1_BASE_IDX 3 8377 #define regGDC_DMA_SION_CL3_Req_TimeSlot_REG0 0x4f7446 8378 #define regGDC_DMA_SION_CL3_Req_TimeSlot_REG0_BASE_IDX 3 8379 #define regGDC_DMA_SION_CL3_Req_TimeSlot_REG1 0x4f7447 8380 #define regGDC_DMA_SION_CL3_Req_TimeSlot_REG1_BASE_IDX 3 8381 #define regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0 0x4f7448 8382 #define regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 8383 #define regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1 0x4f7449 8384 #define regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 8385 #define regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0 0x4f744a 8386 #define regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0_BASE_IDX 3 8387 #define regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1 0x4f744b 8388 #define regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1_BASE_IDX 3 8389 #define regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0 0x4f744c 8390 #define regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 8391 #define regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1 0x4f744d 8392 #define regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 8393 #define regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0 0x4f744e 8394 #define regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 8395 #define regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1 0x4f744f 8396 #define regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 8397 #define regGDC_DMA_SION_CNTL_REG0 0x4f7450 8398 #define regGDC_DMA_SION_CNTL_REG0_BASE_IDX 3 8399 #define regGDC_DMA_SION_CNTL_REG1 0x4f7451 8400 #define regGDC_DMA_SION_CNTL_REG1_BASE_IDX 3 8401 8402 8403 // addressBlock: nbif_gdc_hst_sion_SIONDEC 8404 // base address: 0x1400000 8405 #define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0 0x4f7600 8406 #define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX 3 8407 #define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1 0x4f7601 8408 #define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX 3 8409 #define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0 0x4f7602 8410 #define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX 3 8411 #define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1 0x4f7603 8412 #define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX 3 8413 #define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0 0x4f7604 8414 #define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX 3 8415 #define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1 0x4f7605 8416 #define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX 3 8417 #define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0 0x4f7606 8418 #define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX 3 8419 #define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1 0x4f7607 8420 #define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX 3 8421 #define regGDC_HST_SION_CL0_Req_BurstTarget_REG0 0x4f7608 8422 #define regGDC_HST_SION_CL0_Req_BurstTarget_REG0_BASE_IDX 3 8423 #define regGDC_HST_SION_CL0_Req_BurstTarget_REG1 0x4f7609 8424 #define regGDC_HST_SION_CL0_Req_BurstTarget_REG1_BASE_IDX 3 8425 #define regGDC_HST_SION_CL0_Req_TimeSlot_REG0 0x4f760a 8426 #define regGDC_HST_SION_CL0_Req_TimeSlot_REG0_BASE_IDX 3 8427 #define regGDC_HST_SION_CL0_Req_TimeSlot_REG1 0x4f760b 8428 #define regGDC_HST_SION_CL0_Req_TimeSlot_REG1_BASE_IDX 3 8429 #define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0 0x4f760c 8430 #define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 8431 #define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1 0x4f760d 8432 #define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 8433 #define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0 0x4f760e 8434 #define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX 3 8435 #define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1 0x4f760f 8436 #define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX 3 8437 #define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0 0x4f7610 8438 #define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 8439 #define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1 0x4f7611 8440 #define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 8441 #define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0 0x4f7612 8442 #define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 8443 #define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1 0x4f7613 8444 #define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 8445 #define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0 0x4f7614 8446 #define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX 3 8447 #define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1 0x4f7615 8448 #define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX 3 8449 #define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0 0x4f7616 8450 #define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX 3 8451 #define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1 0x4f7617 8452 #define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX 3 8453 #define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0 0x4f7618 8454 #define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX 3 8455 #define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1 0x4f7619 8456 #define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX 3 8457 #define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0 0x4f761a 8458 #define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX 3 8459 #define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1 0x4f761b 8460 #define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX 3 8461 #define regGDC_HST_SION_CL1_Req_BurstTarget_REG0 0x4f761c 8462 #define regGDC_HST_SION_CL1_Req_BurstTarget_REG0_BASE_IDX 3 8463 #define regGDC_HST_SION_CL1_Req_BurstTarget_REG1 0x4f761d 8464 #define regGDC_HST_SION_CL1_Req_BurstTarget_REG1_BASE_IDX 3 8465 #define regGDC_HST_SION_CL1_Req_TimeSlot_REG0 0x4f761e 8466 #define regGDC_HST_SION_CL1_Req_TimeSlot_REG0_BASE_IDX 3 8467 #define regGDC_HST_SION_CL1_Req_TimeSlot_REG1 0x4f761f 8468 #define regGDC_HST_SION_CL1_Req_TimeSlot_REG1_BASE_IDX 3 8469 #define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0 0x4f7620 8470 #define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 8471 #define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1 0x4f7621 8472 #define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 8473 #define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0 0x4f7622 8474 #define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX 3 8475 #define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1 0x4f7623 8476 #define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX 3 8477 #define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0 0x4f7624 8478 #define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 8479 #define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1 0x4f7625 8480 #define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 8481 #define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0 0x4f7626 8482 #define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 8483 #define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1 0x4f7627 8484 #define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 8485 #define regGDC_HST_SION_CNTL_REG0 0x4f7628 8486 #define regGDC_HST_SION_CNTL_REG0_BASE_IDX 3 8487 #define regGDC_HST_SION_CNTL_REG1 0x4f7629 8488 #define regGDC_HST_SION_CNTL_REG1_BASE_IDX 3 8489 8490 8491 // addressBlock: nbif_gdc_GDCDEC 8492 // base address: 0x1400000 8493 #define regGDC1_SHUB_REGS_IF_CTL 0x4f0aa1 8494 #define regGDC1_SHUB_REGS_IF_CTL_BASE_IDX 3 8495 #define regGDC1_A2S_QUEUE_FIFO_ARB_CNTL 0x4f0aa2 8496 #define regGDC1_A2S_QUEUE_FIFO_ARB_CNTL_BASE_IDX 3 8497 #define regGDC1_NGDC_MGCG_CTRL 0x4f0aa7 8498 #define regGDC1_NGDC_MGCG_CTRL_BASE_IDX 3 8499 #define regGDC1_S2A_MISC_CNTL 0x4f0aa8 8500 #define regGDC1_S2A_MISC_CNTL_BASE_IDX 3 8501 #define regGDC1_NGDC_EARLY_WAKEUP_CTRL 0x4f0aac 8502 #define regGDC1_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX 3 8503 #define regGDC1_NGDC_PG_MISC_CTRL 0x4f0ab0 8504 #define regGDC1_NGDC_PG_MISC_CTRL_BASE_IDX 3 8505 #define regGDC1_NGDC_PGMST_CTRL 0x4f0ab1 8506 #define regGDC1_NGDC_PGMST_CTRL_BASE_IDX 3 8507 #define regGDC1_NGDC_PGSLV_CTRL 0x4f0ab2 8508 #define regGDC1_NGDC_PGSLV_CTRL_BASE_IDX 3 8509 #define regGDC1_ATDMA_MISC_CNTL 0x4f0b01 8510 #define regGDC1_ATDMA_MISC_CNTL_BASE_IDX 3 8511 8512 8513 // addressBlock: nbif_gdc_ras_gdc_ras_regblk 8514 // base address: 0x1400000 8515 #define regGDCSOC_ERR_RSP_CNTL 0x4f5c00 8516 #define regGDCSOC_ERR_RSP_CNTL_BASE_IDX 3 8517 #define regGDCSOC_RAS_CENTRAL_STATUS 0x4f5c10 8518 #define regGDCSOC_RAS_CENTRAL_STATUS_BASE_IDX 3 8519 #define regGDCSOC_RAS_LEAF0_CTRL 0x4f5c20 8520 #define regGDCSOC_RAS_LEAF0_CTRL_BASE_IDX 3 8521 #define regGDCSOC_RAS_LEAF1_CTRL 0x4f5c21 8522 #define regGDCSOC_RAS_LEAF1_CTRL_BASE_IDX 3 8523 #define regGDCSOC_RAS_LEAF2_CTRL 0x4f5c22 8524 #define regGDCSOC_RAS_LEAF2_CTRL_BASE_IDX 3 8525 #define regGDCSOC_RAS_LEAF3_CTRL 0x4f5c23 8526 #define regGDCSOC_RAS_LEAF3_CTRL_BASE_IDX 3 8527 #define regGDCSOC_RAS_LEAF4_CTRL 0x4f5c24 8528 #define regGDCSOC_RAS_LEAF4_CTRL_BASE_IDX 3 8529 #define regGDCSOC_RAS_LEAF2_MISC_CTRL 0x4f5c2e 8530 #define regGDCSOC_RAS_LEAF2_MISC_CTRL_BASE_IDX 3 8531 #define regGDCSOC_RAS_LEAF2_MISC_CTRL2 0x4f5c2f 8532 #define regGDCSOC_RAS_LEAF2_MISC_CTRL2_BASE_IDX 3 8533 #define regGDCSOC_RAS_LEAF0_STATUS 0x4f5c30 8534 #define regGDCSOC_RAS_LEAF0_STATUS_BASE_IDX 3 8535 #define regGDCSOC_RAS_LEAF1_STATUS 0x4f5c31 8536 #define regGDCSOC_RAS_LEAF1_STATUS_BASE_IDX 3 8537 #define regGDCSOC_RAS_LEAF2_STATUS 0x4f5c32 8538 #define regGDCSOC_RAS_LEAF2_STATUS_BASE_IDX 3 8539 #define regGDCSOC_RAS_LEAF3_STATUS 0x4f5c33 8540 #define regGDCSOC_RAS_LEAF3_STATUS_BASE_IDX 3 8541 #define regGDCSOC_RAS_LEAF4_STATUS 0x4f5c34 8542 #define regGDCSOC_RAS_LEAF4_STATUS_BASE_IDX 3 8543 8544 8545 // addressBlock: nbif_gdc_rst_GDCRST_DEC 8546 // base address: 0x1400000 8547 #define regSHUB_PF_FLR_RST 0x4f7800 8548 #define regSHUB_PF_FLR_RST_BASE_IDX 3 8549 #define regSHUB_GFX_DRV_VPU_RST 0x4f7801 8550 #define regSHUB_GFX_DRV_VPU_RST_BASE_IDX 3 8551 #define regSHUB_LINK_RESET 0x4f7802 8552 #define regSHUB_LINK_RESET_BASE_IDX 3 8553 #define regSHUB_HARD_RST_CTRL 0x4f7810 8554 #define regSHUB_HARD_RST_CTRL_BASE_IDX 3 8555 #define regSHUB_SOFT_RST_CTRL 0x4f7811 8556 #define regSHUB_SOFT_RST_CTRL_BASE_IDX 3 8557 #define regSHUB_SDP_PORT_RST 0x4f7812 8558 #define regSHUB_SDP_PORT_RST_BASE_IDX 3 8559 #define regSHUB_RST_MISC_TRL 0x4f7813 8560 #define regSHUB_RST_MISC_TRL_BASE_IDX 3 8561 8562 8563 // addressBlock: nbif_gdc_s2a_GDCS2A_DEC 8564 // base address: 0x1400000 8565 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL 0x4f0aeb 8566 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX 3 8567 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL 0x4f0aec 8568 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX 3 8569 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL 0x4f0aed 8570 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX 3 8571 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL 0x4f0aee 8572 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX 3 8573 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL 0x4f0aef 8574 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX 3 8575 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL 0x4f0af0 8576 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX 3 8577 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL 0x4f0af1 8578 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX 3 8579 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL 0x4f0af2 8580 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX 3 8581 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL 0x4f0af3 8582 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX 3 8583 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL 0x4f0af4 8584 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX 3 8585 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL 0x4f0af5 8586 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX 3 8587 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL 0x4f0af6 8588 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX 3 8589 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL 0x4f0af7 8590 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX 3 8591 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL 0x4f0af8 8592 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX 3 8593 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL 0x4f0af9 8594 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX 3 8595 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL 0x4f0afa 8596 #define regGDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX 3 8597 #define regGDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG 0x4f0afb 8598 #define regGDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX 3 8599 #define regGDC_S2A1_NBIF_GFX_DOORBELL_STATUS 0x4f0afc 8600 #define regGDC_S2A1_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 3 8601 8602 8603 // addressBlock: nbif_gdc_a2s_GDCA2S_DEC 8604 // base address: 0x1400000 8605 #define regA2S_CNTL_SW0 0x4f0c40 8606 #define regA2S_CNTL_SW0_BASE_IDX 3 8607 #define regA2S_CNTL_SW1 0x4f0c41 8608 #define regA2S_CNTL_SW1_BASE_IDX 3 8609 #define regA2S_MISC_CNTL 0x4f0c72 8610 #define regA2S_MISC_CNTL_BASE_IDX 3 8611 #define regA2S_TAG_ALLOC_0 0x4f0c74 8612 #define regA2S_TAG_ALLOC_0_BASE_IDX 3 8613 #define regA2S_TAG_ALLOC_1 0x4f0c75 8614 #define regA2S_TAG_ALLOC_1_BASE_IDX 3 8615 8616 8617 // addressBlock: nbif_syshub_mmreg_syshubdirect 8618 // base address: 0x1400000 8619 #define regHST_CLK0_SW0_CL0_CNTL 0x4f3d40 8620 #define regHST_CLK0_SW0_CL0_CNTL_BASE_IDX 3 8621 #define regHST_CLK0_SW1_CL0_CNTL 0x4f3d60 8622 #define regHST_CLK0_SW1_CL0_CNTL_BASE_IDX 3 8623 #define regDMA_CLK0_SW0_CL0_CNTL 0x4f3e40 8624 #define regDMA_CLK0_SW0_CL0_CNTL_BASE_IDX 3 8625 #define regNIC400_1_ASIB_0_FN_MOD 0x4fbc42 8626 #define regNIC400_1_ASIB_0_FN_MOD_BASE_IDX 3 8627 #define regNIC400_1_IB_0_FN_MOD 0x4ff842 8628 #define regNIC400_1_IB_0_FN_MOD_BASE_IDX 3 8629 8630 8631 // addressBlock: nbif_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 8632 // base address: 0x0 8633 #define regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0x00eb 8634 #define regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX 2 8635 #define regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0x00ec 8636 #define regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 8637 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 8638 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 8639 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 8640 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 8641 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 8642 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 8643 #define regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 8644 #define regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 8645 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 8646 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 8647 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 8648 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 8649 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 8650 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 8651 #define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0x0106 8652 #define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 8653 #define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0x0107 8654 #define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 8655 #define regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0x0108 8656 #define regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX 2 8657 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 8658 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 8659 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 8660 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 8661 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 8662 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 8663 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 8664 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 8665 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0x013a 8666 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 8667 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0x013b 8668 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 8669 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0x013c 8670 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 8671 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0x013d 8672 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 8673 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0x013e 8674 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX 2 8675 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0x013f 8676 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX 2 8677 #define regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0x0140 8678 #define regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX 2 8679 8680 8681 // addressBlock: nbif_bif_bx_dev0_epf0_vf0_SYSPFVFDEC 8682 // base address: 0x0 8683 #define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0x0000 8684 #define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX 0 8685 #define regBIF_BX_DEV0_EPF0_VF0_MM_DATA 0x0001 8686 #define regBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX 0 8687 #define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0x0006 8688 #define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX 0 8689 8690 8691 // addressBlock: nbif_rcc_dev0_epf0_vf0_BIFPFVFDEC1 8692 // base address: 0x0 8693 #define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0x0085 8694 #define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX 2 8695 #define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0x00c0 8696 #define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 8697 #define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0x00c3 8698 #define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 8699 #define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0x00c4 8700 #define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX 2 8701 #define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 8702 #define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 8703 8704 8705 // addressBlock: nbif_rcc_dev0_epf0_vf0_BIFDEC2 8706 // base address: 0x0 8707 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0x0400 8708 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 8709 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0x0401 8710 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 8711 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0x0402 8712 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 8713 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0x0403 8714 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 8715 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0x0404 8716 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 8717 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0x0405 8718 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 8719 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0x0406 8720 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 8721 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0x0407 8722 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 8723 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0x0408 8724 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 8725 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0x0409 8726 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 8727 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0x040a 8728 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 8729 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0x040b 8730 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 8731 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO 0x040c 8732 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 8733 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI 0x040d 8734 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 8735 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA 0x040e 8736 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 8737 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL 0x040f 8738 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 8739 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0x0800 8740 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX 3 8741 8742 8743 // addressBlock: nbif_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 8744 // base address: 0x0 8745 #define regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0x00eb 8746 #define regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX 2 8747 #define regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0x00ec 8748 #define regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 8749 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 8750 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 8751 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 8752 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 8753 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 8754 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 8755 #define regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 8756 #define regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 8757 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 8758 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 8759 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 8760 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 8761 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 8762 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 8763 #define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0x0106 8764 #define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 8765 #define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0x0107 8766 #define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 8767 #define regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0x0108 8768 #define regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX 2 8769 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0x0136 8770 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 8771 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0x0137 8772 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 8773 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0x0138 8774 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 8775 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0x0139 8776 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 8777 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0x013a 8778 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 8779 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0x013b 8780 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 8781 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0x013c 8782 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 8783 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0x013d 8784 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 8785 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0x013e 8786 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX 2 8787 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0x013f 8788 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX 2 8789 #define regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0x0140 8790 #define regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX 2 8791 8792 8793 // addressBlock: nbif_bif_bx_dev0_epf0_vf1_SYSPFVFDEC 8794 // base address: 0x0 8795 #define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0x0000 8796 #define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX 0 8797 #define regBIF_BX_DEV0_EPF0_VF1_MM_DATA 0x0001 8798 #define regBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX 0 8799 #define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0x0006 8800 #define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX 0 8801 8802 8803 // addressBlock: nbif_rcc_dev0_epf0_vf1_BIFPFVFDEC1 8804 // base address: 0x0 8805 #define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0x0085 8806 #define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX 2 8807 #define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0x00c0 8808 #define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX 2 8809 #define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0x00c3 8810 #define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX 2 8811 #define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0x00c4 8812 #define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX 2 8813 #define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0x00c5 8814 #define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 8815 8816 8817 // addressBlock: nbif_rcc_dev0_epf0_vf1_BIFDEC2 8818 // base address: 0x0 8819 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0x0400 8820 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 8821 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0x0401 8822 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 8823 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0x0402 8824 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 8825 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0x0403 8826 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 8827 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0x0404 8828 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 8829 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0x0405 8830 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 8831 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0x0406 8832 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 8833 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0x0407 8834 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 8835 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0x0408 8836 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 8837 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0x0409 8838 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 8839 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0x040a 8840 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 8841 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0x040b 8842 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 8843 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO 0x040c 8844 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 8845 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI 0x040d 8846 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 8847 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA 0x040e 8848 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 8849 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL 0x040f 8850 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 8851 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0x0800 8852 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX 3 8853 8854 8855 // addressBlock: nbif_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 8856 // base address: 0x0 8857 #define regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0x00eb 8858 #define regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX 2 8859 #define regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0x00ec 8860 #define regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 8861 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 8862 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 8863 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 8864 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 8865 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 8866 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 8867 #define regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 8868 #define regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 8869 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 8870 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 8871 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 8872 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 8873 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 8874 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 8875 #define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0x0106 8876 #define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX 2 8877 #define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0x0107 8878 #define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX 2 8879 #define regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0x0108 8880 #define regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX 2 8881 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0x0136 8882 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 8883 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0x0137 8884 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 8885 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0x0138 8886 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 8887 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0x0139 8888 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 8889 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0x013a 8890 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 8891 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0x013b 8892 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 8893 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0x013c 8894 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 8895 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0x013d 8896 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 8897 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0x013e 8898 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX 2 8899 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0x013f 8900 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX 2 8901 #define regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0x0140 8902 #define regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX 2 8903 8904 8905 // addressBlock: nbif_bif_bx_dev0_epf0_vf2_SYSPFVFDEC 8906 // base address: 0x0 8907 #define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0x0000 8908 #define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX 0 8909 #define regBIF_BX_DEV0_EPF0_VF2_MM_DATA 0x0001 8910 #define regBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX 0 8911 #define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0x0006 8912 #define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX 0 8913 8914 8915 // addressBlock: nbif_rcc_dev0_epf0_vf2_BIFPFVFDEC1 8916 // base address: 0x0 8917 #define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0x0085 8918 #define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX 2 8919 #define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0x00c0 8920 #define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX 2 8921 #define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0x00c3 8922 #define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX 2 8923 #define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0x00c4 8924 #define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX 2 8925 #define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0x00c5 8926 #define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 8927 8928 8929 // addressBlock: nbif_rcc_dev0_epf0_vf2_BIFDEC2 8930 // base address: 0x0 8931 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0x0400 8932 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 8933 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0x0401 8934 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 8935 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0x0402 8936 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 8937 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0x0403 8938 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 8939 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0x0404 8940 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 8941 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0x0405 8942 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 8943 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0x0406 8944 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 8945 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0x0407 8946 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 8947 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0x0408 8948 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 8949 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0x0409 8950 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 8951 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0x040a 8952 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 8953 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0x040b 8954 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 8955 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO 0x040c 8956 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 8957 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI 0x040d 8958 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 8959 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA 0x040e 8960 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 8961 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL 0x040f 8962 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 8963 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0x0800 8964 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX 3 8965 8966 8967 // addressBlock: nbif_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 8968 // base address: 0x0 8969 #define regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0x00eb 8970 #define regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX 2 8971 #define regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0x00ec 8972 #define regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 8973 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 8974 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 8975 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 8976 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 8977 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 8978 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 8979 #define regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 8980 #define regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 8981 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 8982 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 8983 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 8984 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 8985 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 8986 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 8987 #define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0x0106 8988 #define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX 2 8989 #define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0x0107 8990 #define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX 2 8991 #define regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0x0108 8992 #define regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX 2 8993 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0x0136 8994 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 8995 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0x0137 8996 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 8997 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0x0138 8998 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 8999 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0x0139 9000 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 9001 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0x013a 9002 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 9003 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0x013b 9004 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 9005 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0x013c 9006 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 9007 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0x013d 9008 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 9009 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0x013e 9010 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX 2 9011 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0x013f 9012 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX 2 9013 #define regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0x0140 9014 #define regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX 2 9015 9016 9017 // addressBlock: nbif_bif_bx_dev0_epf0_vf3_SYSPFVFDEC 9018 // base address: 0x0 9019 #define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0x0000 9020 #define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX 0 9021 #define regBIF_BX_DEV0_EPF0_VF3_MM_DATA 0x0001 9022 #define regBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX 0 9023 #define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0x0006 9024 #define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX 0 9025 9026 9027 // addressBlock: nbif_rcc_dev0_epf0_vf3_BIFPFVFDEC1 9028 // base address: 0x0 9029 #define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0x0085 9030 #define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX 2 9031 #define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0x00c0 9032 #define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX 2 9033 #define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0x00c3 9034 #define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX 2 9035 #define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0x00c4 9036 #define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX 2 9037 #define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0x00c5 9038 #define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 9039 9040 9041 // addressBlock: nbif_rcc_dev0_epf0_vf3_BIFDEC2 9042 // base address: 0x0 9043 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0x0400 9044 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 9045 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0x0401 9046 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 9047 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0x0402 9048 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 9049 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0x0403 9050 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 9051 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0x0404 9052 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 9053 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0x0405 9054 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 9055 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0x0406 9056 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 9057 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0x0407 9058 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 9059 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0x0408 9060 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 9061 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0x0409 9062 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 9063 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0x040a 9064 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 9065 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0x040b 9066 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 9067 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO 0x040c 9068 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 9069 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI 0x040d 9070 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 9071 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA 0x040e 9072 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 9073 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL 0x040f 9074 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 9075 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0x0800 9076 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX 3 9077 9078 9079 // addressBlock: nbif_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 9080 // base address: 0x0 9081 #define regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0x00eb 9082 #define regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX 2 9083 #define regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0x00ec 9084 #define regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 9085 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 9086 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 9087 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 9088 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 9089 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 9090 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 9091 #define regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 9092 #define regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9093 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 9094 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9095 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 9096 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 9097 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 9098 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 9099 #define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0x0106 9100 #define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX 2 9101 #define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0x0107 9102 #define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX 2 9103 #define regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0x0108 9104 #define regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX 2 9105 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0x0136 9106 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 9107 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0x0137 9108 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 9109 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0x0138 9110 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 9111 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0x0139 9112 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 9113 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0x013a 9114 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 9115 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0x013b 9116 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 9117 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0x013c 9118 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 9119 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0x013d 9120 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 9121 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0x013e 9122 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX 2 9123 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0x013f 9124 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX 2 9125 #define regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0x0140 9126 #define regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX 2 9127 9128 9129 // addressBlock: nbif_bif_bx_dev0_epf0_vf4_SYSPFVFDEC 9130 // base address: 0x0 9131 #define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0x0000 9132 #define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX 0 9133 #define regBIF_BX_DEV0_EPF0_VF4_MM_DATA 0x0001 9134 #define regBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX 0 9135 #define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0x0006 9136 #define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX 0 9137 9138 9139 // addressBlock: nbif_rcc_dev0_epf0_vf4_BIFPFVFDEC1 9140 // base address: 0x0 9141 #define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0x0085 9142 #define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX 2 9143 #define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0x00c0 9144 #define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX 2 9145 #define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0x00c3 9146 #define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX 2 9147 #define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0x00c4 9148 #define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX 2 9149 #define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0x00c5 9150 #define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 9151 9152 9153 // addressBlock: nbif_rcc_dev0_epf0_vf4_BIFDEC2 9154 // base address: 0x0 9155 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0x0400 9156 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 9157 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0x0401 9158 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 9159 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0x0402 9160 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 9161 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0x0403 9162 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 9163 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0x0404 9164 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 9165 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0x0405 9166 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 9167 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0x0406 9168 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 9169 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0x0407 9170 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 9171 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0x0408 9172 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 9173 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0x0409 9174 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 9175 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0x040a 9176 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 9177 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0x040b 9178 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 9179 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO 0x040c 9180 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 9181 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI 0x040d 9182 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 9183 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA 0x040e 9184 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 9185 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL 0x040f 9186 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 9187 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0x0800 9188 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX 3 9189 9190 9191 // addressBlock: nbif_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 9192 // base address: 0x0 9193 #define regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0x00eb 9194 #define regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX 2 9195 #define regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0x00ec 9196 #define regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 9197 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 9198 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 9199 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 9200 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 9201 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 9202 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 9203 #define regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 9204 #define regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9205 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 9206 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9207 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 9208 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 9209 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 9210 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 9211 #define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0x0106 9212 #define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX 2 9213 #define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0x0107 9214 #define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX 2 9215 #define regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0x0108 9216 #define regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX 2 9217 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0x0136 9218 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 9219 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0x0137 9220 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 9221 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0x0138 9222 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 9223 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0x0139 9224 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 9225 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0x013a 9226 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 9227 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0x013b 9228 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 9229 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0x013c 9230 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 9231 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0x013d 9232 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 9233 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0x013e 9234 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX 2 9235 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0x013f 9236 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX 2 9237 #define regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0x0140 9238 #define regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX 2 9239 9240 9241 // addressBlock: nbif_bif_bx_dev0_epf0_vf5_SYSPFVFDEC 9242 // base address: 0x0 9243 #define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0x0000 9244 #define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX 0 9245 #define regBIF_BX_DEV0_EPF0_VF5_MM_DATA 0x0001 9246 #define regBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX 0 9247 #define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0x0006 9248 #define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX 0 9249 9250 9251 // addressBlock: nbif_rcc_dev0_epf0_vf5_BIFPFVFDEC1 9252 // base address: 0x0 9253 #define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0x0085 9254 #define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX 2 9255 #define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0x00c0 9256 #define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX 2 9257 #define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0x00c3 9258 #define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX 2 9259 #define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0x00c4 9260 #define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX 2 9261 #define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0x00c5 9262 #define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 9263 9264 9265 // addressBlock: nbif_rcc_dev0_epf0_vf5_BIFDEC2 9266 // base address: 0x0 9267 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0x0400 9268 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 9269 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0x0401 9270 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 9271 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0x0402 9272 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 9273 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0x0403 9274 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 9275 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0x0404 9276 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 9277 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0x0405 9278 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 9279 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0x0406 9280 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 9281 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0x0407 9282 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 9283 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0x0408 9284 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 9285 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0x0409 9286 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 9287 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0x040a 9288 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 9289 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0x040b 9290 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 9291 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO 0x040c 9292 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 9293 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI 0x040d 9294 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 9295 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA 0x040e 9296 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 9297 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL 0x040f 9298 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 9299 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0x0800 9300 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX 3 9301 9302 9303 // addressBlock: nbif_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 9304 // base address: 0x0 9305 #define regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0x00eb 9306 #define regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX 2 9307 #define regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0x00ec 9308 #define regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 9309 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 9310 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 9311 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 9312 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 9313 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 9314 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 9315 #define regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 9316 #define regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9317 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 9318 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9319 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 9320 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 9321 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 9322 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 9323 #define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0x0106 9324 #define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX 2 9325 #define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0x0107 9326 #define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX 2 9327 #define regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0x0108 9328 #define regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX 2 9329 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0x0136 9330 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 9331 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0x0137 9332 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 9333 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0x0138 9334 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 9335 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0x0139 9336 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 9337 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0x013a 9338 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 9339 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0x013b 9340 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 9341 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0x013c 9342 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 9343 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0x013d 9344 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 9345 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0x013e 9346 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX 2 9347 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0x013f 9348 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX 2 9349 #define regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0x0140 9350 #define regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX 2 9351 9352 9353 // addressBlock: nbif_bif_bx_dev0_epf0_vf6_SYSPFVFDEC 9354 // base address: 0x0 9355 #define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0x0000 9356 #define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX 0 9357 #define regBIF_BX_DEV0_EPF0_VF6_MM_DATA 0x0001 9358 #define regBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX 0 9359 #define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0x0006 9360 #define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX 0 9361 9362 9363 // addressBlock: nbif_rcc_dev0_epf0_vf6_BIFPFVFDEC1 9364 // base address: 0x0 9365 #define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0x0085 9366 #define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX 2 9367 #define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0x00c0 9368 #define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX 2 9369 #define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0x00c3 9370 #define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX 2 9371 #define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0x00c4 9372 #define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX 2 9373 #define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0x00c5 9374 #define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 9375 9376 9377 // addressBlock: nbif_rcc_dev0_epf0_vf6_BIFDEC2 9378 // base address: 0x0 9379 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0x0400 9380 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 9381 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0x0401 9382 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 9383 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0x0402 9384 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 9385 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0x0403 9386 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 9387 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0x0404 9388 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 9389 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0x0405 9390 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 9391 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0x0406 9392 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 9393 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0x0407 9394 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 9395 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0x0408 9396 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 9397 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0x0409 9398 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 9399 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0x040a 9400 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 9401 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0x040b 9402 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 9403 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO 0x040c 9404 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 9405 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI 0x040d 9406 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 9407 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA 0x040e 9408 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 9409 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL 0x040f 9410 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 9411 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0x0800 9412 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX 3 9413 9414 9415 // addressBlock: nbif_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 9416 // base address: 0x0 9417 #define regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0x00eb 9418 #define regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX 2 9419 #define regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0x00ec 9420 #define regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 9421 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 9422 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 9423 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 9424 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 9425 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 9426 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 9427 #define regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 9428 #define regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9429 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 9430 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9431 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 9432 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 9433 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 9434 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 9435 #define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0x0106 9436 #define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX 2 9437 #define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0x0107 9438 #define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX 2 9439 #define regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0x0108 9440 #define regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX 2 9441 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0x0136 9442 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 9443 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0x0137 9444 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 9445 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0x0138 9446 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 9447 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0x0139 9448 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 9449 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0x013a 9450 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 9451 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0x013b 9452 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 9453 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0x013c 9454 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 9455 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0x013d 9456 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 9457 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0x013e 9458 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX 2 9459 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0x013f 9460 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX 2 9461 #define regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0x0140 9462 #define regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX 2 9463 9464 9465 // addressBlock: nbif_bif_bx_dev0_epf0_vf7_SYSPFVFDEC 9466 // base address: 0x0 9467 #define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0x0000 9468 #define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX 0 9469 #define regBIF_BX_DEV0_EPF0_VF7_MM_DATA 0x0001 9470 #define regBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX 0 9471 #define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0x0006 9472 #define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX 0 9473 9474 9475 // addressBlock: nbif_rcc_dev0_epf0_vf7_BIFPFVFDEC1 9476 // base address: 0x0 9477 #define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0x0085 9478 #define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX 2 9479 #define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0x00c0 9480 #define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX 2 9481 #define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0x00c3 9482 #define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX 2 9483 #define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0x00c4 9484 #define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX 2 9485 #define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0x00c5 9486 #define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 9487 9488 9489 // addressBlock: nbif_rcc_dev0_epf0_vf7_BIFDEC2 9490 // base address: 0x0 9491 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0x0400 9492 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 9493 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0x0401 9494 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 9495 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0x0402 9496 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 9497 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0x0403 9498 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 9499 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0x0404 9500 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 9501 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0x0405 9502 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 9503 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0x0406 9504 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 9505 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0x0407 9506 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 9507 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0x0408 9508 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 9509 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0x0409 9510 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 9511 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0x040a 9512 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 9513 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0x040b 9514 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 9515 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO 0x040c 9516 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 9517 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI 0x040d 9518 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 9519 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA 0x040e 9520 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 9521 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL 0x040f 9522 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 9523 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0x0800 9524 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX 3 9525 9526 9527 // addressBlock: nbif_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1 9528 // base address: 0x0 9529 #define regBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0x00eb 9530 #define regBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_BASE_IDX 2 9531 #define regBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0x00ec 9532 #define regBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 9533 #define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 9534 #define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 9535 #define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 9536 #define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 9537 #define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 9538 #define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 9539 #define regBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 9540 #define regBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9541 #define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 9542 #define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9543 #define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 9544 #define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 9545 #define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 9546 #define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 9547 #define regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0x0106 9548 #define regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_BASE_IDX 2 9549 #define regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0x0107 9550 #define regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_BASE_IDX 2 9551 #define regBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0x0108 9552 #define regBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_BASE_IDX 2 9553 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0x0136 9554 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 9555 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0x0137 9556 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 9557 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0x0138 9558 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 9559 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0x0139 9560 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 9561 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0x013a 9562 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 9563 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0x013b 9564 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 9565 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0x013c 9566 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 9567 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0x013d 9568 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 9569 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0x013e 9570 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_BASE_IDX 2 9571 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0x013f 9572 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_BASE_IDX 2 9573 #define regBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0x0140 9574 #define regBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_BASE_IDX 2 9575 9576 9577 // addressBlock: nbif_bif_bx_dev0_epf0_vf8_SYSPFVFDEC 9578 // base address: 0x0 9579 #define regBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0x0000 9580 #define regBIF_BX_DEV0_EPF0_VF8_MM_INDEX_BASE_IDX 0 9581 #define regBIF_BX_DEV0_EPF0_VF8_MM_DATA 0x0001 9582 #define regBIF_BX_DEV0_EPF0_VF8_MM_DATA_BASE_IDX 0 9583 #define regBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0x0006 9584 #define regBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_BASE_IDX 0 9585 9586 9587 // addressBlock: nbif_rcc_dev0_epf0_vf8_BIFPFVFDEC1 9588 // base address: 0x0 9589 #define regRCC_DEV0_EPF0_VF8_RCC_ERR_LOG 0x0085 9590 #define regRCC_DEV0_EPF0_VF8_RCC_ERR_LOG_BASE_IDX 2 9591 #define regRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN 0x00c0 9592 #define regRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN_BASE_IDX 2 9593 #define regRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE 0x00c3 9594 #define regRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE_BASE_IDX 2 9595 #define regRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED 0x00c4 9596 #define regRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED_BASE_IDX 2 9597 #define regRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER 0x00c5 9598 #define regRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 9599 9600 9601 // addressBlock: nbif_rcc_dev0_epf0_vf8_BIFDEC2 9602 // base address: 0x0 9603 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO 0x0400 9604 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 9605 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI 0x0401 9606 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 9607 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA 0x0402 9608 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 9609 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL 0x0403 9610 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 9611 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO 0x0404 9612 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 9613 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI 0x0405 9614 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 9615 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA 0x0406 9616 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 9617 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL 0x0407 9618 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 9619 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO 0x0408 9620 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 9621 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI 0x0409 9622 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 9623 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA 0x040a 9624 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 9625 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL 0x040b 9626 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 9627 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO 0x040c 9628 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 9629 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI 0x040d 9630 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 9631 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA 0x040e 9632 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 9633 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL 0x040f 9634 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 9635 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_PBA 0x0800 9636 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_PBA_BASE_IDX 3 9637 9638 9639 // addressBlock: nbif_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1 9640 // base address: 0x0 9641 #define regBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0x00eb 9642 #define regBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_BASE_IDX 2 9643 #define regBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0x00ec 9644 #define regBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 9645 #define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 9646 #define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 9647 #define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 9648 #define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 9649 #define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 9650 #define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 9651 #define regBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 9652 #define regBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9653 #define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 9654 #define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9655 #define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 9656 #define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 9657 #define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 9658 #define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 9659 #define regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0x0106 9660 #define regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_BASE_IDX 2 9661 #define regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0x0107 9662 #define regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_BASE_IDX 2 9663 #define regBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0x0108 9664 #define regBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_BASE_IDX 2 9665 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0x0136 9666 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 9667 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0x0137 9668 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 9669 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0x0138 9670 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 9671 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0x0139 9672 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 9673 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0x013a 9674 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 9675 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0x013b 9676 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 9677 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0x013c 9678 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 9679 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0x013d 9680 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 9681 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0x013e 9682 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_BASE_IDX 2 9683 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0x013f 9684 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_BASE_IDX 2 9685 #define regBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0x0140 9686 #define regBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_BASE_IDX 2 9687 9688 9689 // addressBlock: nbif_bif_bx_dev0_epf0_vf9_SYSPFVFDEC 9690 // base address: 0x0 9691 #define regBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0x0000 9692 #define regBIF_BX_DEV0_EPF0_VF9_MM_INDEX_BASE_IDX 0 9693 #define regBIF_BX_DEV0_EPF0_VF9_MM_DATA 0x0001 9694 #define regBIF_BX_DEV0_EPF0_VF9_MM_DATA_BASE_IDX 0 9695 #define regBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0x0006 9696 #define regBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_BASE_IDX 0 9697 9698 9699 // addressBlock: nbif_rcc_dev0_epf0_vf9_BIFPFVFDEC1 9700 // base address: 0x0 9701 #define regRCC_DEV0_EPF0_VF9_RCC_ERR_LOG 0x0085 9702 #define regRCC_DEV0_EPF0_VF9_RCC_ERR_LOG_BASE_IDX 2 9703 #define regRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN 0x00c0 9704 #define regRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN_BASE_IDX 2 9705 #define regRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE 0x00c3 9706 #define regRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE_BASE_IDX 2 9707 #define regRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED 0x00c4 9708 #define regRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED_BASE_IDX 2 9709 #define regRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER 0x00c5 9710 #define regRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 9711 9712 9713 // addressBlock: nbif_rcc_dev0_epf0_vf9_BIFDEC2 9714 // base address: 0x0 9715 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO 0x0400 9716 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 9717 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI 0x0401 9718 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 9719 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA 0x0402 9720 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 9721 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL 0x0403 9722 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 9723 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO 0x0404 9724 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 9725 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI 0x0405 9726 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 9727 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA 0x0406 9728 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 9729 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL 0x0407 9730 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 9731 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO 0x0408 9732 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 9733 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI 0x0409 9734 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 9735 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA 0x040a 9736 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 9737 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL 0x040b 9738 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 9739 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO 0x040c 9740 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 9741 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI 0x040d 9742 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 9743 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA 0x040e 9744 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 9745 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL 0x040f 9746 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 9747 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_PBA 0x0800 9748 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_PBA_BASE_IDX 3 9749 9750 9751 // addressBlock: nbif_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1 9752 // base address: 0x0 9753 #define regBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0x00eb 9754 #define regBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_BASE_IDX 2 9755 #define regBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0x00ec 9756 #define regBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 9757 #define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 9758 #define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 9759 #define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 9760 #define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 9761 #define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 9762 #define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 9763 #define regBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 9764 #define regBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9765 #define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 9766 #define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9767 #define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 9768 #define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 9769 #define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 9770 #define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 9771 #define regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0x0106 9772 #define regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_BASE_IDX 2 9773 #define regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0x0107 9774 #define regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_BASE_IDX 2 9775 #define regBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0x0108 9776 #define regBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_BASE_IDX 2 9777 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0x0136 9778 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 9779 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0x0137 9780 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 9781 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0x0138 9782 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 9783 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0x0139 9784 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 9785 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0x013a 9786 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 9787 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0x013b 9788 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 9789 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0x013c 9790 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 9791 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0x013d 9792 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 9793 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0x013e 9794 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_BASE_IDX 2 9795 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0x013f 9796 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_BASE_IDX 2 9797 #define regBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0x0140 9798 #define regBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_BASE_IDX 2 9799 9800 9801 // addressBlock: nbif_bif_bx_dev0_epf0_vf10_SYSPFVFDEC 9802 // base address: 0x0 9803 #define regBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0x0000 9804 #define regBIF_BX_DEV0_EPF0_VF10_MM_INDEX_BASE_IDX 0 9805 #define regBIF_BX_DEV0_EPF0_VF10_MM_DATA 0x0001 9806 #define regBIF_BX_DEV0_EPF0_VF10_MM_DATA_BASE_IDX 0 9807 #define regBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0x0006 9808 #define regBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_BASE_IDX 0 9809 9810 9811 // addressBlock: nbif_rcc_dev0_epf0_vf10_BIFPFVFDEC1 9812 // base address: 0x0 9813 #define regRCC_DEV0_EPF0_VF10_RCC_ERR_LOG 0x0085 9814 #define regRCC_DEV0_EPF0_VF10_RCC_ERR_LOG_BASE_IDX 2 9815 #define regRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN 0x00c0 9816 #define regRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN_BASE_IDX 2 9817 #define regRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE 0x00c3 9818 #define regRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE_BASE_IDX 2 9819 #define regRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED 0x00c4 9820 #define regRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED_BASE_IDX 2 9821 #define regRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER 0x00c5 9822 #define regRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 9823 9824 9825 // addressBlock: nbif_rcc_dev0_epf0_vf10_BIFDEC2 9826 // base address: 0x0 9827 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO 0x0400 9828 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 9829 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI 0x0401 9830 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 9831 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA 0x0402 9832 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 9833 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL 0x0403 9834 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 9835 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO 0x0404 9836 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 9837 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI 0x0405 9838 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 9839 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA 0x0406 9840 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 9841 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL 0x0407 9842 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 9843 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO 0x0408 9844 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 9845 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI 0x0409 9846 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 9847 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA 0x040a 9848 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 9849 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL 0x040b 9850 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 9851 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO 0x040c 9852 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 9853 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI 0x040d 9854 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 9855 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA 0x040e 9856 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 9857 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL 0x040f 9858 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 9859 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_PBA 0x0800 9860 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_PBA_BASE_IDX 3 9861 9862 9863 // addressBlock: nbif_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1 9864 // base address: 0x0 9865 #define regBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0x00eb 9866 #define regBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_BASE_IDX 2 9867 #define regBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0x00ec 9868 #define regBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 9869 #define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 9870 #define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 9871 #define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 9872 #define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 9873 #define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 9874 #define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 9875 #define regBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 9876 #define regBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9877 #define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 9878 #define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9879 #define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 9880 #define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 9881 #define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 9882 #define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 9883 #define regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0x0106 9884 #define regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_BASE_IDX 2 9885 #define regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0x0107 9886 #define regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_BASE_IDX 2 9887 #define regBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0x0108 9888 #define regBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_BASE_IDX 2 9889 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0x0136 9890 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 9891 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0x0137 9892 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 9893 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0x0138 9894 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 9895 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0x0139 9896 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 9897 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0x013a 9898 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 9899 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0x013b 9900 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 9901 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0x013c 9902 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 9903 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0x013d 9904 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 9905 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0x013e 9906 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_BASE_IDX 2 9907 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0x013f 9908 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_BASE_IDX 2 9909 #define regBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0x0140 9910 #define regBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_BASE_IDX 2 9911 9912 9913 // addressBlock: nbif_bif_bx_dev0_epf0_vf11_SYSPFVFDEC 9914 // base address: 0x0 9915 #define regBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0x0000 9916 #define regBIF_BX_DEV0_EPF0_VF11_MM_INDEX_BASE_IDX 0 9917 #define regBIF_BX_DEV0_EPF0_VF11_MM_DATA 0x0001 9918 #define regBIF_BX_DEV0_EPF0_VF11_MM_DATA_BASE_IDX 0 9919 #define regBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0x0006 9920 #define regBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_BASE_IDX 0 9921 9922 9923 // addressBlock: nbif_rcc_dev0_epf0_vf11_BIFPFVFDEC1 9924 // base address: 0x0 9925 #define regRCC_DEV0_EPF0_VF11_RCC_ERR_LOG 0x0085 9926 #define regRCC_DEV0_EPF0_VF11_RCC_ERR_LOG_BASE_IDX 2 9927 #define regRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN 0x00c0 9928 #define regRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN_BASE_IDX 2 9929 #define regRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE 0x00c3 9930 #define regRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE_BASE_IDX 2 9931 #define regRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED 0x00c4 9932 #define regRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED_BASE_IDX 2 9933 #define regRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER 0x00c5 9934 #define regRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 9935 9936 9937 // addressBlock: nbif_rcc_dev0_epf0_vf11_BIFDEC2 9938 // base address: 0x0 9939 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO 0x0400 9940 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 9941 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI 0x0401 9942 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 9943 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA 0x0402 9944 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 9945 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL 0x0403 9946 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 9947 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO 0x0404 9948 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 9949 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI 0x0405 9950 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 9951 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA 0x0406 9952 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 9953 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL 0x0407 9954 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 9955 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO 0x0408 9956 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 9957 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI 0x0409 9958 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 9959 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA 0x040a 9960 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 9961 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL 0x040b 9962 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 9963 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO 0x040c 9964 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 9965 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI 0x040d 9966 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 9967 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA 0x040e 9968 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 9969 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL 0x040f 9970 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 9971 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_PBA 0x0800 9972 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_PBA_BASE_IDX 3 9973 9974 9975 // addressBlock: nbif_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1 9976 // base address: 0x0 9977 #define regBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0x00eb 9978 #define regBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_BASE_IDX 2 9979 #define regBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0x00ec 9980 #define regBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 9981 #define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 9982 #define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 9983 #define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 9984 #define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 9985 #define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 9986 #define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 9987 #define regBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 9988 #define regBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9989 #define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 9990 #define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9991 #define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 9992 #define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 9993 #define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 9994 #define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 9995 #define regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0x0106 9996 #define regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_BASE_IDX 2 9997 #define regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0x0107 9998 #define regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_BASE_IDX 2 9999 #define regBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0x0108 10000 #define regBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_BASE_IDX 2 10001 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0x0136 10002 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 10003 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0x0137 10004 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 10005 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0x0138 10006 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 10007 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0x0139 10008 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 10009 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0x013a 10010 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 10011 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0x013b 10012 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 10013 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0x013c 10014 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 10015 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0x013d 10016 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 10017 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0x013e 10018 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_BASE_IDX 2 10019 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0x013f 10020 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_BASE_IDX 2 10021 #define regBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0x0140 10022 #define regBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_BASE_IDX 2 10023 10024 10025 // addressBlock: nbif_bif_bx_dev0_epf0_vf12_SYSPFVFDEC 10026 // base address: 0x0 10027 #define regBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0x0000 10028 #define regBIF_BX_DEV0_EPF0_VF12_MM_INDEX_BASE_IDX 0 10029 #define regBIF_BX_DEV0_EPF0_VF12_MM_DATA 0x0001 10030 #define regBIF_BX_DEV0_EPF0_VF12_MM_DATA_BASE_IDX 0 10031 #define regBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0x0006 10032 #define regBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_BASE_IDX 0 10033 10034 10035 // addressBlock: nbif_rcc_dev0_epf0_vf12_BIFPFVFDEC1 10036 // base address: 0x0 10037 #define regRCC_DEV0_EPF0_VF12_RCC_ERR_LOG 0x0085 10038 #define regRCC_DEV0_EPF0_VF12_RCC_ERR_LOG_BASE_IDX 2 10039 #define regRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN 0x00c0 10040 #define regRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN_BASE_IDX 2 10041 #define regRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE 0x00c3 10042 #define regRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE_BASE_IDX 2 10043 #define regRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED 0x00c4 10044 #define regRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED_BASE_IDX 2 10045 #define regRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER 0x00c5 10046 #define regRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 10047 10048 10049 // addressBlock: nbif_rcc_dev0_epf0_vf12_BIFDEC2 10050 // base address: 0x0 10051 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO 0x0400 10052 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 10053 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI 0x0401 10054 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 10055 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA 0x0402 10056 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 10057 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL 0x0403 10058 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 10059 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO 0x0404 10060 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 10061 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI 0x0405 10062 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 10063 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA 0x0406 10064 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 10065 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL 0x0407 10066 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 10067 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO 0x0408 10068 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 10069 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI 0x0409 10070 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 10071 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA 0x040a 10072 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 10073 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL 0x040b 10074 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 10075 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO 0x040c 10076 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 10077 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI 0x040d 10078 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 10079 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA 0x040e 10080 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 10081 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL 0x040f 10082 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 10083 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_PBA 0x0800 10084 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_PBA_BASE_IDX 3 10085 10086 10087 // addressBlock: nbif_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1 10088 // base address: 0x0 10089 #define regBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0x00eb 10090 #define regBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_BASE_IDX 2 10091 #define regBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0x00ec 10092 #define regBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 10093 #define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 10094 #define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 10095 #define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 10096 #define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 10097 #define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 10098 #define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 10099 #define regBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 10100 #define regBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 10101 #define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 10102 #define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 10103 #define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 10104 #define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 10105 #define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 10106 #define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 10107 #define regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0x0106 10108 #define regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_BASE_IDX 2 10109 #define regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0x0107 10110 #define regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_BASE_IDX 2 10111 #define regBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0x0108 10112 #define regBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_BASE_IDX 2 10113 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0x0136 10114 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 10115 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0x0137 10116 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 10117 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0x0138 10118 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 10119 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0x0139 10120 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 10121 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0x013a 10122 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 10123 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0x013b 10124 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 10125 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0x013c 10126 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 10127 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0x013d 10128 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 10129 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0x013e 10130 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_BASE_IDX 2 10131 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0x013f 10132 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_BASE_IDX 2 10133 #define regBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0x0140 10134 #define regBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_BASE_IDX 2 10135 10136 10137 // addressBlock: nbif_bif_bx_dev0_epf0_vf13_SYSPFVFDEC 10138 // base address: 0x0 10139 #define regBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0x0000 10140 #define regBIF_BX_DEV0_EPF0_VF13_MM_INDEX_BASE_IDX 0 10141 #define regBIF_BX_DEV0_EPF0_VF13_MM_DATA 0x0001 10142 #define regBIF_BX_DEV0_EPF0_VF13_MM_DATA_BASE_IDX 0 10143 #define regBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0x0006 10144 #define regBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_BASE_IDX 0 10145 10146 10147 // addressBlock: nbif_rcc_dev0_epf0_vf13_BIFPFVFDEC1 10148 // base address: 0x0 10149 #define regRCC_DEV0_EPF0_VF13_RCC_ERR_LOG 0x0085 10150 #define regRCC_DEV0_EPF0_VF13_RCC_ERR_LOG_BASE_IDX 2 10151 #define regRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN 0x00c0 10152 #define regRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN_BASE_IDX 2 10153 #define regRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE 0x00c3 10154 #define regRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE_BASE_IDX 2 10155 #define regRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED 0x00c4 10156 #define regRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED_BASE_IDX 2 10157 #define regRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER 0x00c5 10158 #define regRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 10159 10160 10161 // addressBlock: nbif_rcc_dev0_epf0_vf13_BIFDEC2 10162 // base address: 0x0 10163 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO 0x0400 10164 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 10165 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI 0x0401 10166 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 10167 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA 0x0402 10168 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 10169 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL 0x0403 10170 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 10171 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO 0x0404 10172 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 10173 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI 0x0405 10174 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 10175 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA 0x0406 10176 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 10177 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL 0x0407 10178 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 10179 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO 0x0408 10180 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 10181 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI 0x0409 10182 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 10183 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA 0x040a 10184 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 10185 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL 0x040b 10186 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 10187 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO 0x040c 10188 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 10189 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI 0x040d 10190 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 10191 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA 0x040e 10192 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 10193 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL 0x040f 10194 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 10195 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_PBA 0x0800 10196 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_PBA_BASE_IDX 3 10197 10198 10199 // addressBlock: nbif_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1 10200 // base address: 0x0 10201 #define regBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0x00eb 10202 #define regBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_BASE_IDX 2 10203 #define regBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0x00ec 10204 #define regBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 10205 #define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 10206 #define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 10207 #define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 10208 #define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 10209 #define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 10210 #define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 10211 #define regBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 10212 #define regBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 10213 #define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 10214 #define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 10215 #define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 10216 #define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 10217 #define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 10218 #define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 10219 #define regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0x0106 10220 #define regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_BASE_IDX 2 10221 #define regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0x0107 10222 #define regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_BASE_IDX 2 10223 #define regBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0x0108 10224 #define regBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_BASE_IDX 2 10225 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0x0136 10226 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 10227 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0x0137 10228 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 10229 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0x0138 10230 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 10231 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0x0139 10232 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 10233 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0x013a 10234 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 10235 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0x013b 10236 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 10237 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0x013c 10238 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 10239 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0x013d 10240 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 10241 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0x013e 10242 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_BASE_IDX 2 10243 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0x013f 10244 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_BASE_IDX 2 10245 #define regBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0x0140 10246 #define regBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_BASE_IDX 2 10247 10248 10249 // addressBlock: nbif_bif_bx_dev0_epf0_vf14_SYSPFVFDEC 10250 // base address: 0x0 10251 #define regBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0x0000 10252 #define regBIF_BX_DEV0_EPF0_VF14_MM_INDEX_BASE_IDX 0 10253 #define regBIF_BX_DEV0_EPF0_VF14_MM_DATA 0x0001 10254 #define regBIF_BX_DEV0_EPF0_VF14_MM_DATA_BASE_IDX 0 10255 #define regBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0x0006 10256 #define regBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_BASE_IDX 0 10257 10258 10259 // addressBlock: nbif_rcc_dev0_epf0_vf14_BIFPFVFDEC1 10260 // base address: 0x0 10261 #define regRCC_DEV0_EPF0_VF14_RCC_ERR_LOG 0x0085 10262 #define regRCC_DEV0_EPF0_VF14_RCC_ERR_LOG_BASE_IDX 2 10263 #define regRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN 0x00c0 10264 #define regRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN_BASE_IDX 2 10265 #define regRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE 0x00c3 10266 #define regRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE_BASE_IDX 2 10267 #define regRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED 0x00c4 10268 #define regRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED_BASE_IDX 2 10269 #define regRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER 0x00c5 10270 #define regRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 10271 10272 10273 // addressBlock: nbif_rcc_dev0_epf0_vf14_BIFDEC2 10274 // base address: 0x0 10275 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO 0x0400 10276 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 10277 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI 0x0401 10278 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 10279 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA 0x0402 10280 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 10281 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL 0x0403 10282 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 10283 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO 0x0404 10284 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 10285 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI 0x0405 10286 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 10287 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA 0x0406 10288 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 10289 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL 0x0407 10290 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 10291 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO 0x0408 10292 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 10293 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI 0x0409 10294 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 10295 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA 0x040a 10296 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 10297 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL 0x040b 10298 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 10299 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO 0x040c 10300 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 10301 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI 0x040d 10302 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 10303 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA 0x040e 10304 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 10305 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL 0x040f 10306 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 10307 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_PBA 0x0800 10308 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_PBA_BASE_IDX 3 10309 10310 10311 // addressBlock: nbif_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1 10312 // base address: 0x0 10313 #define regBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0x00eb 10314 #define regBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_BASE_IDX 2 10315 #define regBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0x00ec 10316 #define regBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 10317 #define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 10318 #define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 10319 #define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 10320 #define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 10321 #define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 10322 #define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 10323 #define regBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 10324 #define regBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 10325 #define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 10326 #define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 10327 #define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 10328 #define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 10329 #define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 10330 #define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 10331 #define regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0x0106 10332 #define regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_BASE_IDX 2 10333 #define regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0x0107 10334 #define regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_BASE_IDX 2 10335 #define regBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0x0108 10336 #define regBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_BASE_IDX 2 10337 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0x0136 10338 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 10339 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0x0137 10340 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 10341 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0x0138 10342 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 10343 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0x0139 10344 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 10345 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0x013a 10346 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 10347 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0x013b 10348 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 10349 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0x013c 10350 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 10351 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0x013d 10352 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 10353 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0x013e 10354 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_BASE_IDX 2 10355 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0x013f 10356 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_BASE_IDX 2 10357 #define regBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0x0140 10358 #define regBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_BASE_IDX 2 10359 10360 10361 // addressBlock: nbif_bif_bx_dev0_epf0_vf15_SYSPFVFDEC 10362 // base address: 0x0 10363 #define regBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0x0000 10364 #define regBIF_BX_DEV0_EPF0_VF15_MM_INDEX_BASE_IDX 0 10365 #define regBIF_BX_DEV0_EPF0_VF15_MM_DATA 0x0001 10366 #define regBIF_BX_DEV0_EPF0_VF15_MM_DATA_BASE_IDX 0 10367 #define regBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0x0006 10368 #define regBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_BASE_IDX 0 10369 10370 10371 // addressBlock: nbif_rcc_dev0_epf0_vf15_BIFPFVFDEC1 10372 // base address: 0x0 10373 #define regRCC_DEV0_EPF0_VF15_RCC_ERR_LOG 0x0085 10374 #define regRCC_DEV0_EPF0_VF15_RCC_ERR_LOG_BASE_IDX 2 10375 #define regRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN 0x00c0 10376 #define regRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN_BASE_IDX 2 10377 #define regRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE 0x00c3 10378 #define regRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE_BASE_IDX 2 10379 #define regRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED 0x00c4 10380 #define regRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED_BASE_IDX 2 10381 #define regRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER 0x00c5 10382 #define regRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 10383 10384 10385 // addressBlock: nbif_rcc_dev0_epf0_vf15_BIFDEC2 10386 // base address: 0x0 10387 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO 0x0400 10388 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 10389 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI 0x0401 10390 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 10391 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA 0x0402 10392 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 10393 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL 0x0403 10394 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 10395 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO 0x0404 10396 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 10397 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI 0x0405 10398 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 10399 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA 0x0406 10400 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 10401 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL 0x0407 10402 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 10403 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO 0x0408 10404 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 10405 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI 0x0409 10406 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 10407 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA 0x040a 10408 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 10409 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL 0x040b 10410 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 10411 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO 0x040c 10412 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 10413 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI 0x040d 10414 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 10415 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA 0x040e 10416 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 10417 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL 0x040f 10418 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 10419 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_PBA 0x0800 10420 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_PBA_BASE_IDX 3 10421 10422 10423 // addressBlock: nbif_bif_bx_dev0_epf0_vf16_BIFPFVFDEC1 10424 // base address: 0x0 10425 #define regBIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS 0x00eb 10426 #define regBIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS_BASE_IDX 2 10427 #define regBIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG 0x00ec 10428 #define regBIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 10429 #define regBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 10430 #define regBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 10431 #define regBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 10432 #define regBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 10433 #define regBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 10434 #define regBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 10435 #define regBIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 10436 #define regBIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 10437 #define regBIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 10438 #define regBIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 10439 #define regBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ 0x0106 10440 #define regBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ_BASE_IDX 2 10441 #define regBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE 0x0107 10442 #define regBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE_BASE_IDX 2 10443 #define regBIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING 0x0108 10444 #define regBIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING_BASE_IDX 2 10445 #define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0 0x0136 10446 #define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 10447 #define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1 0x0137 10448 #define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 10449 #define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2 0x0138 10450 #define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 10451 #define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3 0x0139 10452 #define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 10453 #define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0 0x013a 10454 #define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 10455 #define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1 0x013b 10456 #define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 10457 #define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2 0x013c 10458 #define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 10459 #define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3 0x013d 10460 #define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 10461 #define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL 0x013e 10462 #define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL_BASE_IDX 2 10463 #define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL 0x013f 10464 #define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL_BASE_IDX 2 10465 #define regBIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX 0x0140 10466 #define regBIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX_BASE_IDX 2 10467 10468 10469 // addressBlock: nbif_bif_bx_dev0_epf0_vf16_SYSPFVFDEC 10470 // base address: 0x0 10471 #define regBIF_BX_DEV0_EPF0_VF16_MM_INDEX 0x0000 10472 #define regBIF_BX_DEV0_EPF0_VF16_MM_INDEX_BASE_IDX 0 10473 #define regBIF_BX_DEV0_EPF0_VF16_MM_DATA 0x0001 10474 #define regBIF_BX_DEV0_EPF0_VF16_MM_DATA_BASE_IDX 0 10475 #define regBIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI 0x0006 10476 #define regBIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI_BASE_IDX 0 10477 10478 10479 // addressBlock: nbif_rcc_dev0_epf0_vf16_BIFPFVFDEC1 10480 // base address: 0x0 10481 #define regRCC_DEV0_EPF0_VF16_RCC_ERR_LOG 0x0085 10482 #define regRCC_DEV0_EPF0_VF16_RCC_ERR_LOG_BASE_IDX 2 10483 #define regRCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN 0x00c0 10484 #define regRCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN_BASE_IDX 2 10485 #define regRCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE 0x00c3 10486 #define regRCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE_BASE_IDX 2 10487 #define regRCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED 0x00c4 10488 #define regRCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED_BASE_IDX 2 10489 #define regRCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER 0x00c5 10490 #define regRCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 10491 10492 10493 // addressBlock: nbif_rcc_dev0_epf0_vf16_BIFDEC2 10494 // base address: 0x0 10495 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO 0x0400 10496 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 10497 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI 0x0401 10498 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 10499 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA 0x0402 10500 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 10501 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL 0x0403 10502 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 10503 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO 0x0404 10504 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 10505 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI 0x0405 10506 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 10507 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA 0x0406 10508 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 10509 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL 0x0407 10510 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 10511 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO 0x0408 10512 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 10513 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI 0x0409 10514 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 10515 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA 0x040a 10516 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 10517 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL 0x040b 10518 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 10519 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO 0x040c 10520 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 10521 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI 0x040d 10522 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 10523 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA 0x040e 10524 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 10525 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL 0x040f 10526 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 10527 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_PBA 0x0800 10528 #define regRCC_DEV0_EPF0_VF16_GFXMSIX_PBA_BASE_IDX 3 10529 10530 10531 // addressBlock: nbif_bif_bx_dev0_epf0_vf17_BIFPFVFDEC1 10532 // base address: 0x0 10533 #define regBIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS 0x00eb 10534 #define regBIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS_BASE_IDX 2 10535 #define regBIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG 0x00ec 10536 #define regBIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 10537 #define regBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 10538 #define regBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 10539 #define regBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 10540 #define regBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 10541 #define regBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 10542 #define regBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 10543 #define regBIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 10544 #define regBIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 10545 #define regBIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 10546 #define regBIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 10547 #define regBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ 0x0106 10548 #define regBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ_BASE_IDX 2 10549 #define regBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE 0x0107 10550 #define regBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE_BASE_IDX 2 10551 #define regBIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING 0x0108 10552 #define regBIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING_BASE_IDX 2 10553 #define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0 0x0136 10554 #define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 10555 #define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1 0x0137 10556 #define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 10557 #define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2 0x0138 10558 #define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 10559 #define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3 0x0139 10560 #define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 10561 #define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0 0x013a 10562 #define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 10563 #define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1 0x013b 10564 #define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 10565 #define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2 0x013c 10566 #define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 10567 #define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3 0x013d 10568 #define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 10569 #define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL 0x013e 10570 #define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL_BASE_IDX 2 10571 #define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL 0x013f 10572 #define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL_BASE_IDX 2 10573 #define regBIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX 0x0140 10574 #define regBIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX_BASE_IDX 2 10575 10576 10577 // addressBlock: nbif_bif_bx_dev0_epf0_vf17_SYSPFVFDEC 10578 // base address: 0x0 10579 #define regBIF_BX_DEV0_EPF0_VF17_MM_INDEX 0x0000 10580 #define regBIF_BX_DEV0_EPF0_VF17_MM_INDEX_BASE_IDX 0 10581 #define regBIF_BX_DEV0_EPF0_VF17_MM_DATA 0x0001 10582 #define regBIF_BX_DEV0_EPF0_VF17_MM_DATA_BASE_IDX 0 10583 #define regBIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI 0x0006 10584 #define regBIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI_BASE_IDX 0 10585 10586 10587 // addressBlock: nbif_rcc_dev0_epf0_vf17_BIFPFVFDEC1 10588 // base address: 0x0 10589 #define regRCC_DEV0_EPF0_VF17_RCC_ERR_LOG 0x0085 10590 #define regRCC_DEV0_EPF0_VF17_RCC_ERR_LOG_BASE_IDX 2 10591 #define regRCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN 0x00c0 10592 #define regRCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN_BASE_IDX 2 10593 #define regRCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE 0x00c3 10594 #define regRCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE_BASE_IDX 2 10595 #define regRCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED 0x00c4 10596 #define regRCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED_BASE_IDX 2 10597 #define regRCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER 0x00c5 10598 #define regRCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 10599 10600 10601 // addressBlock: nbif_rcc_dev0_epf0_vf17_BIFDEC2 10602 // base address: 0x0 10603 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO 0x0400 10604 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 10605 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI 0x0401 10606 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 10607 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA 0x0402 10608 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 10609 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL 0x0403 10610 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 10611 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO 0x0404 10612 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 10613 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI 0x0405 10614 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 10615 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA 0x0406 10616 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 10617 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL 0x0407 10618 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 10619 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO 0x0408 10620 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 10621 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI 0x0409 10622 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 10623 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA 0x040a 10624 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 10625 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL 0x040b 10626 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 10627 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO 0x040c 10628 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 10629 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI 0x040d 10630 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 10631 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA 0x040e 10632 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 10633 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL 0x040f 10634 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 10635 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_PBA 0x0800 10636 #define regRCC_DEV0_EPF0_VF17_GFXMSIX_PBA_BASE_IDX 3 10637 10638 10639 // addressBlock: nbif_bif_bx_dev0_epf0_vf18_BIFPFVFDEC1 10640 // base address: 0x0 10641 #define regBIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS 0x00eb 10642 #define regBIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS_BASE_IDX 2 10643 #define regBIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG 0x00ec 10644 #define regBIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 10645 #define regBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 10646 #define regBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 10647 #define regBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 10648 #define regBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 10649 #define regBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 10650 #define regBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 10651 #define regBIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 10652 #define regBIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 10653 #define regBIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 10654 #define regBIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 10655 #define regBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ 0x0106 10656 #define regBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ_BASE_IDX 2 10657 #define regBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE 0x0107 10658 #define regBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE_BASE_IDX 2 10659 #define regBIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING 0x0108 10660 #define regBIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING_BASE_IDX 2 10661 #define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0 0x0136 10662 #define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 10663 #define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1 0x0137 10664 #define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 10665 #define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2 0x0138 10666 #define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 10667 #define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3 0x0139 10668 #define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 10669 #define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0 0x013a 10670 #define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 10671 #define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1 0x013b 10672 #define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 10673 #define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2 0x013c 10674 #define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 10675 #define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3 0x013d 10676 #define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 10677 #define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL 0x013e 10678 #define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL_BASE_IDX 2 10679 #define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL 0x013f 10680 #define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL_BASE_IDX 2 10681 #define regBIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX 0x0140 10682 #define regBIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX_BASE_IDX 2 10683 10684 10685 // addressBlock: nbif_bif_bx_dev0_epf0_vf18_SYSPFVFDEC 10686 // base address: 0x0 10687 #define regBIF_BX_DEV0_EPF0_VF18_MM_INDEX 0x0000 10688 #define regBIF_BX_DEV0_EPF0_VF18_MM_INDEX_BASE_IDX 0 10689 #define regBIF_BX_DEV0_EPF0_VF18_MM_DATA 0x0001 10690 #define regBIF_BX_DEV0_EPF0_VF18_MM_DATA_BASE_IDX 0 10691 #define regBIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI 0x0006 10692 #define regBIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI_BASE_IDX 0 10693 10694 10695 // addressBlock: nbif_rcc_dev0_epf0_vf18_BIFPFVFDEC1 10696 // base address: 0x0 10697 #define regRCC_DEV0_EPF0_VF18_RCC_ERR_LOG 0x0085 10698 #define regRCC_DEV0_EPF0_VF18_RCC_ERR_LOG_BASE_IDX 2 10699 #define regRCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN 0x00c0 10700 #define regRCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN_BASE_IDX 2 10701 #define regRCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE 0x00c3 10702 #define regRCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE_BASE_IDX 2 10703 #define regRCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED 0x00c4 10704 #define regRCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED_BASE_IDX 2 10705 #define regRCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER 0x00c5 10706 #define regRCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 10707 10708 10709 // addressBlock: nbif_rcc_dev0_epf0_vf18_BIFDEC2 10710 // base address: 0x0 10711 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO 0x0400 10712 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 10713 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI 0x0401 10714 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 10715 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA 0x0402 10716 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 10717 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL 0x0403 10718 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 10719 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO 0x0404 10720 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 10721 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI 0x0405 10722 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 10723 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA 0x0406 10724 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 10725 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL 0x0407 10726 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 10727 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO 0x0408 10728 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 10729 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI 0x0409 10730 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 10731 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA 0x040a 10732 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 10733 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL 0x040b 10734 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 10735 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO 0x040c 10736 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 10737 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI 0x040d 10738 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 10739 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA 0x040e 10740 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 10741 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL 0x040f 10742 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 10743 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_PBA 0x0800 10744 #define regRCC_DEV0_EPF0_VF18_GFXMSIX_PBA_BASE_IDX 3 10745 10746 10747 // addressBlock: nbif_bif_bx_dev0_epf0_vf19_BIFPFVFDEC1 10748 // base address: 0x0 10749 #define regBIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS 0x00eb 10750 #define regBIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS_BASE_IDX 2 10751 #define regBIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG 0x00ec 10752 #define regBIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 10753 #define regBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 10754 #define regBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 10755 #define regBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 10756 #define regBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 10757 #define regBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 10758 #define regBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 10759 #define regBIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 10760 #define regBIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 10761 #define regBIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 10762 #define regBIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 10763 #define regBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ 0x0106 10764 #define regBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ_BASE_IDX 2 10765 #define regBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE 0x0107 10766 #define regBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE_BASE_IDX 2 10767 #define regBIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING 0x0108 10768 #define regBIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING_BASE_IDX 2 10769 #define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0 0x0136 10770 #define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 10771 #define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1 0x0137 10772 #define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 10773 #define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2 0x0138 10774 #define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 10775 #define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3 0x0139 10776 #define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 10777 #define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0 0x013a 10778 #define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 10779 #define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1 0x013b 10780 #define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 10781 #define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2 0x013c 10782 #define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 10783 #define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3 0x013d 10784 #define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 10785 #define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL 0x013e 10786 #define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL_BASE_IDX 2 10787 #define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL 0x013f 10788 #define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL_BASE_IDX 2 10789 #define regBIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX 0x0140 10790 #define regBIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX_BASE_IDX 2 10791 10792 10793 // addressBlock: nbif_bif_bx_dev0_epf0_vf19_SYSPFVFDEC 10794 // base address: 0x0 10795 #define regBIF_BX_DEV0_EPF0_VF19_MM_INDEX 0x0000 10796 #define regBIF_BX_DEV0_EPF0_VF19_MM_INDEX_BASE_IDX 0 10797 #define regBIF_BX_DEV0_EPF0_VF19_MM_DATA 0x0001 10798 #define regBIF_BX_DEV0_EPF0_VF19_MM_DATA_BASE_IDX 0 10799 #define regBIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI 0x0006 10800 #define regBIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI_BASE_IDX 0 10801 10802 10803 // addressBlock: nbif_rcc_dev0_epf0_vf19_BIFPFVFDEC1 10804 // base address: 0x0 10805 #define regRCC_DEV0_EPF0_VF19_RCC_ERR_LOG 0x0085 10806 #define regRCC_DEV0_EPF0_VF19_RCC_ERR_LOG_BASE_IDX 2 10807 #define regRCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN 0x00c0 10808 #define regRCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN_BASE_IDX 2 10809 #define regRCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE 0x00c3 10810 #define regRCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE_BASE_IDX 2 10811 #define regRCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED 0x00c4 10812 #define regRCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED_BASE_IDX 2 10813 #define regRCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER 0x00c5 10814 #define regRCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 10815 10816 10817 // addressBlock: nbif_rcc_dev0_epf0_vf19_BIFDEC2 10818 // base address: 0x0 10819 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO 0x0400 10820 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 10821 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI 0x0401 10822 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 10823 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA 0x0402 10824 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 10825 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL 0x0403 10826 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 10827 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO 0x0404 10828 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 10829 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI 0x0405 10830 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 10831 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA 0x0406 10832 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 10833 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL 0x0407 10834 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 10835 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO 0x0408 10836 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 10837 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI 0x0409 10838 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 10839 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA 0x040a 10840 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 10841 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL 0x040b 10842 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 10843 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO 0x040c 10844 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 10845 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI 0x040d 10846 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 10847 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA 0x040e 10848 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 10849 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL 0x040f 10850 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 10851 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_PBA 0x0800 10852 #define regRCC_DEV0_EPF0_VF19_GFXMSIX_PBA_BASE_IDX 3 10853 10854 10855 // addressBlock: nbif_bif_bx_dev0_epf0_vf20_BIFPFVFDEC1 10856 // base address: 0x0 10857 #define regBIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS 0x00eb 10858 #define regBIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS_BASE_IDX 2 10859 #define regBIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG 0x00ec 10860 #define regBIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 10861 #define regBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 10862 #define regBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 10863 #define regBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 10864 #define regBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 10865 #define regBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 10866 #define regBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 10867 #define regBIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 10868 #define regBIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 10869 #define regBIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 10870 #define regBIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 10871 #define regBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ 0x0106 10872 #define regBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ_BASE_IDX 2 10873 #define regBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE 0x0107 10874 #define regBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE_BASE_IDX 2 10875 #define regBIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING 0x0108 10876 #define regBIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING_BASE_IDX 2 10877 #define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0 0x0136 10878 #define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 10879 #define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1 0x0137 10880 #define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 10881 #define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2 0x0138 10882 #define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 10883 #define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3 0x0139 10884 #define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 10885 #define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0 0x013a 10886 #define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 10887 #define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1 0x013b 10888 #define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 10889 #define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2 0x013c 10890 #define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 10891 #define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3 0x013d 10892 #define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 10893 #define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL 0x013e 10894 #define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL_BASE_IDX 2 10895 #define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL 0x013f 10896 #define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL_BASE_IDX 2 10897 #define regBIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX 0x0140 10898 #define regBIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX_BASE_IDX 2 10899 10900 10901 // addressBlock: nbif_bif_bx_dev0_epf0_vf20_SYSPFVFDEC 10902 // base address: 0x0 10903 #define regBIF_BX_DEV0_EPF0_VF20_MM_INDEX 0x0000 10904 #define regBIF_BX_DEV0_EPF0_VF20_MM_INDEX_BASE_IDX 0 10905 #define regBIF_BX_DEV0_EPF0_VF20_MM_DATA 0x0001 10906 #define regBIF_BX_DEV0_EPF0_VF20_MM_DATA_BASE_IDX 0 10907 #define regBIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI 0x0006 10908 #define regBIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI_BASE_IDX 0 10909 10910 10911 // addressBlock: nbif_rcc_dev0_epf0_vf20_BIFPFVFDEC1 10912 // base address: 0x0 10913 #define regRCC_DEV0_EPF0_VF20_RCC_ERR_LOG 0x0085 10914 #define regRCC_DEV0_EPF0_VF20_RCC_ERR_LOG_BASE_IDX 2 10915 #define regRCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN 0x00c0 10916 #define regRCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN_BASE_IDX 2 10917 #define regRCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE 0x00c3 10918 #define regRCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE_BASE_IDX 2 10919 #define regRCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED 0x00c4 10920 #define regRCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED_BASE_IDX 2 10921 #define regRCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER 0x00c5 10922 #define regRCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 10923 10924 10925 // addressBlock: nbif_rcc_dev0_epf0_vf20_BIFDEC2 10926 // base address: 0x0 10927 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO 0x0400 10928 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 10929 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI 0x0401 10930 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 10931 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA 0x0402 10932 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 10933 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL 0x0403 10934 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 10935 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO 0x0404 10936 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 10937 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI 0x0405 10938 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 10939 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA 0x0406 10940 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 10941 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL 0x0407 10942 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 10943 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO 0x0408 10944 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 10945 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI 0x0409 10946 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 10947 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA 0x040a 10948 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 10949 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL 0x040b 10950 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 10951 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO 0x040c 10952 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 10953 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI 0x040d 10954 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 10955 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA 0x040e 10956 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 10957 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL 0x040f 10958 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 10959 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_PBA 0x0800 10960 #define regRCC_DEV0_EPF0_VF20_GFXMSIX_PBA_BASE_IDX 3 10961 10962 10963 // addressBlock: nbif_bif_bx_dev0_epf0_vf21_BIFPFVFDEC1 10964 // base address: 0x0 10965 #define regBIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS 0x00eb 10966 #define regBIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS_BASE_IDX 2 10967 #define regBIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG 0x00ec 10968 #define regBIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 10969 #define regBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 10970 #define regBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 10971 #define regBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 10972 #define regBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 10973 #define regBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 10974 #define regBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 10975 #define regBIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 10976 #define regBIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 10977 #define regBIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 10978 #define regBIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 10979 #define regBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ 0x0106 10980 #define regBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ_BASE_IDX 2 10981 #define regBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE 0x0107 10982 #define regBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE_BASE_IDX 2 10983 #define regBIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING 0x0108 10984 #define regBIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING_BASE_IDX 2 10985 #define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0 0x0136 10986 #define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 10987 #define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1 0x0137 10988 #define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 10989 #define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2 0x0138 10990 #define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 10991 #define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3 0x0139 10992 #define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 10993 #define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0 0x013a 10994 #define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 10995 #define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1 0x013b 10996 #define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 10997 #define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2 0x013c 10998 #define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 10999 #define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3 0x013d 11000 #define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 11001 #define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL 0x013e 11002 #define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL_BASE_IDX 2 11003 #define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL 0x013f 11004 #define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL_BASE_IDX 2 11005 #define regBIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX 0x0140 11006 #define regBIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX_BASE_IDX 2 11007 11008 11009 // addressBlock: nbif_bif_bx_dev0_epf0_vf21_SYSPFVFDEC 11010 // base address: 0x0 11011 #define regBIF_BX_DEV0_EPF0_VF21_MM_INDEX 0x0000 11012 #define regBIF_BX_DEV0_EPF0_VF21_MM_INDEX_BASE_IDX 0 11013 #define regBIF_BX_DEV0_EPF0_VF21_MM_DATA 0x0001 11014 #define regBIF_BX_DEV0_EPF0_VF21_MM_DATA_BASE_IDX 0 11015 #define regBIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI 0x0006 11016 #define regBIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI_BASE_IDX 0 11017 11018 11019 // addressBlock: nbif_rcc_dev0_epf0_vf21_BIFPFVFDEC1 11020 // base address: 0x0 11021 #define regRCC_DEV0_EPF0_VF21_RCC_ERR_LOG 0x0085 11022 #define regRCC_DEV0_EPF0_VF21_RCC_ERR_LOG_BASE_IDX 2 11023 #define regRCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN 0x00c0 11024 #define regRCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN_BASE_IDX 2 11025 #define regRCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE 0x00c3 11026 #define regRCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE_BASE_IDX 2 11027 #define regRCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED 0x00c4 11028 #define regRCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED_BASE_IDX 2 11029 #define regRCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER 0x00c5 11030 #define regRCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 11031 11032 11033 // addressBlock: nbif_rcc_dev0_epf0_vf21_BIFDEC2 11034 // base address: 0x0 11035 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO 0x0400 11036 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 11037 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI 0x0401 11038 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 11039 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA 0x0402 11040 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 11041 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL 0x0403 11042 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 11043 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO 0x0404 11044 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 11045 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI 0x0405 11046 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 11047 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA 0x0406 11048 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 11049 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL 0x0407 11050 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 11051 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO 0x0408 11052 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 11053 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI 0x0409 11054 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 11055 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA 0x040a 11056 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 11057 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL 0x040b 11058 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 11059 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO 0x040c 11060 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 11061 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI 0x040d 11062 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 11063 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA 0x040e 11064 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 11065 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL 0x040f 11066 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 11067 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_PBA 0x0800 11068 #define regRCC_DEV0_EPF0_VF21_GFXMSIX_PBA_BASE_IDX 3 11069 11070 11071 // addressBlock: nbif_bif_bx_dev0_epf0_vf22_BIFPFVFDEC1 11072 // base address: 0x0 11073 #define regBIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS 0x00eb 11074 #define regBIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS_BASE_IDX 2 11075 #define regBIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG 0x00ec 11076 #define regBIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 11077 #define regBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 11078 #define regBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 11079 #define regBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 11080 #define regBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 11081 #define regBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 11082 #define regBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 11083 #define regBIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 11084 #define regBIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 11085 #define regBIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 11086 #define regBIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 11087 #define regBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ 0x0106 11088 #define regBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ_BASE_IDX 2 11089 #define regBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE 0x0107 11090 #define regBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE_BASE_IDX 2 11091 #define regBIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING 0x0108 11092 #define regBIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING_BASE_IDX 2 11093 #define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0 0x0136 11094 #define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 11095 #define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1 0x0137 11096 #define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 11097 #define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2 0x0138 11098 #define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 11099 #define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3 0x0139 11100 #define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 11101 #define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0 0x013a 11102 #define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 11103 #define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1 0x013b 11104 #define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 11105 #define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2 0x013c 11106 #define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 11107 #define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3 0x013d 11108 #define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 11109 #define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL 0x013e 11110 #define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL_BASE_IDX 2 11111 #define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL 0x013f 11112 #define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL_BASE_IDX 2 11113 #define regBIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX 0x0140 11114 #define regBIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX_BASE_IDX 2 11115 11116 11117 // addressBlock: nbif_bif_bx_dev0_epf0_vf22_SYSPFVFDEC 11118 // base address: 0x0 11119 #define regBIF_BX_DEV0_EPF0_VF22_MM_INDEX 0x0000 11120 #define regBIF_BX_DEV0_EPF0_VF22_MM_INDEX_BASE_IDX 0 11121 #define regBIF_BX_DEV0_EPF0_VF22_MM_DATA 0x0001 11122 #define regBIF_BX_DEV0_EPF0_VF22_MM_DATA_BASE_IDX 0 11123 #define regBIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI 0x0006 11124 #define regBIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI_BASE_IDX 0 11125 11126 11127 // addressBlock: nbif_rcc_dev0_epf0_vf22_BIFPFVFDEC1 11128 // base address: 0x0 11129 #define regRCC_DEV0_EPF0_VF22_RCC_ERR_LOG 0x0085 11130 #define regRCC_DEV0_EPF0_VF22_RCC_ERR_LOG_BASE_IDX 2 11131 #define regRCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN 0x00c0 11132 #define regRCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN_BASE_IDX 2 11133 #define regRCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE 0x00c3 11134 #define regRCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE_BASE_IDX 2 11135 #define regRCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED 0x00c4 11136 #define regRCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED_BASE_IDX 2 11137 #define regRCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER 0x00c5 11138 #define regRCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 11139 11140 11141 // addressBlock: nbif_rcc_dev0_epf0_vf22_BIFDEC2 11142 // base address: 0x0 11143 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO 0x0400 11144 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 11145 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI 0x0401 11146 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 11147 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA 0x0402 11148 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 11149 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL 0x0403 11150 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 11151 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO 0x0404 11152 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 11153 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI 0x0405 11154 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 11155 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA 0x0406 11156 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 11157 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL 0x0407 11158 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 11159 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO 0x0408 11160 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 11161 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI 0x0409 11162 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 11163 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA 0x040a 11164 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 11165 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL 0x040b 11166 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 11167 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO 0x040c 11168 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 11169 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI 0x040d 11170 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 11171 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA 0x040e 11172 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 11173 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL 0x040f 11174 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 11175 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_PBA 0x0800 11176 #define regRCC_DEV0_EPF0_VF22_GFXMSIX_PBA_BASE_IDX 3 11177 11178 11179 // addressBlock: nbif_bif_bx_dev0_epf0_vf23_BIFPFVFDEC1 11180 // base address: 0x0 11181 #define regBIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS 0x00eb 11182 #define regBIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS_BASE_IDX 2 11183 #define regBIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG 0x00ec 11184 #define regBIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 11185 #define regBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 11186 #define regBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 11187 #define regBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 11188 #define regBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 11189 #define regBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 11190 #define regBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 11191 #define regBIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 11192 #define regBIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 11193 #define regBIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 11194 #define regBIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 11195 #define regBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ 0x0106 11196 #define regBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ_BASE_IDX 2 11197 #define regBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE 0x0107 11198 #define regBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE_BASE_IDX 2 11199 #define regBIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING 0x0108 11200 #define regBIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING_BASE_IDX 2 11201 #define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0 0x0136 11202 #define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 11203 #define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1 0x0137 11204 #define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 11205 #define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2 0x0138 11206 #define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 11207 #define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3 0x0139 11208 #define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 11209 #define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0 0x013a 11210 #define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 11211 #define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1 0x013b 11212 #define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 11213 #define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2 0x013c 11214 #define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 11215 #define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3 0x013d 11216 #define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 11217 #define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL 0x013e 11218 #define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL_BASE_IDX 2 11219 #define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL 0x013f 11220 #define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL_BASE_IDX 2 11221 #define regBIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX 0x0140 11222 #define regBIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX_BASE_IDX 2 11223 11224 11225 // addressBlock: nbif_bif_bx_dev0_epf0_vf23_SYSPFVFDEC 11226 // base address: 0x0 11227 #define regBIF_BX_DEV0_EPF0_VF23_MM_INDEX 0x0000 11228 #define regBIF_BX_DEV0_EPF0_VF23_MM_INDEX_BASE_IDX 0 11229 #define regBIF_BX_DEV0_EPF0_VF23_MM_DATA 0x0001 11230 #define regBIF_BX_DEV0_EPF0_VF23_MM_DATA_BASE_IDX 0 11231 #define regBIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI 0x0006 11232 #define regBIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI_BASE_IDX 0 11233 11234 11235 // addressBlock: nbif_rcc_dev0_epf0_vf23_BIFPFVFDEC1 11236 // base address: 0x0 11237 #define regRCC_DEV0_EPF0_VF23_RCC_ERR_LOG 0x0085 11238 #define regRCC_DEV0_EPF0_VF23_RCC_ERR_LOG_BASE_IDX 2 11239 #define regRCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN 0x00c0 11240 #define regRCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN_BASE_IDX 2 11241 #define regRCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE 0x00c3 11242 #define regRCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE_BASE_IDX 2 11243 #define regRCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED 0x00c4 11244 #define regRCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED_BASE_IDX 2 11245 #define regRCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER 0x00c5 11246 #define regRCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 11247 11248 11249 // addressBlock: nbif_rcc_dev0_epf0_vf23_BIFDEC2 11250 // base address: 0x0 11251 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO 0x0400 11252 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 11253 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI 0x0401 11254 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 11255 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA 0x0402 11256 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 11257 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL 0x0403 11258 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 11259 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO 0x0404 11260 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 11261 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI 0x0405 11262 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 11263 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA 0x0406 11264 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 11265 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL 0x0407 11266 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 11267 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO 0x0408 11268 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 11269 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI 0x0409 11270 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 11271 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA 0x040a 11272 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 11273 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL 0x040b 11274 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 11275 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO 0x040c 11276 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 11277 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI 0x040d 11278 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 11279 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA 0x040e 11280 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 11281 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL 0x040f 11282 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 11283 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_PBA 0x0800 11284 #define regRCC_DEV0_EPF0_VF23_GFXMSIX_PBA_BASE_IDX 3 11285 11286 11287 #endif 11288