Searched refs:regMP1_SMN_IH_SW_INT_CTRL (Results 1 – 11 of 11) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/mp/ |
| D | mp_14_0_0_offset.h | 289 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| D | mp_13_0_4_offset.h | 380 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| D | mp_13_0_8_offset.h | 382 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| D | mp_13_0_2_offset.h | 387 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| D | mp_14_0_2_offset.h | 289 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| D | mp_13_0_6_offset.h | 380 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| D | mp_13_0_5_offset.h | 381 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| D | mp_13_0_0_offset.h | 379 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| /linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| D | smu_v13_0.c | 1278 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v13_0_set_irq_state()
1280 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); in smu_v13_0_set_irq_state()
1311 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v13_0_set_irq_state()
1313 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); in smu_v13_0_set_irq_state()
1373 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v13_0_irq_process()
1375 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data); in smu_v13_0_irq_process()
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| D | smu_v13_0_6_ppt.c | 1544 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v13_0_6_irq_process()
1546 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data); in smu_v13_0_6_irq_process()
1594 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v13_0_6_set_irq_state()
1596 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); in smu_v13_0_6_set_irq_state()
1606 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v13_0_6_set_irq_state()
1608 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); in smu_v13_0_6_set_irq_state()
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| /linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| D | smu_v14_0.c | 883 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v14_0_set_irq_state()
885 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); in smu_v14_0_set_irq_state()
926 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v14_0_set_irq_state()
928 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); in smu_v14_0_set_irq_state()
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