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Searched refs:regMMVM_L2_CNTL (Results 1 – 10 of 10) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dmmhub_v3_0_2.c233 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_2_init_cache_regs()
244 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); in mmhub_v3_0_2_init_cache_regs()
409 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_2_gart_disable()
411 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); in mmhub_v3_0_2_gart_disable()
Dmmhub_v3_0_1.c234 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_1_init_cache_regs()
245 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); in mmhub_v3_0_1_init_cache_regs()
404 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_1_gart_disable()
406 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); in mmhub_v3_0_1_gart_disable()
Dmmhub_v3_3.c230 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_3_init_cache_regs()
241 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); in mmhub_v3_3_init_cache_regs()
450 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_3_gart_disable()
452 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); in mmhub_v3_3_gart_disable()
Dmmhub_v3_0.c241 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_init_cache_regs()
252 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); in mmhub_v3_0_init_cache_regs()
417 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_gart_disable()
419 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); in mmhub_v3_0_gart_disable()
Dmmhub_v4_1_0.c242 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v4_1_0_init_cache_regs()
253 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); in mmhub_v4_1_0_init_cache_regs()
418 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v4_1_0_gart_disable()
420 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); in mmhub_v4_1_0_gart_disable()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/mmhub/
Dmmhub_4_1_0_offset.h730 #define regMMVM_L2_CNTL … macro
Dmmhub_3_3_0_offset.h654 #define regMMVM_L2_CNTL … macro
Dmmhub_3_0_0_offset.h782 #define regMMVM_L2_CNTL … macro
Dmmhub_3_0_2_offset.h740 #define regMMVM_L2_CNTL … macro
Dmmhub_3_0_1_offset.h1034 #define regMMVM_L2_CNTL … macro