Searched refs:regGCVM_L2_CNTL3 (Results 1 – 11 of 11) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | imu_v11_0.c | 222 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0xe0000000),
305 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0xe0000000),
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| D | gfxhub_v3_0_3.c | 248 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); in gfxhub_v3_0_3_init_cache_regs()
393 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0); in gfxhub_v3_0_3_gart_disable()
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| D | imu_v11_0_3.c | 85 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0xe0000000),
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| D | gfxhub_v3_0.c | 243 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); in gfxhub_v3_0_init_cache_regs()
400 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0); in gfxhub_v3_0_gart_disable()
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| D | gfxhub_v12_0.c | 251 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); in gfxhub_v12_0_init_cache_regs()
408 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0); in gfxhub_v12_0_gart_disable()
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| D | gfxhub_v11_5_0.c | 246 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); in gfxhub_v11_5_0_init_cache_regs()
403 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0); in gfxhub_v11_5_0_gart_disable()
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| D | imu_v12_0.c | 243 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0x1c0000),
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_11_5_0_offset.h | 1863 #define regGCVM_L2_CNTL3 … macro
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| D | gc_12_0_0_offset.h | 2770 #define regGCVM_L2_CNTL3 … macro
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| D | gc_11_0_0_offset.h | 2734 #define regGCVM_L2_CNTL3 … macro
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| D | gc_11_0_3_offset.h | 2876 #define regGCVM_L2_CNTL3 … macro
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