Searched refs:regGCVM_L2_CNTL (Results 1 – 11 of 11) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | imu_v11_0.c | 220 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0xe0000000),
303 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0xe0000000),
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| D | gfxhub_v3_0_3.c | 220 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL); in gfxhub_v3_0_3_init_cache_regs()
231 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp); in gfxhub_v3_0_3_init_cache_regs()
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| D | imu_v11_0_3.c | 83 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0xe0000000),
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| D | gfxhub_v3_0.c | 215 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL); in gfxhub_v3_0_init_cache_regs()
226 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp); in gfxhub_v3_0_init_cache_regs()
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| D | gfxhub_v12_0.c | 223 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL); in gfxhub_v12_0_init_cache_regs()
234 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp); in gfxhub_v12_0_init_cache_regs()
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| D | gfxhub_v11_5_0.c | 218 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL); in gfxhub_v11_5_0_init_cache_regs()
229 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp); in gfxhub_v11_5_0_init_cache_regs()
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| D | imu_v12_0.c | 241 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0x1c0000),
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_11_5_0_offset.h | 1859 #define regGCVM_L2_CNTL … macro
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| D | gc_12_0_0_offset.h | 2766 #define regGCVM_L2_CNTL … macro
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| D | gc_11_0_0_offset.h | 2730 #define regGCVM_L2_CNTL … macro
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| D | gc_11_0_3_offset.h | 2872 #define regGCVM_L2_CNTL … macro
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