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Searched refs:regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_5_1_offset.h10485 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
Ddcn_3_1_2_offset.h12482 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
Ddcn_3_2_1_offset.h11731 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
Ddcn_3_2_0_offset.h11722 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
Ddcn_3_1_5_offset.h12347 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
Ddcn_3_1_4_offset.h11607 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
Ddcn_3_5_0_offset.h10506 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
Ddcn_3_1_6_offset.h13078 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro