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Searched refs:regCP_ME_IC_OP_CNTL (Results 1 – 6 of 6) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dgfx_v11_0.c2311 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache()
2313 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache()
2317 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache()
2585 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2598 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2600 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2604 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
3291 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3304 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3306 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
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Dgfx_v12_0.c2430 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2443 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2445 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2449 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_11_5_0_offset.h8405 #define regCP_ME_IC_OP_CNTL … macro
Dgc_12_0_0_offset.h6210 #define regCP_ME_IC_OP_CNTL … macro
Dgc_11_0_0_offset.h9734 #define regCP_ME_IC_OP_CNTL … macro
Dgc_11_0_3_offset.h10284 #define regCP_ME_IC_OP_CNTL … macro