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Searched refs:regCP_ME_CNTL (Results 1 – 8 of 8) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dgfx_v11_0.c2506 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2513 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2522 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2629 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_me_cache_rs64()
2636 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2645 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2790 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
2793 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2798 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2812 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
[all …]
Dgfx_v12_0.c1994 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v12_0_config_gfx_rs64()
1997 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2002 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2016 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v12_0_config_gfx_rs64()
2019 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2024 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2073 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v12_0_set_pfp_ucode_start_addr()
2080 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_set_pfp_ucode_start_addr()
2089 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_set_pfp_ucode_start_addr()
2115 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v12_0_set_me_ucode_start_addr()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_2_offset.h239 #define regCP_ME_CNTL … macro
Dgc_9_4_3_offset.h196 #define regCP_ME_CNTL … macro
Dgc_11_5_0_offset.h5013 #define regCP_ME_CNTL … macro
Dgc_12_0_0_offset.h4058 #define regCP_ME_CNTL … macro
Dgc_11_0_0_offset.h6198 #define regCP_ME_CNTL … macro
Dgc_11_0_3_offset.h6478 #define regCP_ME_CNTL … macro