Searched refs:regCP_MEC_DC_OP_CNTL (Results 1 – 6 of 6) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v11_0.c | 2724 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2726 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2730 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
3817 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3819 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
3823 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
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| D | gfx_v12_0.c | 2766 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v12_0_cp_compute_load_microcode_rs64()
2768 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); in gfx_v12_0_cp_compute_load_microcode_rs64()
2772 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v12_0_cp_compute_load_microcode_rs64()
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_11_5_0_offset.h | 6551 #define regCP_MEC_DC_OP_CNTL … macro
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| D | gc_12_0_0_offset.h | 4968 #define regCP_MEC_DC_OP_CNTL … macro
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| D | gc_11_0_0_offset.h | 7778 #define regCP_MEC_DC_OP_CNTL … macro
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| D | gc_11_0_3_offset.h | 8082 #define regCP_MEC_DC_OP_CNTL … macro
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