Searched refs:regCP_INT_CNTL_RING0 (Results 1 – 9 of 9) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v9_4_3.c | 1479 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); in gfx_v9_4_3_xcc_enable_gui_idle_interrupt()
1485 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); in gfx_v9_4_3_xcc_enable_gui_idle_interrupt()
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| D | gfx_v12_0.c | 1708 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v12_0_get_cpg_int_cntl()
4646 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v12_0_set_gfx_eop_interrupt_state()
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| D | gfx_v11_0.c | 1989 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v11_0_get_cpg_int_cntl()
6109 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v11_0_set_gfx_eop_interrupt_state()
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_4_2_offset.h | 437 #define regCP_INT_CNTL_RING0 … macro
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| D | gc_9_4_3_offset.h | 2890 #define regCP_INT_CNTL_RING0 … macro
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| D | gc_11_5_0_offset.h | 3179 #define regCP_INT_CNTL_RING0 … macro
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| D | gc_12_0_0_offset.h | 3528 #define regCP_INT_CNTL_RING0 … macro
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| D | gc_11_0_0_offset.h | 4198 #define regCP_INT_CNTL_RING0 … macro
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| D | gc_11_0_3_offset.h | 4416 #define regCP_INT_CNTL_RING0 … macro
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