Searched refs:regCP_HQD_PQ_CONTROL (Results 1 – 11 of 11) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | mes_v12_0.c | 1148 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); in mes_v12_0_queue_init_register()
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| D | gfx_v9_4_3.c | 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
1871 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); in gfx_v9_4_3_xcc_mqd_init()
1983 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, in gfx_v9_4_3_xcc_kiq_init_register()
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| D | mes_v11_0.c | 1175 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); in mes_v11_0_queue_init_register()
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| D | gfx_v12_0.c | 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
3056 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); in gfx_v12_0_compute_mqd_init()
3181 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, in gfx_v12_0_kiq_init_register()
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| D | gfx_v11_0.c | 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
4111 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); in gfx_v11_0_compute_mqd_init()
4237 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, in gfx_v11_0_kiq_init_register()
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_4_2_offset.h | 725 #define regCP_HQD_PQ_CONTROL … macro
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| D | gc_9_4_3_offset.h | 3314 #define regCP_HQD_PQ_CONTROL … macro
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| D | gc_11_5_0_offset.h | 3605 #define regCP_HQD_PQ_CONTROL … macro
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| D | gc_12_0_0_offset.h | 3874 #define regCP_HQD_PQ_CONTROL … macro
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| D | gc_11_0_0_offset.h | 4632 #define regCP_HQD_PQ_CONTROL … macro
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| D | gc_11_0_3_offset.h | 4856 #define regCP_HQD_PQ_CONTROL … macro
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