Searched refs:regCP_CPC_IC_OP_CNTL (Results 1 – 8 of 8) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v11_0.c | 2399 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache()
2402 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v11_0_config_mec_cache()
2406 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache()
2743 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2745 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2749 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
3836 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3838 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
3842 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
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| D | gfx_v12_0.c | 2785 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v12_0_cp_compute_load_microcode_rs64()
2787 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v12_0_cp_compute_load_microcode_rs64()
2791 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v12_0_cp_compute_load_microcode_rs64()
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_4_2_offset.h | 587 #define regCP_CPC_IC_OP_CNTL … macro
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| D | gc_9_4_3_offset.h | 3048 #define regCP_CPC_IC_OP_CNTL … macro
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| D | gc_11_5_0_offset.h | 6757 #define regCP_CPC_IC_OP_CNTL … macro
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| D | gc_12_0_0_offset.h | 5176 #define regCP_CPC_IC_OP_CNTL … macro
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| D | gc_11_0_0_offset.h | 7984 #define regCP_CPC_IC_OP_CNTL … macro
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| D | gc_11_0_3_offset.h | 8288 #define regCP_CPC_IC_OP_CNTL … macro
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