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Searched refs:regBIF_BX1_BIF_S5_MEM_POWER_CTRL0_BASE_IDX (Results 1 – 3 of 3) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/nbif/
Dnbif_6_3_1_offset.h8084 #define regBIF_BX1_BIF_S5_MEM_POWER_CTRL0_BASE_IDX … macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_4_3_0_offset.h14411 #define regBIF_BX1_BIF_S5_MEM_POWER_CTRL0_BASE_IDX … macro
Dnbio_7_2_0_offset.h6469 #define regBIF_BX1_BIF_S5_MEM_POWER_CTRL0_BASE_IDX … macro