/linux-6.12.1/drivers/pci/pcie/ |
D | aer.c | 146 u32 reg32; in enable_ecrc_checking() local 151 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32); in enable_ecrc_checking() 152 if (reg32 & PCI_ERR_CAP_ECRC_GENC) in enable_ecrc_checking() 153 reg32 |= PCI_ERR_CAP_ECRC_GENE; in enable_ecrc_checking() 154 if (reg32 & PCI_ERR_CAP_ECRC_CHKC) in enable_ecrc_checking() 155 reg32 |= PCI_ERR_CAP_ECRC_CHKE; in enable_ecrc_checking() 156 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32); in enable_ecrc_checking() 170 u32 reg32; in disable_ecrc_checking() local 175 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32); in disable_ecrc_checking() 176 reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); in disable_ecrc_checking() [all …]
|
D | portdrv.c | 79 u32 reg32; in pcie_message_numbers() local 84 ®32); in pcie_message_numbers() 85 *aer = FIELD_GET(PCI_ERR_ROOT_AER_IRQ, reg32); in pcie_message_numbers()
|
D | aspm.c | 359 u32 reg32; in pcie_clkpm_cap_init() local 366 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32); in pcie_clkpm_cap_init() 367 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { in pcie_clkpm_cap_init() 982 u32 reg32; in pcie_aspm_sanity_check() local 1005 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32); in pcie_aspm_sanity_check() 1006 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) { in pcie_aspm_sanity_check()
|
/linux-6.12.1/drivers/infiniband/hw/hfi1/ |
D | aspm.c | 49 u32 reg32; in aspm_hw_set_l1_ent_latency() local 51 pci_read_config_dword(dd->pcidev, PCIE_CFG_REG_PL3, ®32); in aspm_hw_set_l1_ent_latency() 52 reg32 &= ~PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SMASK; in aspm_hw_set_l1_ent_latency() 53 reg32 |= l1_ent_lat << PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SHIFT; in aspm_hw_set_l1_ent_latency() 54 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL3, reg32); in aspm_hw_set_l1_ent_latency()
|
D | pcie.c | 940 u32 reg32, fs, lf; in do_pcie_gen3_transition() local 1062 reg32 = 0x10ul << PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT; in do_pcie_gen3_transition() 1063 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); in do_pcie_gen3_transition() 1072 reg32 = PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK; in do_pcie_gen3_transition() 1073 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); in do_pcie_gen3_transition() 1317 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, ®32); in do_pcie_gen3_transition() 1324 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); in do_pcie_gen3_transition()
|
/linux-6.12.1/drivers/pci/ |
D | pci-acpi.c | 311 u32 reg32; in program_hpx_type2() local 361 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32); in program_hpx_type2() 362 reg32 = (reg32 & hpx->unc_err_mask_and) | hpx->unc_err_mask_or; in program_hpx_type2() 363 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32); in program_hpx_type2() 366 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32); in program_hpx_type2() 367 reg32 = (reg32 & hpx->unc_err_sever_and) | hpx->unc_err_sever_or; in program_hpx_type2() 368 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32); in program_hpx_type2() 371 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32); in program_hpx_type2() 372 reg32 = (reg32 & hpx->cor_err_mask_and) | hpx->cor_err_mask_or; in program_hpx_type2() 373 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32); in program_hpx_type2() [all …]
|
D | probe.c | 1562 u32 reg32; in set_pcie_port_type() local 1576 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32); in set_pcie_port_type() 1577 if (reg32 & PCI_EXP_LNKCAP_DLLLARC) in set_pcie_port_type() 1617 u32 reg32; in set_pcie_hotplug_bridge() local 1619 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); in set_pcie_hotplug_bridge() 1620 if (reg32 & PCI_EXP_SLTCAP_HPC) in set_pcie_hotplug_bridge()
|
/linux-6.12.1/drivers/net/wireless/ath/ath9k/ |
D | ar9002_phy.c | 69 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; in ar9002_hw_set_channel() local 76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ar9002_hw_set_channel() 77 reg32 &= 0xc0000000; in ar9002_hw_set_channel() 149 reg32 = reg32 | in ar9002_hw_set_channel() 153 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9002_hw_set_channel()
|
D | ar5008_phy.c | 111 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, in ar5008_hw_phy_modify_rx_buffer() argument 118 tmp32 = ath9k_hw_reverse_bits(reg32, numBits); in ar5008_hw_phy_modify_rx_buffer() 209 u32 reg32 = 0; in ar5008_hw_set_channel() local 264 reg32 = in ar5008_hw_set_channel() 268 REG_WRITE(ah, AR_PHY(0x37), reg32); in ar5008_hw_set_channel()
|
D | ar9003_phy.c | 152 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0; in ar9003_hw_set_channel() local 205 reg32 = (bMode << 29); in ar9003_hw_set_channel() 206 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9003_hw_set_channel() 213 reg32 = (channelSel << 2) | (fracMode << 30) | in ar9003_hw_set_channel() 215 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel() 219 reg32 = (channelSel << 2) | (fracMode << 30) | in ar9003_hw_set_channel() 221 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
|
D | eeprom_4k.c | 296 u32 reg32, regOffset, regChainOffset; in ath9k_hw_set_4k_power_cal_table() local 360 reg32 = get_unaligned_le32(&pdadcValues[4 * j]); in ath9k_hw_set_4k_power_cal_table() 361 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_4k_power_cal_table() 366 reg32); in ath9k_hw_set_4k_power_cal_table()
|
D | eeprom_def.c | 778 u32 reg32, regOffset, regChainOffset; in ath9k_hw_set_def_power_cal_table() local 895 reg32 = get_unaligned_le32(&pdadcValues[4 * j]); in ath9k_hw_set_def_power_cal_table() 896 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_def_power_cal_table() 901 reg32); in ath9k_hw_set_def_power_cal_table()
|
D | eeprom_9287.c | 365 u32 reg32, regOffset, regChainOffset, regval; in ath9k_hw_set_ar9287_power_cal_table() local 480 reg32 = get_unaligned_le32(&pdadcValues[4 * j]); in ath9k_hw_set_ar9287_power_cal_table() 482 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_ar9287_power_cal_table()
|
/linux-6.12.1/drivers/ipack/carriers/ |
D | tpci200.c | 522 u32 reg32; in tpci200_pci_probe() local 556 reg32 = ioread32(tpci200->info->cfg_regs + LAS1_DESC); in tpci200_pci_probe() 557 reg32 |= 1 << LAS_BIT_BIGENDIAN; in tpci200_pci_probe() 558 iowrite32(reg32, tpci200->info->cfg_regs + LAS1_DESC); in tpci200_pci_probe() 560 reg32 = ioread32(tpci200->info->cfg_regs + LAS2_DESC); in tpci200_pci_probe() 561 reg32 |= 1 << LAS_BIT_BIGENDIAN; in tpci200_pci_probe() 562 iowrite32(reg32, tpci200->info->cfg_regs + LAS2_DESC); in tpci200_pci_probe()
|
/linux-6.12.1/drivers/gpu/drm/bridge/cadence/ |
D | cdns-mhdp8546-core.c | 879 u32 reg32; in cdns_mhdp_link_training_init() local 886 reg32 = CDNS_PHY_COMMON_CONFIG | CDNS_PHY_TRAINING_TYPE(1); in cdns_mhdp_link_training_init() 888 reg32 |= CDNS_PHY_SCRAMBLER_BYPASS; in cdns_mhdp_link_training_init() 890 cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG, reg32); in cdns_mhdp_link_training_init() 1050 u32 reg32; in cdns_mhdp_link_training_channel_eq() local 1057 reg32 = CDNS_PHY_COMMON_CONFIG | CDNS_PHY_TRAINING_EN | in cdns_mhdp_link_training_channel_eq() 1060 reg32 |= CDNS_PHY_SCRAMBLER_BYPASS; in cdns_mhdp_link_training_channel_eq() 1061 cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG, reg32); in cdns_mhdp_link_training_channel_eq() 1267 u32 reg32; in cdns_mhdp_link_training() local 1325 ret = cdns_mhdp_reg_read(mhdp, CDNS_DP_FRAMER_GLOBAL_CONFIG, ®32); in cdns_mhdp_link_training() [all …]
|
/linux-6.12.1/drivers/gpu/drm/i915/gt/ |
D | intel_rps.h | 63 bool rps_read_mask_mmio(struct intel_rps *rps, i915_reg_t reg32, u32 mask);
|
D | intel_gt_sysfs_pm.c | 471 i915_reg_t (*reg32)(struct intel_gt *gt); member 482 bool val = rps_read_mask_mmio(>->rps, t_attr->reg32(gt), t_attr->mask); in throttle_reason_bool_show() 491 .reg32 = intel_gt_perf_limit_reasons_reg, \
|
D | intel_rps.c | 2693 static u32 rps_read_mmio(struct intel_rps *rps, i915_reg_t reg32) in rps_read_mmio() argument 2700 val = intel_uncore_read(gt->uncore, reg32); in rps_read_mmio() 2706 i915_reg_t reg32, u32 mask) in rps_read_mask_mmio() argument 2708 return rps_read_mmio(rps, reg32) & mask; in rps_read_mask_mmio()
|
/linux-6.12.1/kernel/debug/kdb/ |
D | kdb_main.c | 1877 u32 reg32; in kdb_rd() local 1908 rname = dbg_get_reg(i, ®32, kdb_current_regs); in kdb_rd() 1911 len += kdb_printf("%s: %08x", rname, reg32); in kdb_rd() 1946 u32 reg32; in kdb_rm() local 1985 reg32 = reg64; in kdb_rm() 1986 dbg_set_reg(i, ®32, kdb_current_regs); in kdb_rm()
|
/linux-6.12.1/drivers/net/ethernet/freescale/fman/ |
D | fman_memac.c | 905 u32 reg32 = 0; in memac_init() local 939 reg32 = ioread32be(&memac->regs->command_config); in memac_init() 940 reg32 &= ~CMD_CFG_CRC_FWD; in memac_init() 941 iowrite32be(reg32, &memac->regs->command_config); in memac_init()
|
/linux-6.12.1/Documentation/translations/zh_TW/filesystems/ |
D | debugfs.rst | 165 “base”參數可能爲0,但您可能需要使用__stringify構建reg32數組,實際上有許多寄存器
|
/linux-6.12.1/Documentation/translations/zh_CN/filesystems/ |
D | debugfs.rst | 164 “base”参数可能为0,但您可能需要使用__stringify构建reg32数组,实际上有许多寄存器
|
/linux-6.12.1/drivers/net/wireless/realtek/rtl818x/rtl8180/ |
D | dev.c | 820 u32 reg32; in rtl8180_init_hw() local 971 reg32 = rtl818x_ioread32(priv, &priv->map->RF_PARA); in rtl8180_init_hw() 972 reg32 &= 0x00ffff00; in rtl8180_init_hw() 973 reg32 |= 0xb8000054; in rtl8180_init_hw() 974 rtl818x_iowrite32(priv, &priv->map->RF_PARA, reg32); in rtl8180_init_hw()
|
/linux-6.12.1/tools/lib/bpf/ |
D | usdt.c | 1244 #define reg_off(reg64, reg32) offsetof(struct pt_regs, reg64) in calc_pt_regs_off() argument 1246 #define reg_off(reg64, reg32) offsetof(struct pt_regs, reg32) in calc_pt_regs_off()
|
/linux-6.12.1/drivers/net/wireless/realtek/rtl818x/rtl8187/ |
D | dev.c | 1539 u32 reg32; in rtl8187_probe() local 1540 reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF); in rtl8187_probe() 1541 reg32 &= RTL818X_TX_CONF_HWVER_MASK; in rtl8187_probe() 1542 switch (reg32) { in rtl8187_probe()
|