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/linux-6.12.1/arch/nios2/include/asm/
Dasm-macros.h19 .macro ANDI32 reg1, reg2, mask
22 movhi \reg1, %hi(\mask)
23 movui \reg1, %lo(\mask)
24 and \reg1, \reg1, \reg2
26 andi \reg1, \reg2, %lo(\mask)
29 andhi \reg1, \reg2, %hi(\mask)
39 .macro ORI32 reg1, reg2, mask
42 orhi \reg1, \reg2, %hi(\mask)
43 ori \reg1, \reg2, %lo(\mask)
45 ori \reg1, \reg2, %lo(\mask)
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/linux-6.12.1/arch/arm64/include/asm/
Dkvm_ptrauth.h26 .macro ptrauth_save_state base, reg1, reg2
27 mrs_s \reg1, SYS_APIAKEYLO_EL1
29 stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APIAKEYLO_EL1)]
30 mrs_s \reg1, SYS_APIBKEYLO_EL1
32 stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APIBKEYLO_EL1)]
33 mrs_s \reg1, SYS_APDAKEYLO_EL1
35 stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APDAKEYLO_EL1)]
36 mrs_s \reg1, SYS_APDBKEYLO_EL1
38 stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APDBKEYLO_EL1)]
39 mrs_s \reg1, SYS_APGAKEYLO_EL1
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Dkvm_mte.h14 .macro mte_switch_to_guest g_ctxt, h_ctxt, reg1
18 mrs \reg1, hcr_el2
19 tbz \reg1, #(HCR_ATA_SHIFT), .L__skip_switch\@
21 mrs_s \reg1, SYS_RGSR_EL1
22 str \reg1, [\h_ctxt, #CPU_RGSR_EL1]
23 mrs_s \reg1, SYS_GCR_EL1
24 str \reg1, [\h_ctxt, #CPU_GCR_EL1]
26 ldr \reg1, [\g_ctxt, #CPU_RGSR_EL1]
27 msr_s SYS_RGSR_EL1, \reg1
28 ldr \reg1, [\g_ctxt, #CPU_GCR_EL1]
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/linux-6.12.1/arch/s390/include/asm/
Dap.h74 unsigned long reg1 = 0; in ap_instructions_available() local
84 : [reg1] "+&d" (reg1) in ap_instructions_available()
87 return reg1 != 0; in ap_instructions_available()
138 union ap_queue_status_reg reg1; in ap_tapq() local
147 : [reg1] "=&d" (reg1.value), [reg2] "=&d" (reg2) in ap_tapq()
152 return reg1.status; in ap_tapq()
181 union ap_queue_status_reg reg1; in ap_rapq() local
190 : [reg1] "=&d" (reg1.value) in ap_rapq()
193 return reg1.status; in ap_rapq()
206 union ap_queue_status_reg reg1; in ap_zapq() local
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/linux-6.12.1/arch/arm/probes/kprobes/
Dtest-core.h239 #define TEST_RR(code1, reg1, val1, code2, reg2, val2, code3) \ argument
240 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
241 TEST_ARG_REG(reg1, val1) \
244 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \
247 #define TEST_RRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\ argument
248 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
249 TEST_ARG_REG(reg1, val1) \
253 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
256 #define TEST_RRRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4, reg4, val4) \ argument
257 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4 #reg4) \
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/linux-6.12.1/arch/x86/events/intel/
Duncore_nhmex.c354 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; in nhmex_bbox_hw_config() local
369 reg1->reg = NHMEX_B0_MSR_MATCH; in nhmex_bbox_hw_config()
371 reg1->reg = NHMEX_B1_MSR_MATCH; in nhmex_bbox_hw_config()
372 reg1->idx = 0; in nhmex_bbox_hw_config()
373 reg1->config = event->attr.config1; in nhmex_bbox_hw_config()
381 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; in nhmex_bbox_msr_enable_event() local
384 if (reg1->idx != EXTRA_REG_NONE) { in nhmex_bbox_msr_enable_event()
385 wrmsrl(reg1->reg, reg1->config); in nhmex_bbox_msr_enable_event()
386 wrmsrl(reg1->reg + 1, reg2->config); in nhmex_bbox_msr_enable_event()
445 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; in nhmex_sbox_hw_config() local
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/linux-6.12.1/arch/arm/kernel/
Dhyp-stub.S31 .macro store_primary_cpu_mode reg1, reg2
32 mrs \reg1, cpsr
33 and \reg1, \reg1, #MODE_MASK
34 str_l \reg1, __boot_cpu_mode, \reg2
43 .macro compare_cpu_mode_with_primary mode, reg1, reg2
45 ldr \reg1, [\reg2]
46 cmp \mode, \reg1 @ matches primary CPU boot mode?
47 orrne \reg1, \reg1, #BOOT_CPU_MODE_MISMATCH
48 strne \reg1, [\reg2] @ record what happened and give up
53 .macro store_primary_cpu_mode reg1:req, reg2:req
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/linux-6.12.1/arch/arm/lib/
Dcsumpartialcopy.S25 .macro load1b, reg1 argument
26 ldrb \reg1, [r0], #1
29 .macro load2b, reg1, reg2
30 ldrb \reg1, [r0], #1
34 .macro load1l, reg1 argument
35 ldr \reg1, [r0], #4
38 .macro load2l, reg1, reg2
39 ldr \reg1, [r0], #4
43 .macro load4l, reg1, reg2, reg3, reg4
44 ldmia r0!, {\reg1, \reg2, \reg3, \reg4}
Dcsumpartialcopyuser.S56 .macro load1b, reg1 argument
57 ldrusr \reg1, r0, 1
60 .macro load2b, reg1, reg2
61 ldrusr \reg1, r0, 1
65 .macro load1l, reg1 argument
66 ldrusr \reg1, r0, 4
69 .macro load2l, reg1, reg2
70 ldrusr \reg1, r0, 4
74 .macro load4l, reg1, reg2, reg3, reg4
75 ldrusr \reg1, r0, 4
Dcopy_from_user.S46 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
47 ldr1w \ptr, \reg1, \abort
53 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
54 ldr4w \ptr, \reg1, \reg2, \reg3, \reg4, \abort
66 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
67 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4})
70 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
71 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
86 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
87 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
Dcopy_to_user.S40 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
41 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
44 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
45 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
64 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
65 str1w \ptr, \reg1, \abort
83 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
84 USERL(\abort, stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
Dmemcpy.S21 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
22 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
25 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
26 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
37 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
38 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
/linux-6.12.1/crypto/
Daria_generic.c32 u32 reg0, reg1, reg2, reg3; in aria_set_encrypt_key() local
44 reg1 = w0[1] ^ ck[1]; in aria_set_encrypt_key()
48 aria_subst_diff_odd(&reg0, &reg1, &reg2, &reg3); in aria_set_encrypt_key()
68 w1[1] ^= reg1; in aria_set_encrypt_key()
73 reg1 = w1[1]; in aria_set_encrypt_key()
78 reg1 ^= ck[5]; in aria_set_encrypt_key()
82 aria_subst_diff_even(&reg0, &reg1, &reg2, &reg3); in aria_set_encrypt_key()
85 reg1 ^= w0[1]; in aria_set_encrypt_key()
90 w2[1] = reg1; in aria_set_encrypt_key()
95 reg1 ^= ck[9]; in aria_set_encrypt_key()
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/linux-6.12.1/tools/perf/arch/x86/annotate/
Dinstructions.c266 if (!has_reg_type(state, dst->reg1)) in update_insn_state_x86()
269 tsr = &state->regs[dst->reg1]; in update_insn_state_x86()
274 else if (has_reg_type(state, src->reg1) && in update_insn_state_x86()
275 state->regs[src->reg1].kind == TSR_KIND_CONST) in update_insn_state_x86()
276 imm_value = state->regs[src->reg1].imm_value; in update_insn_state_x86()
277 else if (src->reg1 == DWARF_REG_PC) { in update_insn_state_x86()
307 insn_offset, imm_value, dst->reg1); in update_insn_state_x86()
326 if (!has_reg_type(state, dst->reg1)) in update_insn_state_x86()
329 tsr = &state->regs[dst->reg1]; in update_insn_state_x86()
350 insn_offset, dst->reg1); in update_insn_state_x86()
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/linux-6.12.1/sound/pci/ice1712/
Dwm8776.c133 .reg1 = WM8776_REG_DACLVOL,
143 .reg1 = WM8776_REG_DACCTRL1,
152 .reg1 = WM8776_REG_DACCTRL1,
159 .reg1 = WM8776_REG_HPLVOL,
170 .reg1 = WM8776_REG_PWRDOWN,
177 .reg1 = WM8776_REG_HPLVOL,
186 .reg1 = WM8776_REG_OUTMUX,
192 .reg1 = WM8776_REG_OUTMUX,
198 .reg1 = WM8776_REG_DACCTRL1,
204 .reg1 = WM8776_REG_PHASESWAP,
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Dwm8766.c34 .reg1 = WM8766_REG_DACL1,
45 .reg1 = WM8766_REG_DACL2,
56 .reg1 = WM8766_REG_DACL3,
66 .reg1 = WM8766_REG_DACCTRL2,
73 .reg1 = WM8766_REG_DACCTRL2,
80 .reg1 = WM8766_REG_DACCTRL2,
87 .reg1 = WM8766_REG_IFCTRL,
93 .reg1 = WM8766_REG_IFCTRL,
99 .reg1 = WM8766_REG_IFCTRL,
105 .reg1 = WM8766_REG_DACCTRL2,
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/linux-6.12.1/arch/arm64/crypto/
Daes-cipher-core.S20 .macro __pair1, sz, op, reg0, reg1, in0, in1e, in1d, shift
23 ubfiz \reg1, \in1e, #2, #8
26 ubfx \reg1, \in1e, #\shift, #8
38 ldr \reg1, [tt, \reg1, uxtw #2]
42 lsl \reg1, \reg1, #2
45 ldrb \reg1, [tt, \reg1, uxtw]
49 .macro __pair0, sz, op, reg0, reg1, in0, in1e, in1d, shift
51 ubfx \reg1, \in1d, #\shift, #8
53 ldr\op \reg1, [tt, \reg1, uxtw #\sz]
/linux-6.12.1/drivers/rtc/
Drtc-aspeed.c26 u32 reg1, reg2; in aspeed_rtc_read_time() local
35 reg1 = readl(rtc->base + RTC_TIME); in aspeed_rtc_read_time()
38 tm->tm_mday = (reg1 >> 24) & 0x1f; in aspeed_rtc_read_time()
39 tm->tm_hour = (reg1 >> 16) & 0x1f; in aspeed_rtc_read_time()
40 tm->tm_min = (reg1 >> 8) & 0x3f; in aspeed_rtc_read_time()
41 tm->tm_sec = (reg1 >> 0) & 0x3f; in aspeed_rtc_read_time()
56 u32 reg1, reg2, ctrl; in aspeed_rtc_set_time() local
62 reg1 = (tm->tm_mday << 24) | (tm->tm_hour << 16) | (tm->tm_min << 8) | in aspeed_rtc_set_time()
71 writel(reg1, rtc->base + RTC_TIME); in aspeed_rtc_set_time()
/linux-6.12.1/drivers/media/dvb-frontends/
Da8293.c29 u8 reg0, reg1; in a8293_set_voltage_slew() local
125 reg1 = 0x82; in a8293_set_voltage_slew()
126 if (reg1 != dev->reg[1]) { in a8293_set_voltage_slew()
127 ret = i2c_master_send(client, &reg1, 1); in a8293_set_voltage_slew()
130 dev->reg[1] = reg1; in a8293_set_voltage_slew()
148 u8 reg0, reg1; in a8293_set_voltage_noslew() local
178 reg1 = 0x82; in a8293_set_voltage_noslew()
179 if (reg1 != dev->reg[1]) { in a8293_set_voltage_noslew()
180 ret = i2c_master_send(client, &reg1, 1); in a8293_set_voltage_noslew()
183 dev->reg[1] = reg1; in a8293_set_voltage_noslew()
Dtua6100.c64 u8 reg1[] = { 0x01, 0x00, 0x00, 0x00 }; in tua6100_set_params() local
67 struct i2c_msg msg1 = { .addr = priv->i2c_address, .flags = 0, .buf = reg1, .len = 4 }; in tua6100_set_params()
82 reg1[1] = 0x2c; in tua6100_set_params()
84 reg1[1] = 0x0c; in tua6100_set_params()
87 reg1[1] |= 0x40; in tua6100_set_params()
89 reg1[1] |= 0x80; in tua6100_set_params()
107 reg1[1] |= (div >> 9) & 0x03; in tua6100_set_params()
108 reg1[2] = div >> 1; in tua6100_set_params()
109 reg1[3] = (div << 7); in tua6100_set_params()
113 reg1[3] |= (prediv - (div*_P_VAL)) & 0x7f; in tua6100_set_params()
/linux-6.12.1/tools/perf/arch/powerpc/annotate/
Dinstructions.c278 int src_reg = src->reg1; in update_insn_state_powerpc()
280 src->reg1 = dst->reg1; in update_insn_state_powerpc()
281 dst->reg1 = src_reg; in update_insn_state_powerpc()
284 if (!has_reg_type(state, dst->reg1)) in update_insn_state_powerpc()
287 tsr = &state->regs[dst->reg1]; in update_insn_state_powerpc()
289 if (!has_reg_type(state, src->reg1) || in update_insn_state_powerpc()
290 !state->regs[src->reg1].ok) { in update_insn_state_powerpc()
295 tsr->type = state->regs[src->reg1].type; in update_insn_state_powerpc()
296 tsr->kind = state->regs[src->reg1].kind; in update_insn_state_powerpc()
300 insn_offset, src->reg1, dst->reg1); in update_insn_state_powerpc()
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_pmdemand.c381 u32 reg1, reg2; in intel_pmdemand_init_pmdemand_params() local
394 reg1 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0)); in intel_pmdemand_init_pmdemand_params()
400 REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
402 REG_FIELD_GET(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
404 REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
406 REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
408 REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
410 REG_FIELD_GET(XELPDP_PMDEMAND_PHYS_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
465 u32 *reg1, u32 *reg2, bool serialized) in intel_pmdemand_update_params() argument
495 update_reg(reg1, qclk_gv_bw, XELPDP_PMDEMAND_QCLK_GV_BW_MASK); in intel_pmdemand_update_params()
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/linux-6.12.1/arch/s390/kvm/
Dpriv.c260 int reg1, reg2; in handle_iske() local
273 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2); in handle_iske()
299 vcpu->run->s.regs.gprs[reg1] &= ~0xff; in handle_iske()
300 vcpu->run->s.regs.gprs[reg1] |= key; in handle_iske()
307 int reg1, reg2; in handle_rrbe() local
320 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2); in handle_rrbe()
358 int reg1, reg2; in handle_sske() local
378 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2); in handle_sske()
380 key = vcpu->run->s.regs.gprs[reg1] & 0xfe; in handle_sske()
424 vcpu->run->s.regs.gprs[reg1] &= ~0xff00UL; in handle_sske()
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/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dnv04.c49 nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv) in nv04_clk_pll_prog() argument
57 if (reg1 > 0x405c) in nv04_clk_pll_prog()
58 setPLL_double_highregs(devinit, reg1, pv); in nv04_clk_pll_prog()
60 setPLL_double_lowregs(devinit, reg1, pv); in nv04_clk_pll_prog()
62 setPLL_single(devinit, reg1, pv); in nv04_clk_pll_prog()
/linux-6.12.1/arch/parisc/net/
Dbpf_jit.h103 #define hppa_or(reg1, reg2, target) \ argument
104 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x09, target) /* or reg1,reg2,target */
105 #define hppa_or_cond(reg1, reg2, cond, f, target) \ argument
106 hppa_t6_insn(0x02, reg2, reg1, cond, f, 0x09, target)
107 #define hppa_and(reg1, reg2, target) \ argument
108 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x08, target) /* and reg1,reg2,target */
109 #define hppa_and_cond(reg1, reg2, cond, f, target) \ argument
110 hppa_t6_insn(0x02, reg2, reg1, cond, f, 0x08, target)
111 #define hppa_xor(reg1, reg2, target) \ argument
112 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x0a, target) /* xor reg1,reg2,target */
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