Searched refs:refclk_hz (Results 1 – 7 of 7) sorted by relevance
552 u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd; in tc358743_set_pll()593 BUG_ON(!(pdata->refclk_hz == 26000000 || in tc358743_set_ref_clk()594 pdata->refclk_hz == 27000000 || in tc358743_set_ref_clk()595 pdata->refclk_hz == 42000000)); in tc358743_set_ref_clk()597 sys_freq = pdata->refclk_hz / 10000; in tc358743_set_ref_clk()602 (pdata->refclk_hz == 42000000) ? in tc358743_set_ref_clk()605 fh_min = pdata->refclk_hz / 100000; in tc358743_set_ref_clk()613 lockdet_ref = pdata->refclk_hz / 100; in tc358743_set_ref_clk()619 (pdata->refclk_hz == 27000000) ? in tc358743_set_ref_clk()674 u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd; in tc358743_num_csi_lanes_needed()[all …]
43 .refclk_hz = 26000000,68 .refclk_hz = 26000000,94 .refclk_hz = 26000000,114 .refclk_hz = 40000000,133 .refclk_hz = 40000000,152 .refclk_hz = 0,663 if (ar->hw.refclk_hz != 0) { in ath6kl_configure_target()665 ar->hw.refclk_hz); in ath6kl_configure_target()1606 ar->hw.refclk_hz, ar->hw.uarttx_pin); in ath6kl_init_hw_params()
781 u32 refclk_hz; member
33 u32 refclk_hz; /* 26 MHz, 27 MHz or 42 MHz */ member
64 uint64_t refclk_hz; member
1093 dto_params.refclk_hz = dtbclk_p_src_clk_khz; in dcn401_program_pix_clk()1094 dto_params.refclk_hz *= e->div_factor; in dcn401_program_pix_clk()1098 dto_params.refclk_hz = dtbclk_p_src_clk_khz; in dcn401_program_pix_clk()1099 dto_params.refclk_hz *= 1000; in dcn401_program_pix_clk()
606 if (!params->refclk_hz) { in dccg401_set_dp_dto()614 uint64_t dto_modulo_hz = params->refclk_hz; in dccg401_set_dp_dto()