| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn32/ |
| D | dcn32_dccg.c | 212 if (params->ref_dtbclk_khz && req_dtbclk_khz) { in dccg32_set_dtbclk_dto()
216 modulo = params->ref_dtbclk_khz * 1000; in dccg32_set_dtbclk_dto()
249 int ref_dtbclk_khz, in dccg32_set_valid_pixel_rate() argument
255 dto_params.ref_dtbclk_khz = ref_dtbclk_khz; in dccg32_set_valid_pixel_rate()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| D | dcn31_dccg.c | 572 if (params->ref_dtbclk_khz && req_dtbclk_khz) { in dccg31_set_dtbclk_dto()
576 modulo = params->ref_dtbclk_khz * 1000; in dccg31_set_dtbclk_dto()
577 phase = div_u64((((unsigned long long)modulo * req_dtbclk_khz) + params->ref_dtbclk_khz - 1), in dccg31_set_dtbclk_dto()
578 params->ref_dtbclk_khz); in dccg31_set_dtbclk_dto()
616 if (params->ref_dtbclk_khz && params->req_audio_dtbclk_khz) { in dccg31_set_audio_dtbclk_dto()
620 modulo = params->ref_dtbclk_khz * 1000; in dccg31_set_audio_dtbclk_dto()
621 …div_u64((((unsigned long long)modulo * params->req_audio_dtbclk_khz) + params->ref_dtbclk_khz - 1), in dccg31_set_audio_dtbclk_dto()
622 params->ref_dtbclk_khz); in dccg31_set_audio_dtbclk_dto()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| D | dcn314_dccg.c | 213 if (params->ref_dtbclk_khz && req_dtbclk_khz) { in dccg314_set_dtbclk_dto()
217 modulo = params->ref_dtbclk_khz * 1000; in dccg314_set_dtbclk_dto()
316 int ref_dtbclk_khz, in dccg314_set_valid_pixel_rate() argument
322 dto_params.ref_dtbclk_khz = ref_dtbclk_khz; in dccg314_set_valid_pixel_rate()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| D | dcn35_clk_mgr.c | 168 int ref_dtbclk_khz) in dcn35_update_clocks_update_dtb_dto() argument
184 dto_params.ref_dtbclk_khz = ref_dtbclk_khz; in dcn35_update_clocks_update_dtb_dto()
305 if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz) in dcn35_update_clocks()
306 new_clocks->ref_dtbclk_khz = 600000; in dcn35_update_clocks()
343 dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz); in dcn35_update_clocks()
344 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz; in dcn35_update_clocks()
397 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, in dcn35_update_clocks()
398 clk_mgr_base->clks.ref_dtbclk_khz / 1000)) { in dcn35_update_clocks()
399 dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz); in dcn35_update_clocks()
400 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz; in dcn35_update_clocks()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| D | dcn32_clk_mgr.c | 268 int ref_dtbclk_khz) in dcn32_update_clocks_update_dtb_dto() argument
284 dto_params.ref_dtbclk_khz = ref_dtbclk_khz; in dcn32_update_clocks_update_dtb_dto()
798 new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn32_update_clocks()
803 …should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_k… in dcn32_update_clocks()
805 clk_mgr_base->clks.ref_dtbclk_khz = in dcn32_update_clocks()
806 …dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz)); in dcn32_update_clocks()
808 dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz); in dcn32_update_clocks()
1183 clk_mgr->base.clks.ref_dtbclk_khz = 477800; in dcn32_clk_mgr_construct()
1185 clk_mgr->base.clks.ref_dtbclk_khz = 268750; in dcn32_clk_mgr_construct()
1199 clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) { in dcn32_clk_mgr_construct()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| D | dcn401_clk_mgr.c | 500 int ref_dtbclk_khz) in dcn401_update_clocks_update_dtb_dto() argument
772 new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn401_update_clocks_legacy()
777 …should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_k… in dcn401_update_clocks_legacy()
780 clk_mgr_base->clks.ref_dtbclk_khz = in dcn401_update_clocks_legacy()
781 …cn401_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz)); in dcn401_update_clocks_legacy()
783 dcn401_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz); in dcn401_update_clocks_legacy()
913 *params->update_dtbclk_dto_params.ref_dtbclk_khz); in dcn401_execute_block_sequence()
1257 new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn401_build_update_display_clocks_sequence()
1262 …should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_k… in dcn401_build_update_display_clocks_sequence()
1266 …nce[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz); in dcn401_build_update_display_clocks_sequence()
[all …]
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| D | dcn401_clk_mgr.h | 63 int *ref_dtbclk_khz; member
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | dccg.h | 91 int ref_dtbclk_khz; member
186 int ref_dtbclk_khz,
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| D | dcn31_clk_mgr.c | 298 uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz; in dcn31_init_clocks()
302 clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk in dcn31_init_clocks()
657 return clk_mgr_base->clks.ref_dtbclk_khz; in dcn31_get_dtb_ref_freq_khz()
737 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000; in dcn31_clk_mgr_construct()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn35/ |
| D | dcn35_dccg.c | 1358 if (params->ref_dtbclk_khz && req_dtbclk_khz) { in dccg35_set_dtbclk_dto()
1377 modulo = params->ref_dtbclk_khz * 1000; in dccg35_set_dtbclk_dto()
1618 int ref_dtbclk_khz, in dccg35_set_valid_pixel_rate() argument
1624 dto_params.ref_dtbclk_khz = ref_dtbclk_khz; in dccg35_set_valid_pixel_rate()
2265 if (params->ref_dtbclk_khz && req_dtbclk_khz) { in dccg35_set_dtbclk_dto_cb()
2271 modulo = params->ref_dtbclk_khz * 1000; in dccg35_set_dtbclk_dto_cb()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/ |
| D | dml2_wrapper.h | 65 unsigned int ref_dtbclk_khz; member
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| D | dml2_utils.c | 190 context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = out_clks->ref_dtbclk_khz; in dml2_copy_clocks_to_dc_state()
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| D | dml2_wrapper.c | 584 …out_clks.ref_dtbclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx… in dml2_validate_and_build_resource()
642 …out_clks.ref_dtbclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx… in dml2_validate_and_build_resource()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| D | dcn314_clk_mgr.c | 187 uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz; in dcn314_init_clocks()
191 clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk in dcn314_init_clocks()
848 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000; in dcn314_clk_mgr_construct()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| D | dcn315_clk_mgr.c | 665 clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz; in dcn315_clk_mgr_construct()
667 …clk_mgr->base.base.clks.ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->ba… in dcn315_clk_mgr_construct()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| D | dcn316_clk_mgr.c | 645 clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz; in dcn316_clk_mgr_construct()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/ |
| D | dc.h | 592 int ref_dtbclk_khz; member
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| D | dml21_translation_helper.c | 1038 …context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.d… in dml21_copy_clocks_to_dc_state()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| D | dcn20_hwseq.c | 890 dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); in dcn20_enable_stream_timing()
3000 dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); in dcn20_enable_stream()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| D | dcn32_hwseq.c | 753 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn32_initialize_min_clocks()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| D | dcn401_hwseq.c | 70 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn401_initialize_min_clocks()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| D | dcn32_fpu.c | 1672 context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000; in dcn32_calculate_dlg_params()
|