1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * TI clock drivers support
4 *
5 * Copyright (C) 2013 Texas Instruments, Inc.
6 */
7 #ifndef __LINUX_CLK_TI_H__
8 #define __LINUX_CLK_TI_H__
9
10 #include <linux/clk-provider.h>
11 #include <linux/clkdev.h>
12
13 /**
14 * struct clk_omap_reg - OMAP register declaration
15 * @offset: offset from the master IP module base address
16 * @bit: register bit offset
17 * @index: index of the master IP module
18 * @flags: flags
19 */
20 struct clk_omap_reg {
21 void __iomem *ptr;
22 u16 offset;
23 u8 bit;
24 u8 index;
25 u8 flags;
26 };
27
28 /**
29 * struct dpll_data - DPLL registers and integration data
30 * @mult_div1_reg: register containing the DPLL M and N bitfields
31 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
32 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
33 * @clk_bypass: struct clk_hw pointer to the clock's bypass clock input
34 * @clk_ref: struct clk_hw pointer to the clock's reference clock input
35 * @control_reg: register containing the DPLL mode bitfield
36 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
37 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
38 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
39 * @last_rounded_m4xen: cache of the last M4X result of
40 * omap4_dpll_regm4xen_round_rate()
41 * @last_rounded_lpmode: cache of the last lpmode result of
42 * omap4_dpll_lpmode_recalc()
43 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
44 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
45 * @min_divider: minimum valid non-bypass divider value (actual)
46 * @max_divider: maximum valid non-bypass divider value (actual)
47 * @max_rate: maximum clock rate for the DPLL
48 * @modes: possible values of @enable_mask
49 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
50 * @idlest_reg: register containing the DPLL idle status bitfield
51 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
52 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
53 * @dcc_mask: mask of the DPLL DCC correction bitfield @mult_div1_reg
54 * @dcc_rate: rate atleast which DCC @dcc_mask must be set
55 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
56 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
57 * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
58 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
59 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
60 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
61 * @ssc_deltam_reg: register containing the DPLL SSC frequency spreading
62 * @ssc_modfreq_reg: register containing the DPLL SSC modulation frequency
63 * @ssc_modfreq_mant_mask: mask of the mantissa component in @ssc_modfreq_reg
64 * @ssc_modfreq_exp_mask: mask of the exponent component in @ssc_modfreq_reg
65 * @ssc_enable_mask: mask of the DPLL SSC enable bit in @control_reg
66 * @ssc_downspread_mask: mask of the DPLL SSC low frequency only bit in
67 * @control_reg
68 * @ssc_modfreq: the DPLL SSC frequency modulation in kHz
69 * @ssc_deltam: the DPLL SSC frequency spreading in permille (10th of percent)
70 * @ssc_downspread: require the only low frequency spread of the DPLL in SSC
71 * mode
72 * @flags: DPLL type/features (see below)
73 *
74 * Possible values for @flags:
75 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
76 *
77 * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
78 *
79 * XXX Some DPLLs have multiple bypass inputs, so it's not technically
80 * correct to only have one @clk_bypass pointer.
81 *
82 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
83 * @last_rounded_n) should be separated from the runtime-fixed fields
84 * and placed into a different structure, so that the runtime-fixed data
85 * can be placed into read-only space.
86 */
87 struct dpll_data {
88 struct clk_omap_reg mult_div1_reg;
89 u32 mult_mask;
90 u32 div1_mask;
91 struct clk_hw *clk_bypass;
92 struct clk_hw *clk_ref;
93 struct clk_omap_reg control_reg;
94 u32 enable_mask;
95 unsigned long last_rounded_rate;
96 u16 last_rounded_m;
97 u8 last_rounded_m4xen;
98 u8 last_rounded_lpmode;
99 u16 max_multiplier;
100 u8 last_rounded_n;
101 u8 min_divider;
102 u16 max_divider;
103 unsigned long max_rate;
104 u8 modes;
105 struct clk_omap_reg autoidle_reg;
106 struct clk_omap_reg idlest_reg;
107 u32 autoidle_mask;
108 u32 freqsel_mask;
109 u32 idlest_mask;
110 u32 dco_mask;
111 u32 sddiv_mask;
112 u32 dcc_mask;
113 unsigned long dcc_rate;
114 u32 lpmode_mask;
115 u32 m4xen_mask;
116 u8 auto_recal_bit;
117 u8 recal_en_bit;
118 u8 recal_st_bit;
119 struct clk_omap_reg ssc_deltam_reg;
120 struct clk_omap_reg ssc_modfreq_reg;
121 u32 ssc_deltam_int_mask;
122 u32 ssc_deltam_frac_mask;
123 u32 ssc_modfreq_mant_mask;
124 u32 ssc_modfreq_exp_mask;
125 u32 ssc_enable_mask;
126 u32 ssc_downspread_mask;
127 u32 ssc_modfreq;
128 u32 ssc_deltam;
129 bool ssc_downspread;
130 u8 flags;
131 };
132
133 struct clk_hw_omap;
134
135 /**
136 * struct clk_hw_omap_ops - OMAP clk ops
137 * @find_idlest: find idlest register information for a clock
138 * @find_companion: find companion clock register information for a clock,
139 * basically converts CM_ICLKEN* <-> CM_FCLKEN*
140 * @allow_idle: enables autoidle hardware functionality for a clock
141 * @deny_idle: prevent autoidle hardware functionality for a clock
142 */
143 struct clk_hw_omap_ops {
144 void (*find_idlest)(struct clk_hw_omap *oclk,
145 struct clk_omap_reg *idlest_reg,
146 u8 *idlest_bit, u8 *idlest_val);
147 void (*find_companion)(struct clk_hw_omap *oclk,
148 struct clk_omap_reg *other_reg,
149 u8 *other_bit);
150 void (*allow_idle)(struct clk_hw_omap *oclk);
151 void (*deny_idle)(struct clk_hw_omap *oclk);
152 };
153
154 /**
155 * struct clk_hw_omap - OMAP struct clk
156 * @node: list_head connecting this clock into the full clock list
157 * @enable_reg: register to write to enable the clock (see @enable_bit)
158 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
159 * @flags: see "struct clk.flags possibilities" above
160 * @clksel_reg: for clksel clks, register va containing src/divisor select
161 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
162 * @clkdm_name: clockdomain name that this clock is contained in
163 * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
164 * @ops: clock ops for this clock
165 */
166 struct clk_hw_omap {
167 struct clk_hw hw;
168 struct list_head node;
169 unsigned long fixed_rate;
170 u8 fixed_div;
171 struct clk_omap_reg enable_reg;
172 u8 enable_bit;
173 unsigned long flags;
174 struct clk_omap_reg clksel_reg;
175 struct dpll_data *dpll_data;
176 const char *clkdm_name;
177 struct clockdomain *clkdm;
178 const struct clk_hw_omap_ops *ops;
179 u32 context;
180 int autoidle_count;
181 };
182
183 /*
184 * struct clk_hw_omap.flags possibilities
185 *
186 * XXX document the rest of the clock flags here
187 *
188 * ENABLE_REG_32BIT: (OMAP1 only) clock control register must be accessed
189 * with 32bit ops, by default OMAP1 uses 16bit ops.
190 * CLOCK_IDLE_CONTROL: (OMAP1 only) clock has autoidle support.
191 * CLOCK_NO_IDLE_PARENT: (OMAP1 only) when clock is enabled, its parent
192 * clock is put to no-idle mode.
193 * ENABLE_ON_INIT: Clock is enabled on init.
194 * INVERT_ENABLE: By default, clock enable bit behavior is '1' enable, '0'
195 * disable. This inverts the behavior making '0' enable and '1' disable.
196 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
197 * bits share the same register. This flag allows the
198 * omap4_dpllmx*() code to determine which GATE_CTRL bit field
199 * should be used. This is a temporary solution - a better approach
200 * would be to associate clock type-specific data with the clock,
201 * similar to the struct dpll_data approach.
202 */
203 #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
204 #define CLOCK_IDLE_CONTROL (1 << 1)
205 #define CLOCK_NO_IDLE_PARENT (1 << 2)
206 #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
207 #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
208 #define CLOCK_CLKOUTX2 (1 << 5)
209
210 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
211 #define DPLL_LOW_POWER_STOP 0x1
212 #define DPLL_LOW_POWER_BYPASS 0x5
213 #define DPLL_LOCKED 0x7
214
215 /* DPLL Type and DCO Selection Flags */
216 #define DPLL_J_TYPE 0x1
217
218 /* Static memmap indices */
219 enum {
220 TI_CLKM_CM = 0,
221 TI_CLKM_CM2,
222 TI_CLKM_PRM,
223 TI_CLKM_SCRM,
224 TI_CLKM_CTRL,
225 TI_CLKM_CTRL_AUX,
226 TI_CLKM_PLLSS,
227 CLK_MAX_MEMMAPS
228 };
229
230 /**
231 * struct ti_clk_ll_ops - low-level ops for clocks
232 * @clk_readl: pointer to register read function
233 * @clk_writel: pointer to register write function
234 * @clk_rmw: pointer to register read-modify-write function
235 * @clkdm_clk_enable: pointer to clockdomain enable function
236 * @clkdm_clk_disable: pointer to clockdomain disable function
237 * @clkdm_lookup: pointer to clockdomain lookup function
238 * @cm_wait_module_ready: pointer to CM module wait ready function
239 * @cm_split_idlest_reg: pointer to CM module function to split idlest reg
240 *
241 * Low-level ops are generally used by the basic clock types (clk-gate,
242 * clk-mux, clk-divider etc.) to provide support for various low-level
243 * hadrware interfaces (direct MMIO, regmap etc.), and is initialized
244 * by board code. Low-level ops also contain some other platform specific
245 * operations not provided directly by clock drivers.
246 */
247 struct ti_clk_ll_ops {
248 u32 (*clk_readl)(const struct clk_omap_reg *reg);
249 void (*clk_writel)(u32 val, const struct clk_omap_reg *reg);
250 void (*clk_rmw)(u32 val, u32 mask, const struct clk_omap_reg *reg);
251 int (*clkdm_clk_enable)(struct clockdomain *clkdm, struct clk *clk);
252 int (*clkdm_clk_disable)(struct clockdomain *clkdm,
253 struct clk *clk);
254 struct clockdomain * (*clkdm_lookup)(const char *name);
255 int (*cm_wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg,
256 u8 idlest_shift);
257 int (*cm_split_idlest_reg)(struct clk_omap_reg *idlest_reg,
258 s16 *prcm_inst, u8 *idlest_reg_id);
259 };
260
261 #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
262
263 bool omap2_clk_is_hw_omap(struct clk_hw *hw);
264 int omap2_clk_disable_autoidle_all(void);
265 int omap2_clk_enable_autoidle_all(void);
266 int omap2_clk_allow_idle(struct clk *clk);
267 int omap2_clk_deny_idle(struct clk *clk);
268 unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
269 unsigned long parent_rate);
270 int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
271 unsigned long parent_rate);
272 void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
273 void omap2xxx_clkt_vps_init(void);
274 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
275
276 void ti_dt_clk_init_retry_clks(void);
277 void ti_dt_clockdomains_setup(void);
278 int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops);
279
280 struct regmap;
281
282 int omap2_clk_provider_init(struct device_node *parent, int index,
283 struct regmap *syscon, void __iomem *mem);
284 void omap2_clk_legacy_provider_init(int index, void __iomem *mem);
285
286 int omap3430_dt_clk_init(void);
287 int omap3630_dt_clk_init(void);
288 int am35xx_dt_clk_init(void);
289 int dm814x_dt_clk_init(void);
290 int dm816x_dt_clk_init(void);
291 int omap4xxx_dt_clk_init(void);
292 int omap5xxx_dt_clk_init(void);
293 int dra7xx_dt_clk_init(void);
294 int am33xx_dt_clk_init(void);
295 int am43xx_dt_clk_init(void);
296 int omap2420_dt_clk_init(void);
297 int omap2430_dt_clk_init(void);
298
299 struct ti_clk_features {
300 u32 flags;
301 long fint_min;
302 long fint_max;
303 long fint_band1_max;
304 long fint_band2_min;
305 u8 dpll_bypass_vals;
306 u8 cm_idlest_val;
307 };
308
309 #define TI_CLK_DPLL_HAS_FREQSEL BIT(0)
310 #define TI_CLK_DPLL4_DENY_REPROGRAM BIT(1)
311 #define TI_CLK_DISABLE_CLKDM_CONTROL BIT(2)
312 #define TI_CLK_ERRATA_I810 BIT(3)
313 #define TI_CLK_CLKCTRL_COMPAT BIT(4)
314 #define TI_CLK_DEVICE_TYPE_GP BIT(5)
315
316 void ti_clk_setup_features(struct ti_clk_features *features);
317 const struct ti_clk_features *ti_clk_get_features(void);
318 bool ti_clk_is_in_standby(struct clk *clk);
319 int omap3_noncore_dpll_save_context(struct clk_hw *hw);
320 void omap3_noncore_dpll_restore_context(struct clk_hw *hw);
321
322 int omap3_core_dpll_save_context(struct clk_hw *hw);
323 void omap3_core_dpll_restore_context(struct clk_hw *hw);
324
325 extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
326
327 #ifdef CONFIG_ATAGS
328 int omap3430_clk_legacy_init(void);
329 int omap3430es1_clk_legacy_init(void);
330 int omap36xx_clk_legacy_init(void);
331 int am35xx_clk_legacy_init(void);
332 #else
omap3430_clk_legacy_init(void)333 static inline int omap3430_clk_legacy_init(void) { return -ENXIO; }
omap3430es1_clk_legacy_init(void)334 static inline int omap3430es1_clk_legacy_init(void) { return -ENXIO; }
omap36xx_clk_legacy_init(void)335 static inline int omap36xx_clk_legacy_init(void) { return -ENXIO; }
am35xx_clk_legacy_init(void)336 static inline int am35xx_clk_legacy_init(void) { return -ENXIO; }
337 #endif
338
339
340 #endif
341