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Searched refs:rb0_mask (Results 1 – 3 of 3) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c1405 unsigned rb0_mask = 1 << (se * rb_per_se); in gfx_v6_0_write_harvested_raster_configs() local
1406 unsigned rb1_mask = rb0_mask << 1; in gfx_v6_0_write_harvested_raster_configs()
1408 rb0_mask &= rb_mask; in gfx_v6_0_write_harvested_raster_configs()
1410 if (!rb0_mask || !rb1_mask) { in gfx_v6_0_write_harvested_raster_configs()
1413 if (!rb0_mask) in gfx_v6_0_write_harvested_raster_configs()
1422 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); in gfx_v6_0_write_harvested_raster_configs()
1423 rb1_mask = rb0_mask << 1; in gfx_v6_0_write_harvested_raster_configs()
1424 rb0_mask &= rb_mask; in gfx_v6_0_write_harvested_raster_configs()
1426 if (!rb0_mask || !rb1_mask) { in gfx_v6_0_write_harvested_raster_configs()
1429 if (!rb0_mask) in gfx_v6_0_write_harvested_raster_configs()
Dgfx_v7_0.c1694 unsigned rb0_mask = 1 << (se * rb_per_se); in gfx_v7_0_write_harvested_raster_configs() local
1695 unsigned rb1_mask = rb0_mask << 1; in gfx_v7_0_write_harvested_raster_configs()
1697 rb0_mask &= rb_mask; in gfx_v7_0_write_harvested_raster_configs()
1699 if (!rb0_mask || !rb1_mask) { in gfx_v7_0_write_harvested_raster_configs()
1702 if (!rb0_mask) { in gfx_v7_0_write_harvested_raster_configs()
1712 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); in gfx_v7_0_write_harvested_raster_configs()
1713 rb1_mask = rb0_mask << 1; in gfx_v7_0_write_harvested_raster_configs()
1714 rb0_mask &= rb_mask; in gfx_v7_0_write_harvested_raster_configs()
1716 if (!rb0_mask || !rb1_mask) { in gfx_v7_0_write_harvested_raster_configs()
1719 if (!rb0_mask) { in gfx_v7_0_write_harvested_raster_configs()
Dgfx_v8_0.c3542 unsigned rb0_mask = 1 << (se * rb_per_se); in gfx_v8_0_write_harvested_raster_configs() local
3543 unsigned rb1_mask = rb0_mask << 1; in gfx_v8_0_write_harvested_raster_configs()
3545 rb0_mask &= rb_mask; in gfx_v8_0_write_harvested_raster_configs()
3547 if (!rb0_mask || !rb1_mask) { in gfx_v8_0_write_harvested_raster_configs()
3550 if (!rb0_mask) { in gfx_v8_0_write_harvested_raster_configs()
3560 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); in gfx_v8_0_write_harvested_raster_configs()
3561 rb1_mask = rb0_mask << 1; in gfx_v8_0_write_harvested_raster_configs()
3562 rb0_mask &= rb_mask; in gfx_v8_0_write_harvested_raster_configs()
3564 if (!rb0_mask || !rb1_mask) { in gfx_v8_0_write_harvested_raster_configs()
3567 if (!rb0_mask) { in gfx_v8_0_write_harvested_raster_configs()