/linux-6.12.1/arch/sh/kernel/cpu/sh4a/ |
D | clock-sh7722.c | 30 static struct clk r_clk = { variable 61 .parent = &r_clk, 88 &r_clk, 145 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0), 146 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0), 153 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0), 156 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0), 171 CLKDEV_CON_ID("rclk", &r_clk),
|
D | clock-sh7723.c | 31 static struct clk r_clk = { variable 62 .parent = &r_clk, 89 &r_clk, 155 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0), 156 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0), 171 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0), 181 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0), 196 CLKDEV_CON_ID("rclk", &r_clk),
|
D | clock-sh7343.c | 27 static struct clk r_clk = { variable 58 .parent = &r_clk, 82 &r_clk, 151 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0), 152 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0), 171 [MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0), 187 CLKDEV_CON_ID("rclk", &r_clk),
|
D | clock-sh7724.c | 34 static struct clk r_clk = { variable 67 .parent = &r_clk, 116 &r_clk, 216 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0), 217 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0), 229 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 12, 0), 230 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 11, 0), 261 CLKDEV_CON_ID("rclk", &r_clk),
|
D | clock-sh7366.c | 27 static struct clk r_clk = { variable 58 .parent = &r_clk, 85 &r_clk, 154 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0), 155 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0), 185 CLKDEV_CON_ID("rclk", &r_clk),
|
/linux-6.12.1/arch/sh/kernel/cpu/sh2a/ |
D | clock-sh7264.c | 29 static struct clk r_clk = { variable 58 &r_clk, 101 [MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */ 106 CLKDEV_CON_ID("rclk", &r_clk),
|
D | clock-sh7269.c | 26 static struct clk r_clk = { variable 84 &r_clk, 135 [MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */ 140 CLKDEV_CON_ID("rclk", &r_clk),
|
/linux-6.12.1/drivers/iio/adc/ |
D | ad9467.c | 823 long r_clk; in ad9467_write_raw() local 830 r_clk = clk_round_rate(st->clk, val); in ad9467_write_raw() 831 if (r_clk < 0 || r_clk > info->max_rate) { in ad9467_write_raw() 833 "Error setting ADC sample rate %ld", r_clk); in ad9467_write_raw() 842 if (sample_rate == r_clk) in ad9467_write_raw() 846 ret = clk_set_rate(st->clk, r_clk); in ad9467_write_raw()
|