| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer_debug.c | 158 …(s->qos_level_low_wm * frac) / ref_clk_mhz / frac, (s->qos_level_low_wm * frac) / ref_clk_mhz % fr… in dcn10_get_hubp_states()
178 …(s->qos_level_low_wm * frac) / ref_clk_mhz / frac, (s->qos_level_low_wm * frac) / ref_clk_mhz % fr… in dcn10_get_hubp_states()
312 …pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_v… in dcn10_get_ttu_states()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn21/ |
| D | dcn21_hubp.c | 479 QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm, in hubp21_validate_dml_output()
482 if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm) in hubp21_validate_dml_output()
484 dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm); in hubp21_validate_dml_output()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn20/ |
| D | dcn20_hubp.c | 147 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, in hubp2_program_deadline()
1227 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, in hubp2_read_state_common()
1291 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, in hubp2_read_state_common()
1572 QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm, in hubp2_validate_dml_output()
1575 if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm) in hubp2_validate_dml_output()
1577 dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm); in hubp2_validate_dml_output()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| D | dml_top_dchub_registers.h | 62 uint32_t qos_level_low_wm; member
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn401/ |
| D | dcn401_hubp.c | 266 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, in hubp401_program_deadline()
872 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, in hubp401_read_state()
936 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, in hubp401_read_state()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/ |
| D | display_rq_dlg_helpers.c | 334 ttu_regs->qos_level_low_wm); in print__ttu_regs_st()
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| D | display_mode_structs.h | 676 unsigned int qos_level_low_wm; member
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| D | dml1_display_rq_dlg_calc.c | 1904 disp_ttu_regs->qos_level_low_wm = 0; in dml1_rq_dlg_get_dlg_params()
1905 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); in dml1_rq_dlg_get_dlg_params()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn10/ |
| D | dcn10_hubp.c | 652 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, in hubp1_program_deadline()
992 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, in hubp1_read_state_common()
1056 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, in hubp1_read_state_common()
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| D | dcn10_hubp.h | 687 uint32_t qos_level_low_wm; member
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| D | display_rq_dlg_calc_32.c | 541 ttu_regs->qos_level_low_wm = 0; in dml32_rq_dlg_get_dlg_reg()
607 ASSERT(ttu_regs->qos_level_low_wm < dml_pow(2, 14)); in dml32_rq_dlg_get_dlg_reg()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/ |
| D | dml_display_rq_dlg_calc.c | 502 disp_ttu_regs->qos_level_low_wm = 0; in dml_rq_dlg_get_dlg_reg()
567 ASSERT(disp_ttu_regs->qos_level_low_wm < (dml_uint_t) dml_pow(2, 14)); in dml_rq_dlg_get_dlg_reg()
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| D | dml2_translation_helper.c | 1483 out->ttu_regs.qos_level_low_wm = disp_ttu_regs->qos_level_low_wm; in dml2_update_pipe_ctx_dchub_regs()
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| D | display_mode_util.c | 304 dml_print("DML: qos_level_low_wm = 0x%x\n", ttu_regs->qos_level_low_wm); in dml_print_ttu_regs_st()
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| D | display_mode_core_structs.h | 1922 dml_uint_t qos_level_low_wm; member
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| D | dml21_utils.c | 227 out->ttu_regs.qos_level_low_wm = disp_ttu_regs->qos_level_low_wm; in dml21_update_pipe_ctx_dchub_regs()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_rq_dlg_calc_21.c | 1620 disp_ttu_regs->qos_level_low_wm = 0; in dml_rq_dlg_get_dlg_params()
1621 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); in dml_rq_dlg_get_dlg_params()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | display_rq_dlg_calc_20.c | 1512 disp_ttu_regs->qos_level_low_wm = 0; in dml20_rq_dlg_get_dlg_params()
1513 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); in dml20_rq_dlg_get_dlg_params()
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| D | display_rq_dlg_calc_20v2.c | 1513 disp_ttu_regs->qos_level_low_wm = 0; in dml20v2_rq_dlg_get_dlg_params()
1514 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); in dml20v2_rq_dlg_get_dlg_params()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | display_rq_dlg_calc_31.c | 1526 disp_ttu_regs->qos_level_low_wm = 0; in dml_rq_dlg_get_dlg_params()
1527 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); in dml_rq_dlg_get_dlg_params()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | display_rq_dlg_calc_30.c | 1708 disp_ttu_regs->qos_level_low_wm = 0; in dml_rq_dlg_get_dlg_params()
1709 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); in dml_rq_dlg_get_dlg_params()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| D | display_rq_dlg_calc_314.c | 1614 disp_ttu_regs->qos_level_low_wm = 0; in dml_rq_dlg_get_dlg_params()
1615 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); in dml_rq_dlg_get_dlg_params()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| D | dcn10_hwseq.c | 202 DTN_INFO_MICRO_SEC(s->qos_level_low_wm); in dcn10_log_hubp_states()
276 …pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_v… in dcn10_log_hubp_states()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| D | dml2_core_shared.c | 11863 disp_ttu_regs->qos_level_low_wm = 0; in rq_dlg_get_dlg_reg()
11921 DML2_ASSERT(disp_ttu_regs->qos_level_low_wm < (unsigned int)math_pow(2, 14)); in rq_dlg_get_dlg_reg()
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| D | dml2_core_dcn4_calcs.c | 12170 disp_ttu_regs->qos_level_low_wm = 0; in rq_dlg_get_dlg_reg()
12228 DML2_ASSERT(disp_ttu_regs->qos_level_low_wm < (unsigned int)math_pow(2, 14)); in rq_dlg_get_dlg_reg()
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