1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. 4 * 5 * Authors: Shlomi Gridish <gridish@freescale.com> 6 * Li Yang <leoli@freescale.com> 7 * 8 * Description: 9 * QUICC Engine (QE) external definitions and structure. 10 */ 11 #ifndef _ASM_POWERPC_QE_H 12 #define _ASM_POWERPC_QE_H 13 #ifdef __KERNEL__ 14 15 #include <linux/compiler.h> 16 #include <linux/genalloc.h> 17 #include <linux/spinlock.h> 18 #include <linux/errno.h> 19 #include <linux/err.h> 20 #include <soc/fsl/cpm.h> 21 #include <soc/fsl/qe/immap_qe.h> 22 #include <linux/of.h> 23 #include <linux/of_address.h> 24 #include <linux/types.h> 25 26 struct device; 27 28 #define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */ 29 #define QE_NUM_OF_BRGS 16 30 #define QE_NUM_OF_PORTS 1024 31 32 /* Clocks and BRGs */ 33 enum qe_clock { 34 QE_CLK_NONE = 0, 35 QE_BRG1, /* Baud Rate Generator 1 */ 36 QE_BRG2, /* Baud Rate Generator 2 */ 37 QE_BRG3, /* Baud Rate Generator 3 */ 38 QE_BRG4, /* Baud Rate Generator 4 */ 39 QE_BRG5, /* Baud Rate Generator 5 */ 40 QE_BRG6, /* Baud Rate Generator 6 */ 41 QE_BRG7, /* Baud Rate Generator 7 */ 42 QE_BRG8, /* Baud Rate Generator 8 */ 43 QE_BRG9, /* Baud Rate Generator 9 */ 44 QE_BRG10, /* Baud Rate Generator 10 */ 45 QE_BRG11, /* Baud Rate Generator 11 */ 46 QE_BRG12, /* Baud Rate Generator 12 */ 47 QE_BRG13, /* Baud Rate Generator 13 */ 48 QE_BRG14, /* Baud Rate Generator 14 */ 49 QE_BRG15, /* Baud Rate Generator 15 */ 50 QE_BRG16, /* Baud Rate Generator 16 */ 51 QE_CLK1, /* Clock 1 */ 52 QE_CLK2, /* Clock 2 */ 53 QE_CLK3, /* Clock 3 */ 54 QE_CLK4, /* Clock 4 */ 55 QE_CLK5, /* Clock 5 */ 56 QE_CLK6, /* Clock 6 */ 57 QE_CLK7, /* Clock 7 */ 58 QE_CLK8, /* Clock 8 */ 59 QE_CLK9, /* Clock 9 */ 60 QE_CLK10, /* Clock 10 */ 61 QE_CLK11, /* Clock 11 */ 62 QE_CLK12, /* Clock 12 */ 63 QE_CLK13, /* Clock 13 */ 64 QE_CLK14, /* Clock 14 */ 65 QE_CLK15, /* Clock 15 */ 66 QE_CLK16, /* Clock 16 */ 67 QE_CLK17, /* Clock 17 */ 68 QE_CLK18, /* Clock 18 */ 69 QE_CLK19, /* Clock 19 */ 70 QE_CLK20, /* Clock 20 */ 71 QE_CLK21, /* Clock 21 */ 72 QE_CLK22, /* Clock 22 */ 73 QE_CLK23, /* Clock 23 */ 74 QE_CLK24, /* Clock 24 */ 75 QE_RSYNC_PIN, /* RSYNC from pin */ 76 QE_TSYNC_PIN, /* TSYNC from pin */ 77 QE_CLK_DUMMY 78 }; 79 qe_clock_is_brg(enum qe_clock clk)80 static inline bool qe_clock_is_brg(enum qe_clock clk) 81 { 82 return clk >= QE_BRG1 && clk <= QE_BRG16; 83 } 84 85 extern spinlock_t cmxgcr_lock; 86 87 /* Export QE common operations */ 88 #ifdef CONFIG_QUICC_ENGINE 89 extern void qe_reset(void); 90 #else qe_reset(void)91 static inline void qe_reset(void) {} 92 #endif 93 94 int cpm_muram_init(void); 95 96 #if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) 97 s32 cpm_muram_alloc(unsigned long size, unsigned long align); 98 s32 devm_cpm_muram_alloc(struct device *dev, unsigned long size, 99 unsigned long align); 100 void cpm_muram_free(s32 offset); 101 s32 cpm_muram_alloc_fixed(unsigned long offset, unsigned long size); 102 s32 devm_cpm_muram_alloc_fixed(struct device *dev, unsigned long offset, 103 unsigned long size); 104 void __iomem *cpm_muram_addr(unsigned long offset); 105 unsigned long cpm_muram_offset(const void __iomem *addr); 106 dma_addr_t cpm_muram_dma(void __iomem *addr); 107 void cpm_muram_free_addr(const void __iomem *addr); 108 #else cpm_muram_alloc(unsigned long size,unsigned long align)109 static inline s32 cpm_muram_alloc(unsigned long size, 110 unsigned long align) 111 { 112 return -ENOSYS; 113 } 114 devm_cpm_muram_alloc(struct device * dev,unsigned long size,unsigned long align)115 static inline s32 devm_cpm_muram_alloc(struct device *dev, unsigned long size, 116 unsigned long align) 117 { 118 return -ENOSYS; 119 } 120 cpm_muram_free(s32 offset)121 static inline void cpm_muram_free(s32 offset) 122 { 123 } 124 cpm_muram_alloc_fixed(unsigned long offset,unsigned long size)125 static inline s32 cpm_muram_alloc_fixed(unsigned long offset, 126 unsigned long size) 127 { 128 return -ENOSYS; 129 } 130 devm_cpm_muram_alloc_fixed(struct device * dev,unsigned long offset,unsigned long size)131 static inline s32 devm_cpm_muram_alloc_fixed(struct device *dev, 132 unsigned long offset, 133 unsigned long size) 134 { 135 return -ENOSYS; 136 } 137 cpm_muram_addr(unsigned long offset)138 static inline void __iomem *cpm_muram_addr(unsigned long offset) 139 { 140 return NULL; 141 } 142 cpm_muram_offset(const void __iomem * addr)143 static inline unsigned long cpm_muram_offset(const void __iomem *addr) 144 { 145 return -ENOSYS; 146 } 147 cpm_muram_dma(void __iomem * addr)148 static inline dma_addr_t cpm_muram_dma(void __iomem *addr) 149 { 150 return 0; 151 } cpm_muram_free_addr(const void __iomem * addr)152 static inline void cpm_muram_free_addr(const void __iomem *addr) 153 { 154 } 155 #endif /* defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) */ 156 157 /* QE PIO */ 158 #define QE_PIO_PINS 32 159 160 struct qe_pio_regs { 161 __be32 cpodr; /* Open drain register */ 162 __be32 cpdata; /* Data register */ 163 __be32 cpdir1; /* Direction register */ 164 __be32 cpdir2; /* Direction register */ 165 __be32 cppar1; /* Pin assignment register */ 166 __be32 cppar2; /* Pin assignment register */ 167 #ifdef CONFIG_PPC_85xx 168 u8 pad[8]; 169 #endif 170 }; 171 172 #define QE_PIO_DIR_IN 2 173 #define QE_PIO_DIR_OUT 1 174 extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, 175 int dir, int open_drain, int assignment, 176 int has_irq); 177 #ifdef CONFIG_QUICC_ENGINE 178 extern int par_io_init(struct device_node *np); 179 extern int par_io_of_config(struct device_node *np); 180 extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, 181 int assignment, int has_irq); 182 extern int par_io_data_set(u8 port, u8 pin, u8 val); 183 #else par_io_init(struct device_node * np)184 static inline int par_io_init(struct device_node *np) { return -ENOSYS; } par_io_of_config(struct device_node * np)185 static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; } par_io_config_pin(u8 port,u8 pin,int dir,int open_drain,int assignment,int has_irq)186 static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, 187 int assignment, int has_irq) { return -ENOSYS; } par_io_data_set(u8 port,u8 pin,u8 val)188 static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; } 189 #endif /* CONFIG_QUICC_ENGINE */ 190 191 /* 192 * Pin multiplexing functions. 193 */ 194 struct qe_pin; 195 #ifdef CONFIG_QE_GPIO 196 extern struct qe_pin *qe_pin_request(struct device *dev, int index); 197 extern void qe_pin_free(struct qe_pin *qe_pin); 198 extern void qe_pin_set_gpio(struct qe_pin *qe_pin); 199 extern void qe_pin_set_dedicated(struct qe_pin *pin); 200 #else qe_pin_request(struct device * dev,int index)201 static inline struct qe_pin *qe_pin_request(struct device *dev, int index) 202 { 203 return ERR_PTR(-ENOSYS); 204 } qe_pin_free(struct qe_pin * qe_pin)205 static inline void qe_pin_free(struct qe_pin *qe_pin) {} qe_pin_set_gpio(struct qe_pin * qe_pin)206 static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {} qe_pin_set_dedicated(struct qe_pin * pin)207 static inline void qe_pin_set_dedicated(struct qe_pin *pin) {} 208 #endif /* CONFIG_QE_GPIO */ 209 210 #ifdef CONFIG_QUICC_ENGINE 211 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); 212 #else qe_issue_cmd(u32 cmd,u32 device,u8 mcn_protocol,u32 cmd_input)213 static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, 214 u32 cmd_input) 215 { 216 return -ENOSYS; 217 } 218 #endif /* CONFIG_QUICC_ENGINE */ 219 220 /* QE internal API */ 221 enum qe_clock qe_clock_source(const char *source); 222 unsigned int qe_get_brg_clk(void); 223 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier); 224 int qe_get_snum(void); 225 void qe_put_snum(u8 snum); 226 unsigned int qe_get_num_of_risc(void); 227 unsigned int qe_get_num_of_snums(void); 228 qe_alive_during_sleep(void)229 static inline int qe_alive_during_sleep(void) 230 { 231 /* 232 * MPC8568E reference manual says: 233 * 234 * "...power down sequence waits for all I/O interfaces to become idle. 235 * In some applications this may happen eventually without actively 236 * shutting down interfaces, but most likely, software will have to 237 * take steps to shut down the eTSEC, QUICC Engine Block, and PCI 238 * interfaces before issuing the command (either the write to the core 239 * MSR[WE] as described above or writing to POWMGTCSR) to put the 240 * device into sleep state." 241 * 242 * MPC8569E reference manual has a similar paragraph. 243 */ 244 #ifdef CONFIG_PPC_85xx 245 return 0; 246 #else 247 return 1; 248 #endif 249 } 250 251 /* we actually use cpm_muram implementation, define this for convenience */ 252 #define qe_muram_init cpm_muram_init 253 #define qe_muram_alloc cpm_muram_alloc 254 #define devm_qe_muram_alloc devm_cpm_muram_alloc 255 #define qe_muram_alloc_fixed cpm_muram_alloc_fixed 256 #define devm_qe_muram_alloc_fixed devm_cpm_muram_alloc_fixed 257 #define qe_muram_free cpm_muram_free 258 #define qe_muram_addr cpm_muram_addr 259 #define qe_muram_offset cpm_muram_offset 260 #define qe_muram_dma cpm_muram_dma 261 #define qe_muram_free_addr cpm_muram_free_addr 262 263 #define qe_setbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr)) 264 #define qe_clrbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr)) 265 266 #define qe_setbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr)) 267 #define qe_clrbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr)) 268 269 #define qe_setbits_8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr)) 270 #define qe_clrbits_8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr)) 271 272 #define qe_clrsetbits_be32(addr, clear, set) \ 273 iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr)) 274 #define qe_clrsetbits_be16(addr, clear, set) \ 275 iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr)) 276 #define qe_clrsetbits_8(addr, clear, set) \ 277 iowrite8((ioread8(addr) & ~(clear)) | (set), (addr)) 278 279 /* Structure that defines QE firmware binary files. 280 * 281 * See Documentation/arch/powerpc/qe_firmware.rst for a description of these 282 * fields. 283 */ 284 struct qe_firmware { 285 struct qe_header { 286 __be32 length; /* Length of the entire structure, in bytes */ 287 u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */ 288 u8 version; /* Version of this layout. First ver is '1' */ 289 } header; 290 u8 id[62]; /* Null-terminated identifier string */ 291 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */ 292 u8 count; /* Number of microcode[] structures */ 293 struct { 294 __be16 model; /* The SOC model */ 295 u8 major; /* The SOC revision major */ 296 u8 minor; /* The SOC revision minor */ 297 } __attribute__ ((packed)) soc; 298 u8 padding[4]; /* Reserved, for alignment */ 299 __be64 extended_modes; /* Extended modes */ 300 __be32 vtraps[8]; /* Virtual trap addresses */ 301 u8 reserved[4]; /* Reserved, for future expansion */ 302 struct qe_microcode { 303 u8 id[32]; /* Null-terminated identifier */ 304 __be32 traps[16]; /* Trap addresses, 0 == ignore */ 305 __be32 eccr; /* The value for the ECCR register */ 306 __be32 iram_offset; /* Offset into I-RAM for the code */ 307 __be32 count; /* Number of 32-bit words of the code */ 308 __be32 code_offset; /* Offset of the actual microcode */ 309 u8 major; /* The microcode version major */ 310 u8 minor; /* The microcode version minor */ 311 u8 revision; /* The microcode version revision */ 312 u8 padding; /* Reserved, for alignment */ 313 u8 reserved[4]; /* Reserved, for future expansion */ 314 } __packed microcode[]; 315 /* All microcode binaries should be located here */ 316 /* CRC32 should be located here, after the microcode binaries */ 317 } __attribute__ ((packed)); 318 319 struct qe_firmware_info { 320 char id[64]; /* Firmware name */ 321 u32 vtraps[8]; /* Virtual trap addresses */ 322 u64 extended_modes; /* Extended modes */ 323 }; 324 325 #ifdef CONFIG_QUICC_ENGINE 326 /* Upload a firmware to the QE */ 327 int qe_upload_firmware(const struct qe_firmware *firmware); 328 #else qe_upload_firmware(const struct qe_firmware * firmware)329 static inline int qe_upload_firmware(const struct qe_firmware *firmware) 330 { 331 return -ENOSYS; 332 } 333 #endif /* CONFIG_QUICC_ENGINE */ 334 335 /* Obtain information on the uploaded firmware */ 336 struct qe_firmware_info *qe_get_firmware_info(void); 337 338 /* QE USB */ 339 int qe_usb_clock_set(enum qe_clock clk, int rate); 340 341 /* Buffer descriptors */ 342 struct qe_bd { 343 __be16 status; 344 __be16 length; 345 __be32 buf; 346 } __attribute__ ((packed)); 347 348 #define BD_STATUS_MASK 0xffff0000 349 #define BD_LENGTH_MASK 0x0000ffff 350 351 /* Alignment */ 352 #define QE_INTR_TABLE_ALIGN 16 /* ??? */ 353 #define QE_ALIGNMENT_OF_BD 8 354 #define QE_ALIGNMENT_OF_PRAM 64 355 356 /* RISC allocation */ 357 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */ 358 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */ 359 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */ 360 #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */ 361 #define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \ 362 QE_RISC_ALLOCATION_RISC2) 363 #define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \ 364 QE_RISC_ALLOCATION_RISC2 | \ 365 QE_RISC_ALLOCATION_RISC3 | \ 366 QE_RISC_ALLOCATION_RISC4) 367 368 /* QE extended filtering Table Lookup Key Size */ 369 enum qe_fltr_tbl_lookup_key_size { 370 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES 371 = 0x3f, /* LookupKey parsed by the Generate LookupKey 372 CMD is truncated to 8 bytes */ 373 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES 374 = 0x5f, /* LookupKey parsed by the Generate LookupKey 375 CMD is truncated to 16 bytes */ 376 }; 377 378 /* QE FLTR extended filtering Largest External Table Lookup Key Size */ 379 enum qe_fltr_largest_external_tbl_lookup_key_size { 380 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE 381 = 0x0,/* not used */ 382 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES 383 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */ 384 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES 385 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */ 386 }; 387 388 /* structure representing QE parameter RAM */ 389 struct qe_timer_tables { 390 u16 tm_base; /* QE timer table base adr */ 391 u16 tm_ptr; /* QE timer table pointer */ 392 u16 r_tmr; /* QE timer mode register */ 393 u16 r_tmv; /* QE timer valid register */ 394 u32 tm_cmd; /* QE timer cmd register */ 395 u32 tm_cnt; /* QE timer internal cnt */ 396 } __attribute__ ((packed)); 397 398 #define QE_FLTR_TAD_SIZE 8 399 400 /* QE extended filtering Termination Action Descriptor (TAD) */ 401 struct qe_fltr_tad { 402 u8 serialized[QE_FLTR_TAD_SIZE]; 403 } __attribute__ ((packed)); 404 405 /* Communication Direction */ 406 enum comm_dir { 407 COMM_DIR_NONE = 0, 408 COMM_DIR_RX = 1, 409 COMM_DIR_TX = 2, 410 COMM_DIR_RX_AND_TX = 3 411 }; 412 413 /* QE CMXUCR Registers. 414 * There are two UCCs represented in each of the four CMXUCR registers. 415 * These values are for the UCC in the LSBs 416 */ 417 #define QE_CMXUCR_MII_ENET_MNG 0x00007000 418 #define QE_CMXUCR_MII_ENET_MNG_SHIFT 12 419 #define QE_CMXUCR_GRANT 0x00008000 420 #define QE_CMXUCR_TSA 0x00004000 421 #define QE_CMXUCR_BKPT 0x00000100 422 #define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F 423 424 /* QE CMXGCR Registers. 425 */ 426 #define QE_CMXGCR_MII_ENET_MNG 0x00007000 427 #define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 428 #define QE_CMXGCR_USBCS 0x0000000f 429 #define QE_CMXGCR_USBCS_CLK3 0x1 430 #define QE_CMXGCR_USBCS_CLK5 0x2 431 #define QE_CMXGCR_USBCS_CLK7 0x3 432 #define QE_CMXGCR_USBCS_CLK9 0x4 433 #define QE_CMXGCR_USBCS_CLK13 0x5 434 #define QE_CMXGCR_USBCS_CLK17 0x6 435 #define QE_CMXGCR_USBCS_CLK19 0x7 436 #define QE_CMXGCR_USBCS_CLK21 0x8 437 #define QE_CMXGCR_USBCS_BRG9 0x9 438 #define QE_CMXGCR_USBCS_BRG10 0xa 439 440 /* QE CECR Commands. 441 */ 442 #define QE_CR_FLG 0x00010000 443 #define QE_RESET 0x80000000 444 #define QE_INIT_TX_RX 0x00000000 445 #define QE_INIT_RX 0x00000001 446 #define QE_INIT_TX 0x00000002 447 #define QE_ENTER_HUNT_MODE 0x00000003 448 #define QE_STOP_TX 0x00000004 449 #define QE_GRACEFUL_STOP_TX 0x00000005 450 #define QE_RESTART_TX 0x00000006 451 #define QE_CLOSE_RX_BD 0x00000007 452 #define QE_SWITCH_COMMAND 0x00000007 453 #define QE_SET_GROUP_ADDRESS 0x00000008 454 #define QE_START_IDMA 0x00000009 455 #define QE_MCC_STOP_RX 0x00000009 456 #define QE_ATM_TRANSMIT 0x0000000a 457 #define QE_HPAC_CLEAR_ALL 0x0000000b 458 #define QE_GRACEFUL_STOP_RX 0x0000001a 459 #define QE_RESTART_RX 0x0000001b 460 #define QE_HPAC_SET_PRIORITY 0x0000010b 461 #define QE_HPAC_STOP_TX 0x0000020b 462 #define QE_HPAC_STOP_RX 0x0000030b 463 #define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b 464 #define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b 465 #define QE_HPAC_START_TX 0x0000060b 466 #define QE_HPAC_START_RX 0x0000070b 467 #define QE_USB_STOP_TX 0x0000000a 468 #define QE_USB_RESTART_TX 0x0000000c 469 #define QE_QMC_STOP_TX 0x0000000c 470 #define QE_QMC_STOP_RX 0x0000000d 471 #define QE_SS7_SU_FIL_RESET 0x0000000e 472 #define QE_PUSHSCHED 0x0000000f 473 /* jonathbr added from here down for 83xx */ 474 #define QE_RESET_BCS 0x0000000a 475 #define QE_MCC_INIT_TX_RX_16 0x00000003 476 #define QE_MCC_STOP_TX 0x00000004 477 #define QE_MCC_INIT_TX_1 0x00000005 478 #define QE_MCC_INIT_RX_1 0x00000006 479 #define QE_MCC_RESET 0x00000007 480 #define QE_SET_TIMER 0x00000008 481 #define QE_RANDOM_NUMBER 0x0000000c 482 #define QE_ATM_MULTI_THREAD_INIT 0x00000011 483 #define QE_ASSIGN_PAGE 0x00000012 484 #define QE_ADD_REMOVE_HASH_ENTRY 0x00000013 485 #define QE_START_FLOW_CONTROL 0x00000014 486 #define QE_STOP_FLOW_CONTROL 0x00000015 487 #define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016 488 489 #define QE_ASSIGN_RISC 0x00000010 490 #define QE_CR_MCN_NORMAL_SHIFT 6 491 #define QE_CR_MCN_USB_SHIFT 4 492 #define QE_CR_MCN_RISC_ASSIGN_SHIFT 8 493 #define QE_CR_SNUM_SHIFT 17 494 495 /* QE CECR Sub Block - sub block of QE command. 496 */ 497 #define QE_CR_SUBBLOCK_INVALID 0x00000000 498 #define QE_CR_SUBBLOCK_USB 0x03200000 499 #define QE_CR_SUBBLOCK_UCCFAST1 0x02000000 500 #define QE_CR_SUBBLOCK_UCCFAST2 0x02200000 501 #define QE_CR_SUBBLOCK_UCCFAST3 0x02400000 502 #define QE_CR_SUBBLOCK_UCCFAST4 0x02600000 503 #define QE_CR_SUBBLOCK_UCCFAST5 0x02800000 504 #define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000 505 #define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000 506 #define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000 507 #define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000 508 #define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000 509 #define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000 510 #define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000 511 #define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000 512 #define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000 513 #define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000 514 #define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000 515 #define QE_CR_SUBBLOCK_MCC1 0x03800000 516 #define QE_CR_SUBBLOCK_MCC2 0x03a00000 517 #define QE_CR_SUBBLOCK_MCC3 0x03000000 518 #define QE_CR_SUBBLOCK_IDMA1 0x02800000 519 #define QE_CR_SUBBLOCK_IDMA2 0x02a00000 520 #define QE_CR_SUBBLOCK_IDMA3 0x02c00000 521 #define QE_CR_SUBBLOCK_IDMA4 0x02e00000 522 #define QE_CR_SUBBLOCK_HPAC 0x01e00000 523 #define QE_CR_SUBBLOCK_SPI1 0x01400000 524 #define QE_CR_SUBBLOCK_SPI2 0x01600000 525 #define QE_CR_SUBBLOCK_RAND 0x01c00000 526 #define QE_CR_SUBBLOCK_TIMER 0x01e00000 527 #define QE_CR_SUBBLOCK_GENERAL 0x03c00000 528 529 /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */ 530 #define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */ 531 #define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00 532 #define QE_CR_PROTOCOL_QMC 0x02 533 #define QE_CR_PROTOCOL_UART 0x04 534 #define QE_CR_PROTOCOL_ATM_POS 0x0A 535 #define QE_CR_PROTOCOL_ETHERNET 0x0C 536 #define QE_CR_PROTOCOL_L2_SWITCH 0x0D 537 538 /* BRG configuration register */ 539 #define QE_BRGC_ENABLE 0x00010000 540 #define QE_BRGC_DIVISOR_SHIFT 1 541 #define QE_BRGC_DIVISOR_MAX 0xFFF 542 #define QE_BRGC_DIV16 1 543 544 /* QE Timers registers */ 545 #define QE_GTCFR1_PCAS 0x80 546 #define QE_GTCFR1_STP2 0x20 547 #define QE_GTCFR1_RST2 0x10 548 #define QE_GTCFR1_GM2 0x08 549 #define QE_GTCFR1_GM1 0x04 550 #define QE_GTCFR1_STP1 0x02 551 #define QE_GTCFR1_RST1 0x01 552 553 /* SDMA registers */ 554 #define QE_SDSR_BER1 0x02000000 555 #define QE_SDSR_BER2 0x01000000 556 557 #define QE_SDMR_GLB_1_MSK 0x80000000 558 #define QE_SDMR_ADR_SEL 0x20000000 559 #define QE_SDMR_BER1_MSK 0x02000000 560 #define QE_SDMR_BER2_MSK 0x01000000 561 #define QE_SDMR_EB1_MSK 0x00800000 562 #define QE_SDMR_ER1_MSK 0x00080000 563 #define QE_SDMR_ER2_MSK 0x00040000 564 #define QE_SDMR_CEN_MASK 0x0000E000 565 #define QE_SDMR_SBER_1 0x00000200 566 #define QE_SDMR_SBER_2 0x00000200 567 #define QE_SDMR_EB1_PR_MASK 0x000000C0 568 #define QE_SDMR_ER1_PR 0x00000008 569 570 #define QE_SDMR_CEN_SHIFT 13 571 #define QE_SDMR_EB1_PR_SHIFT 6 572 573 #define QE_SDTM_MSNUM_SHIFT 24 574 575 #define QE_SDEBCR_BA_MASK 0x01FFFFFF 576 577 /* Communication Processor */ 578 #define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */ 579 #define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */ 580 #define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */ 581 582 /* I-RAM */ 583 #define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ 584 #define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ 585 #define QE_IRAM_READY 0x80000000 /* Ready */ 586 587 /* UPC */ 588 #define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ 589 #define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */ 590 #define UPGCR_RMS 0x20000000 /* Receive master/slave mode */ 591 #define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */ 592 #define UPGCR_DIAG 0x01000000 /* Diagnostic mode */ 593 594 /* UCC GUEMR register */ 595 #define UCC_GUEMR_MODE_MASK_RX 0x02 596 #define UCC_GUEMR_MODE_FAST_RX 0x02 597 #define UCC_GUEMR_MODE_SLOW_RX 0x00 598 #define UCC_GUEMR_MODE_MASK_TX 0x01 599 #define UCC_GUEMR_MODE_FAST_TX 0x01 600 #define UCC_GUEMR_MODE_SLOW_TX 0x00 601 #define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX) 602 #define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but 603 must be set 1 */ 604 605 /* structure representing UCC SLOW parameter RAM */ 606 struct ucc_slow_pram { 607 __be16 rbase; /* RX BD base address */ 608 __be16 tbase; /* TX BD base address */ 609 u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */ 610 u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */ 611 __be16 mrblr; /* Rx buffer length */ 612 __be32 rstate; /* Rx internal state */ 613 __be32 rptr; /* Rx internal data pointer */ 614 __be16 rbptr; /* rb BD Pointer */ 615 __be16 rcount; /* Rx internal byte count */ 616 __be32 rtemp; /* Rx temp */ 617 __be32 tstate; /* Tx internal state */ 618 __be32 tptr; /* Tx internal data pointer */ 619 __be16 tbptr; /* Tx BD pointer */ 620 __be16 tcount; /* Tx byte count */ 621 __be32 ttemp; /* Tx temp */ 622 __be32 rcrc; /* temp receive CRC */ 623 __be32 tcrc; /* temp transmit CRC */ 624 } __attribute__ ((packed)); 625 626 /* General UCC SLOW Mode Register (GUMRH & GUMRL) */ 627 #define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000 628 #define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000 629 #define UCC_SLOW_GUMR_H_REVD 0x00002000 630 #define UCC_SLOW_GUMR_H_TRX 0x00001000 631 #define UCC_SLOW_GUMR_H_TTX 0x00000800 632 #define UCC_SLOW_GUMR_H_CDP 0x00000400 633 #define UCC_SLOW_GUMR_H_CTSP 0x00000200 634 #define UCC_SLOW_GUMR_H_CDS 0x00000100 635 #define UCC_SLOW_GUMR_H_CTSS 0x00000080 636 #define UCC_SLOW_GUMR_H_TFL 0x00000040 637 #define UCC_SLOW_GUMR_H_RFW 0x00000020 638 #define UCC_SLOW_GUMR_H_TXSY 0x00000010 639 #define UCC_SLOW_GUMR_H_4SYNC 0x00000004 640 #define UCC_SLOW_GUMR_H_8SYNC 0x00000008 641 #define UCC_SLOW_GUMR_H_16SYNC 0x0000000c 642 #define UCC_SLOW_GUMR_H_RTSM 0x00000002 643 #define UCC_SLOW_GUMR_H_RSYN 0x00000001 644 645 #define UCC_SLOW_GUMR_L_TCI 0x10000000 646 #define UCC_SLOW_GUMR_L_RINV 0x02000000 647 #define UCC_SLOW_GUMR_L_TINV 0x01000000 648 #define UCC_SLOW_GUMR_L_TEND 0x00040000 649 #define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000 650 #define UCC_SLOW_GUMR_L_TDCR_32 0x00030000 651 #define UCC_SLOW_GUMR_L_TDCR_16 0x00020000 652 #define UCC_SLOW_GUMR_L_TDCR_8 0x00010000 653 #define UCC_SLOW_GUMR_L_TDCR_1 0x00000000 654 #define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000 655 #define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000 656 #define UCC_SLOW_GUMR_L_RDCR_16 0x00008000 657 #define UCC_SLOW_GUMR_L_RDCR_8 0x00004000 658 #define UCC_SLOW_GUMR_L_RDCR_1 0x00000000 659 #define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800 660 #define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000 661 #define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100 662 #define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000 663 #define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0 664 #define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0 665 #define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080 666 #define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040 667 #define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000 668 #define UCC_SLOW_GUMR_L_ENR 0x00000020 669 #define UCC_SLOW_GUMR_L_ENT 0x00000010 670 #define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F 671 #define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008 672 #define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006 673 #define UCC_SLOW_GUMR_L_MODE_UART 0x00000004 674 #define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002 675 676 /* General UCC FAST Mode Register */ 677 #define UCC_FAST_GUMR_LOOPBACK 0x40000000 678 #define UCC_FAST_GUMR_TCI 0x20000000 679 #define UCC_FAST_GUMR_TRX 0x10000000 680 #define UCC_FAST_GUMR_TTX 0x08000000 681 #define UCC_FAST_GUMR_CDP 0x04000000 682 #define UCC_FAST_GUMR_CTSP 0x02000000 683 #define UCC_FAST_GUMR_CDS 0x01000000 684 #define UCC_FAST_GUMR_CTSS 0x00800000 685 #define UCC_FAST_GUMR_TXSY 0x00020000 686 #define UCC_FAST_GUMR_RSYN 0x00010000 687 #define UCC_FAST_GUMR_SYNL_MASK 0x0000C000 688 #define UCC_FAST_GUMR_SYNL_16 0x0000C000 689 #define UCC_FAST_GUMR_SYNL_8 0x00008000 690 #define UCC_FAST_GUMR_SYNL_AUTO 0x00004000 691 #define UCC_FAST_GUMR_RTSM 0x00002000 692 #define UCC_FAST_GUMR_REVD 0x00000400 693 #define UCC_FAST_GUMR_ENR 0x00000020 694 #define UCC_FAST_GUMR_ENT 0x00000010 695 696 /* UART Slow UCC Event Register (UCCE) */ 697 #define UCC_UART_UCCE_AB 0x0200 698 #define UCC_UART_UCCE_IDLE 0x0100 699 #define UCC_UART_UCCE_GRA 0x0080 700 #define UCC_UART_UCCE_BRKE 0x0040 701 #define UCC_UART_UCCE_BRKS 0x0020 702 #define UCC_UART_UCCE_CCR 0x0008 703 #define UCC_UART_UCCE_BSY 0x0004 704 #define UCC_UART_UCCE_TX 0x0002 705 #define UCC_UART_UCCE_RX 0x0001 706 707 /* HDLC Slow UCC Event Register (UCCE) */ 708 #define UCC_HDLC_UCCE_GLR 0x1000 709 #define UCC_HDLC_UCCE_GLT 0x0800 710 #define UCC_HDLC_UCCE_IDLE 0x0100 711 #define UCC_HDLC_UCCE_BRKE 0x0040 712 #define UCC_HDLC_UCCE_BRKS 0x0020 713 #define UCC_HDLC_UCCE_TXE 0x0010 714 #define UCC_HDLC_UCCE_RXF 0x0008 715 #define UCC_HDLC_UCCE_BSY 0x0004 716 #define UCC_HDLC_UCCE_TXB 0x0002 717 #define UCC_HDLC_UCCE_RXB 0x0001 718 719 /* BISYNC Slow UCC Event Register (UCCE) */ 720 #define UCC_BISYNC_UCCE_GRA 0x0080 721 #define UCC_BISYNC_UCCE_TXE 0x0010 722 #define UCC_BISYNC_UCCE_RCH 0x0008 723 #define UCC_BISYNC_UCCE_BSY 0x0004 724 #define UCC_BISYNC_UCCE_TXB 0x0002 725 #define UCC_BISYNC_UCCE_RXB 0x0001 726 727 /* Gigabit Ethernet Fast UCC Event Register (UCCE) */ 728 #define UCC_GETH_UCCE_MPD 0x80000000 729 #define UCC_GETH_UCCE_SCAR 0x40000000 730 #define UCC_GETH_UCCE_GRA 0x20000000 731 #define UCC_GETH_UCCE_CBPR 0x10000000 732 #define UCC_GETH_UCCE_BSY 0x08000000 733 #define UCC_GETH_UCCE_RXC 0x04000000 734 #define UCC_GETH_UCCE_TXC 0x02000000 735 #define UCC_GETH_UCCE_TXE 0x01000000 736 #define UCC_GETH_UCCE_TXB7 0x00800000 737 #define UCC_GETH_UCCE_TXB6 0x00400000 738 #define UCC_GETH_UCCE_TXB5 0x00200000 739 #define UCC_GETH_UCCE_TXB4 0x00100000 740 #define UCC_GETH_UCCE_TXB3 0x00080000 741 #define UCC_GETH_UCCE_TXB2 0x00040000 742 #define UCC_GETH_UCCE_TXB1 0x00020000 743 #define UCC_GETH_UCCE_TXB0 0x00010000 744 #define UCC_GETH_UCCE_RXB7 0x00008000 745 #define UCC_GETH_UCCE_RXB6 0x00004000 746 #define UCC_GETH_UCCE_RXB5 0x00002000 747 #define UCC_GETH_UCCE_RXB4 0x00001000 748 #define UCC_GETH_UCCE_RXB3 0x00000800 749 #define UCC_GETH_UCCE_RXB2 0x00000400 750 #define UCC_GETH_UCCE_RXB1 0x00000200 751 #define UCC_GETH_UCCE_RXB0 0x00000100 752 #define UCC_GETH_UCCE_RXF7 0x00000080 753 #define UCC_GETH_UCCE_RXF6 0x00000040 754 #define UCC_GETH_UCCE_RXF5 0x00000020 755 #define UCC_GETH_UCCE_RXF4 0x00000010 756 #define UCC_GETH_UCCE_RXF3 0x00000008 757 #define UCC_GETH_UCCE_RXF2 0x00000004 758 #define UCC_GETH_UCCE_RXF1 0x00000002 759 #define UCC_GETH_UCCE_RXF0 0x00000001 760 761 /* UCC Protocol Specific Mode Register (UPSMR), when used for UART */ 762 #define UCC_UART_UPSMR_FLC 0x8000 763 #define UCC_UART_UPSMR_SL 0x4000 764 #define UCC_UART_UPSMR_CL_MASK 0x3000 765 #define UCC_UART_UPSMR_CL_8 0x3000 766 #define UCC_UART_UPSMR_CL_7 0x2000 767 #define UCC_UART_UPSMR_CL_6 0x1000 768 #define UCC_UART_UPSMR_CL_5 0x0000 769 #define UCC_UART_UPSMR_UM_MASK 0x0c00 770 #define UCC_UART_UPSMR_UM_NORMAL 0x0000 771 #define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400 772 #define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00 773 #define UCC_UART_UPSMR_FRZ 0x0200 774 #define UCC_UART_UPSMR_RZS 0x0100 775 #define UCC_UART_UPSMR_SYN 0x0080 776 #define UCC_UART_UPSMR_DRT 0x0040 777 #define UCC_UART_UPSMR_PEN 0x0010 778 #define UCC_UART_UPSMR_RPM_MASK 0x000c 779 #define UCC_UART_UPSMR_RPM_ODD 0x0000 780 #define UCC_UART_UPSMR_RPM_LOW 0x0004 781 #define UCC_UART_UPSMR_RPM_EVEN 0x0008 782 #define UCC_UART_UPSMR_RPM_HIGH 0x000C 783 #define UCC_UART_UPSMR_TPM_MASK 0x0003 784 #define UCC_UART_UPSMR_TPM_ODD 0x0000 785 #define UCC_UART_UPSMR_TPM_LOW 0x0001 786 #define UCC_UART_UPSMR_TPM_EVEN 0x0002 787 #define UCC_UART_UPSMR_TPM_HIGH 0x0003 788 789 /* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */ 790 #define UCC_GETH_UPSMR_FTFE 0x80000000 791 #define UCC_GETH_UPSMR_PTPE 0x40000000 792 #define UCC_GETH_UPSMR_ECM 0x04000000 793 #define UCC_GETH_UPSMR_HSE 0x02000000 794 #define UCC_GETH_UPSMR_PRO 0x00400000 795 #define UCC_GETH_UPSMR_CAP 0x00200000 796 #define UCC_GETH_UPSMR_RSH 0x00100000 797 #define UCC_GETH_UPSMR_RPM 0x00080000 798 #define UCC_GETH_UPSMR_R10M 0x00040000 799 #define UCC_GETH_UPSMR_RLPB 0x00020000 800 #define UCC_GETH_UPSMR_TBIM 0x00010000 801 #define UCC_GETH_UPSMR_RES1 0x00002000 802 #define UCC_GETH_UPSMR_RMM 0x00001000 803 #define UCC_GETH_UPSMR_CAM 0x00000400 804 #define UCC_GETH_UPSMR_BRO 0x00000200 805 #define UCC_GETH_UPSMR_SMM 0x00000080 806 #define UCC_GETH_UPSMR_SGMM 0x00000020 807 808 /* UCC Protocol Specific Mode Register (UPSMR), when used for HDLC */ 809 #define UCC_HDLC_UPSMR_RTE 0x02000000 810 #define UCC_HDLC_UPSMR_BUS 0x00200000 811 #define UCC_HDLC_UPSMR_CW8 0x00007000 812 813 /* UCC Transmit On Demand Register (UTODR) */ 814 #define UCC_SLOW_TOD 0x8000 815 #define UCC_FAST_TOD 0x8000 816 817 /* UCC Bus Mode Register masks */ 818 /* Not to be confused with the Bundle Mode Register */ 819 #define UCC_BMR_GBL 0x20 820 #define UCC_BMR_BO_BE 0x10 821 #define UCC_BMR_CETM 0x04 822 #define UCC_BMR_DTB 0x02 823 #define UCC_BMR_BDB 0x01 824 825 /* Function code masks */ 826 #define FC_GBL 0x20 827 #define FC_DTB_LCL 0x02 828 #define UCC_FAST_FUNCTION_CODE_GBL 0x20 829 #define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02 830 #define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01 831 832 #endif /* __KERNEL__ */ 833 #endif /* _ASM_POWERPC_QE_H */ 834