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Searched refs:primary_gt (Results 1 – 21 of 21) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/xe/
Dxe_tile.c124 tile->primary_gt = xe_gt_alloc(tile); in xe_tile_init_early()
125 if (IS_ERR(tile->primary_gt)) in xe_tile_init_early()
126 return PTR_ERR(tile->primary_gt); in xe_tile_init_early()
Dxe_irq.c55 struct xe_gt *mmio = tile->primary_gt; in unmask_and_enable()
73 struct xe_gt *mmio = tile->primary_gt; in mask_and_disable()
268 return tile->primary_gt; in pick_engine_gt()
285 return tile->primary_gt; in pick_engine_gt()
294 struct xe_gt *mmio = tile->primary_gt; in gt_irq_handler()
434 struct xe_gt *mmio = tile->primary_gt; in dg1_irq_handler()
477 struct xe_gt *mmio = tile->primary_gt; in gt_irq_reset()
479 u32 ccs_mask = xe_hw_engine_mask_per_class(tile->primary_gt, in gt_irq_reset()
481 u32 bcs_mask = xe_hw_engine_mask_per_class(tile->primary_gt, in gt_irq_reset()
550 struct xe_gt *mmio = tile->primary_gt; in dg1_irq_reset_mstr()
Dxe_device.h68 return gt_id ? tile->media_gt : tile->primary_gt; in xe_tile_get_gt()
89 gt = xe->tiles[gt_id].primary_gt; in xe_device_get_gt()
115 return xe_device_get_root_tile(xe)->primary_gt; in xe_root_mmio_gt()
Dxe_gsc.c265 if (XE_WA(tile->primary_gt, 14018094691)) { in gsc_upload_and_init()
266 ret = xe_force_wake_get(gt_to_fw(tile->primary_gt), XE_FORCEWAKE_ALL); in gsc_upload_and_init()
274 xe_gt_WARN_ON(tile->primary_gt, ret); in gsc_upload_and_init()
276 xe_gt_mcr_multicast_write(tile->primary_gt, in gsc_upload_and_init()
283 if (XE_WA(tile->primary_gt, 14018094691)) in gsc_upload_and_init()
284 xe_force_wake_put(gt_to_fw(tile->primary_gt), XE_FORCEWAKE_ALL); in gsc_upload_and_init()
Dxe_ggtt.c110 struct xe_gt *gt = XE_WA(ggtt->tile->primary_gt, 22019338487) ? ggtt->tile->primary_gt : in ggtt_update_access_counter()
112 u32 max_gtt_writes = XE_WA(ggtt->tile->primary_gt, 22019338487) ? 1100 : 63; in ggtt_update_access_counter()
241 XE_WA(ggtt->tile->primary_gt, 22019338487) ? in xe_ggtt_init_early()
411 ggtt_invalidate_gt_tlb(ggtt->tile->primary_gt); in xe_ggtt_invalidate()
422 xe_gt_dbg(ggtt->tile->primary_gt, "GGTT %#llx-%#llx (%s) %s\n", in xe_ggtt_dump_node()
455 if (xe_gt_WARN(ggtt->tile->primary_gt, err, in xe_ggtt_node_insert_balloon()
Dxe_migrate.c252 batch = tile->primary_gt->usm.bb_pool->bo; in xe_migrate_prepare_vm()
273 batch = tile->primary_gt->usm.bb_pool->bo; in xe_migrate_prepare_vm()
398 struct xe_gt *primary_gt = tile->primary_gt; in xe_migrate_init() local
424 struct xe_hw_engine *hwe = xe_gt_hw_engine(primary_gt, in xe_migrate_init()
426 primary_gt->usm.reserved_bcs_instance, in xe_migrate_init()
428 u32 logical_mask = xe_migrate_usm_logical_mask(primary_gt); in xe_migrate_init()
442 m->q = xe_exec_queue_create_class(xe, primary_gt, vm, in xe_migrate_init()
705 struct xe_gt *gt = m->tile->primary_gt; in xe_migrate_ccs_copy()
767 struct xe_gt *gt = m->tile->primary_gt; in xe_migrate_copy()
1059 struct xe_gt *gt = m->tile->primary_gt; in xe_migrate_clear()
[all …]
Dxe_pcode.c47 err = xe_mmio_read32(tile->primary_gt, PCODE_MAILBOX) & PCODE_ERROR_MASK; in pcode_mailbox_status()
61 struct xe_gt *mmio = tile->primary_gt; in __pcode_mailbox_rw()
Dxe_gt_sriov_pf_config.c308 struct xe_gt *primary = gt->tile->primary_gt; in pf_push_full_vf_config()
373 err = pf_push_vf_cfg_ggtt(tile->primary_gt, vfid, start, size); in pf_distribute_config_ggtt()
475 size = pf_get_vf_config_ggtt(gt_to_tile(gt)->primary_gt, vfid); in xe_gt_sriov_pf_config_get_ggtt()
477 size = pf_get_spare_ggtt(gt_to_tile(gt)->primary_gt); in xe_gt_sriov_pf_config_get_ggtt()
1266 if (tile->primary_gt == gt) { in pf_distribute_config_lmem()
1269 u64 lmem = pf_get_vf_config_lmem(tile->primary_gt, vfid); in pf_distribute_config_lmem()
1318 total += pf_get_vf_config_lmem(tile->primary_gt, vfid); in pf_update_vf_lmtt()
1935 xe_gt_sriov_dbg_verbose(tile->primary_gt, "LMEM cleared in %dms\n", in pf_sanitize_lmem()
2022 struct xe_gt *primary_gt = gt_to_tile(gt)->primary_gt; in pf_validate_vf_config() local
2028 valid_ggtt = pf_get_vf_config_ggtt(primary_gt, vfid); in pf_validate_vf_config()
[all …]
Dxe_vram.c221 struct xe_gt *gt = tile->primary_gt; in tile_vram_size()
233 offset += xe_gt_sriov_vf_lmem(t->primary_gt); in tile_vram_size()
Dxe_device.c643 xe_guc_comm_init_early(&tile->primary_gt->uc.guc); in xe_device_probe()
644 err = xe_gt_sriov_vf_bootstrap(tile->primary_gt); in xe_device_probe()
647 err = xe_gt_sriov_vf_query_config(tile->primary_gt); in xe_device_probe()
Dxe_device_types.h134 struct xe_gt *primary_gt; member
Dxe_query.c561 struct xe_guc *guc = &xe->tiles[0].primary_gt->uc.guc; in query_uc_fw_version()
581 media_gt = xe->tiles[0].primary_gt; in query_uc_fw_version()
Dxe_memirq.c421 memirq_dispatch_guc(memirq, &map, &tile->primary_gt->uc.guc); in xe_memirq_handler()
Dxe_lmtt.c196 xe_mmio_write32(tile->primary_gt, in lmtt_setup_dir_ptr()
Dxe_wa.c894 struct xe_gt *mmio = tile->primary_gt; in xe_wa_apply_tile_workarounds()
Dxe_pci.c705 gt = tile->primary_gt; in xe_info_init()
Dxe_exec_queue.c215 struct xe_gt *gt = tile->primary_gt; in xe_exec_queue_create_bind()
Dxe_vm.c3196 xe_gt_tlb_invalidation_fence_init(tile->primary_gt, in xe_vm_invalidate_vma()
3200 ret = xe_gt_tlb_invalidation_vma(tile->primary_gt, in xe_vm_invalidate_vma()
Dxe_pt.c2073 invalidation_fence_init(tile->primary_gt, ifence, fence, in xe_pt_update_ops_run()
/linux-6.12.1/drivers/gpu/drm/xe/tests/
Dxe_rtp_test.c311 struct xe_gt *gt = xe_device_get_root_tile(xe)->primary_gt; in xe_rtp_process_to_sr_tests()
476 struct xe_gt *gt = xe_device_get_root_tile(xe)->primary_gt; in xe_rtp_process_tests()
Dxe_migrate.c232 bb = xe_bb_new(tile->primary_gt, 32, xe->info.has_usm); in xe_migrate_sanity_test()
269 emit_clear(tile->primary_gt, bb, xe_migrate_vm_addr(NUM_KERNEL_PDE - 1, 0), 4, 4, in xe_migrate_sanity_test()
371 struct xe_gt *gt = tile->primary_gt; in blt_copy()