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Searched refs:pp_offset (Results 1 – 6 of 6) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_top.c173 static const u32 pp_offset[PINGPONG_MAX] = {0xC, 0x8, 0x4, 0x13, 0x18}; in dpu_hw_setup_vsync_sel() local
184 if (pp_idx >= ARRAY_SIZE(pp_offset)) in dpu_hw_setup_vsync_sel()
187 reg &= ~(0xf << pp_offset[pp_idx]); in dpu_hw_setup_vsync_sel()
188 reg |= (cfg->vsync_source & 0xf) << pp_offset[pp_idx]; in dpu_hw_setup_vsync_sel()
/linux-6.12.1/drivers/platform/x86/intel/speed_select_if/
Disst_tpmi_core.c70 u8 pp_offset; member
131 u64 pp_offset :8; member
346 pd_info->sst_header.pp_offset + in sst_add_perf_profiles()
349 perf_level_offsets = readq(pd_info->sst_base + pd_info->sst_header.pp_offset + in sst_add_perf_profiles()
359 pd_info->perf_levels[i].mmio_offset = pd_info->sst_header.pp_offset + offset; in sst_add_perf_profiles()
372 pd_info->sst_header.pp_offset *= 8; in sst_main()
391 *((u64 *)&pd_info->pp_header) = readq(pd_info->sst_base + pd_info->sst_header.pp_offset); in sst_main()
782 val = readq(power_domain_info->sst_base + power_domain_info->sst_header.pp_offset +\
794 val = readq(power_domain_info->sst_base + power_domain_info->sst_header.pp_offset +\
799 writeq(val, power_domain_info->sst_base + power_domain_info->sst_header.pp_offset +\
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/linux-6.12.1/drivers/misc/cxl/
Dsysfs.c215 return scnprintf(buf, PAGE_SIZE, "%llu\n", afu->native->pp_offset); in pp_mmio_off_show()
Dpci.c848 afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu); in cxl_read_afu_descriptor()
879 (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) { in cxl_afu_descriptor_looks_ok()
Dcxl.h463 u64 pp_offset; member
Dnative.c543 (ctx->afu->native->pp_offset + ctx->afu->pp_size * ctx->pe); in cxl_assign_psn_space()