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Searched refs:postdiv (Results 1 – 25 of 27) sorted by relevance

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/linux-6.12.1/arch/mips/ath79/
Dclock.c238 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; in ar934x_clocks_init() local
309 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & in ar934x_clocks_init()
315 cpu_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
317 cpu_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
319 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & in ar934x_clocks_init()
325 ddr_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
327 ddr_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
329 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & in ar934x_clocks_init()
335 ahb_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
337 ahb_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
[all …]
/linux-6.12.1/drivers/clk/mediatek/
Dclk-pll.c41 u32 pcw, int postdiv) in __mtk_pll_recalc_rate() argument
64 return ((unsigned long)vco + postdiv - 1) / postdiv; in __mtk_pll_recalc_rate()
94 int postdiv) in mtk_pll_set_rate_regs() argument
104 val |= (ffs(postdiv) - 1) << pll->data->pd_shift; in mtk_pll_set_rate_regs()
138 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, in mtk_pll_calc_values() argument
158 *postdiv = 1 << val; in mtk_pll_calc_values()
161 *postdiv = 1 << val; in mtk_pll_calc_values()
162 if ((u64)freq * *postdiv >= fmin) in mtk_pll_calc_values()
180 u32 postdiv; in mtk_pll_set_rate() local
182 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); in mtk_pll_set_rate()
[all …]
Dclk-fhctl.c171 static void __set_postdiv(struct mtk_clk_pll *pll, unsigned int postdiv) in __set_postdiv() argument
177 regval |= (ffs(postdiv) - 1) << pll->data->pd_shift; in __set_postdiv()
182 unsigned int postdiv) in fhctl_hopping() argument
193 if (postdiv) { in fhctl_hopping()
196 if (postdiv > pll_postdiv) in fhctl_hopping()
197 __set_postdiv(pll, postdiv); in fhctl_hopping()
206 if (postdiv && postdiv < pll_postdiv) in fhctl_hopping()
207 __set_postdiv(pll, postdiv); in fhctl_hopping()
Dclk-pllfh.c33 u32 postdiv; in mtk_fhctl_set_rate() local
35 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); in mtk_fhctl_set_rate()
37 return fh->ops->hopping(fh, pcw, postdiv); in mtk_fhctl_set_rate()
Dclk-pllfh.h67 unsigned int postdiv);
Dclk-pll.h95 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
/linux-6.12.1/drivers/clk/mmp/
Dclk-audio.c121 unsigned int postdiv; in audio_pll_recalc_rate() local
140 for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) { in audio_pll_recalc_rate()
146 val |= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(postdivs[postdiv].modulo); in audio_pll_recalc_rate()
154 val |= SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(postdivs[postdiv].pattern); in audio_pll_recalc_rate()
159 freq /= postdivs[postdiv].divisor; in audio_pll_recalc_rate()
171 unsigned int postdiv; in audio_pll_round_rate() local
177 for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) { in audio_pll_round_rate()
180 freq /= postdivs[postdiv].divisor; in audio_pll_round_rate()
199 unsigned int postdiv; in audio_pll_set_rate() local
206 for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) { in audio_pll_set_rate()
[all …]
Dclk-pll.c49 u32 fbdiv, refdiv, postdiv; in mmp_clk_pll_recalc_rate() local
71 postdiv = (val >> pll->postdiv_shift) & 0x7; in mmp_clk_pll_recalc_rate()
76 do_div(rate, postdivs[postdiv]); in mmp_clk_pll_recalc_rate()
/linux-6.12.1/drivers/clk/keystone/
Dpll.c60 u32 postdiv; member
81 u32 mult = 0, prediv, postdiv, val; in clk_pllclk_recalc() local
100 postdiv = ((val & pll_data->clkod_mask) >> in clk_pllclk_recalc()
103 postdiv = readl(pll_data->pllod); in clk_pllclk_recalc()
104 postdiv = ((postdiv & pll_data->clkod_mask) >> in clk_pllclk_recalc()
107 postdiv = pll_data->postdiv; in clk_pllclk_recalc()
111 rate /= postdiv; in clk_pllclk_recalc()
172 if (of_property_read_u32(node, "fixed-postdiv", &pll_data->postdiv)) { in _of_pll_clk_init()
/linux-6.12.1/drivers/media/i2c/
Dtc358746.c822 u8 postdiv; in tc358746_find_pll_settings() local
830 postdiv = 1; in tc358746_find_pll_settings()
832 postdiv = 2; in tc358746_find_pll_settings()
834 postdiv = 4; in tc358746_find_pll_settings()
836 postdiv = 8; in tc358746_find_pll_settings()
846 tmp = fout * postdiv; in tc358746_find_pll_settings()
852 do_div(tmp, postdiv); in tc358746_find_pll_settings()
871 tc358746->pll_post_div = postdiv; in tc358746_find_pll_settings()
880 best_freq, p_best, m_best, postdiv); in tc358746_find_pll_settings()
1102 unsigned int postdiv, mclkdiv; in tc358746_find_mclk_settings() local
[all …]
Dov2659.c897 u32 prediv, postdiv, mult; in ov2659_pll_calc_params() local
903 postdiv = ctrl1[i].div; in ov2659_pll_calc_params()
910 actual /= postdiv; in ov2659_pll_calc_params()
/linux-6.12.1/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy_14nm.c608 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); in dsi_pll_14nm_postdiv_recalc_rate() local
609 struct dsi_pll_14nm *pll_14nm = postdiv->pll; in dsi_pll_14nm_postdiv_recalc_rate()
611 u8 shift = postdiv->shift; in dsi_pll_14nm_postdiv_recalc_rate()
612 u8 width = postdiv->width; in dsi_pll_14nm_postdiv_recalc_rate()
621 postdiv->flags, width); in dsi_pll_14nm_postdiv_recalc_rate()
628 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); in dsi_pll_14nm_postdiv_round_rate() local
629 struct dsi_pll_14nm *pll_14nm = postdiv->pll; in dsi_pll_14nm_postdiv_round_rate()
634 postdiv->width, in dsi_pll_14nm_postdiv_round_rate()
635 postdiv->flags); in dsi_pll_14nm_postdiv_round_rate()
641 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); in dsi_pll_14nm_postdiv_set_rate() local
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dkeystone-pll.txt18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
19 for postdiv
28 fixed-postdiv = <2>;
/linux-6.12.1/drivers/clk/
Dclk-tps68470.c35 unsigned int postdiv; member
171 regmap_write(clkdata->regmap, TPS68470_REG_POSTDIV, clk_freqs[idx].postdiv); in tps68470_clk_set_rate()
172 regmap_write(clkdata->regmap, TPS68470_REG_POSTDIV2, clk_freqs[idx].postdiv); in tps68470_clk_set_rate()
Dclk-axm5516.c52 unsigned long rate, fbdiv, refdiv, postdiv; in axxia_pllclk_recalc() local
56 postdiv = ((control >> 0) & 0xf) + 1; in axxia_pllclk_recalc()
59 rate = (parent_rate / (refdiv * postdiv)) * fbdiv; in axxia_pllclk_recalc()
/linux-6.12.1/drivers/gpu/drm/bridge/
Dlontium-lt9611.c173 … lt9611_pcr_setup(struct lt9611 *lt9611, const struct drm_display_mode *mode, unsigned int postdiv) in lt9611_pcr_setup() argument
175 unsigned int pcr_m = mode->clock * 5 * postdiv / 27000; in lt9611_pcr_setup()
223 …lt9611_pll_setup(struct lt9611 *lt9611, const struct drm_display_mode *mode, unsigned int *postdiv) in lt9611_pll_setup() argument
244 *postdiv = 1; in lt9611_pll_setup()
247 *postdiv = 2; in lt9611_pll_setup()
250 *postdiv = 4; in lt9611_pll_setup()
695 unsigned int postdiv; in lt9611_bridge_atomic_enable() local
712 lt9611_pll_setup(lt9611, mode, &postdiv); in lt9611_bridge_atomic_enable()
714 lt9611_pcr_setup(lt9611, mode, postdiv); in lt9611_bridge_atomic_enable()
/linux-6.12.1/drivers/clk/visconti/
Dpll.c59 u32 postdiv, val; in visconti_pll_get_params() local
70 postdiv = readl(pll->pll_base + PLL_POSTDIV_REG); in visconti_pll_get_params()
71 rate_table->postdiv1 = postdiv & PLL_POSTDIV_MASK; in visconti_pll_get_params()
72 rate_table->postdiv2 = (postdiv >> 4) & PLL_POSTDIV_MASK; in visconti_pll_get_params()
/linux-6.12.1/drivers/clk/imx/
Dclk-composite-8m.c52 int *prediv, int *postdiv) in imx8m_clk_composite_compute_dividers() argument
59 *postdiv = 1; in imx8m_clk_composite_compute_dividers()
67 *postdiv = div2; in imx8m_clk_composite_compute_dividers()
/linux-6.12.1/drivers/video/fbdev/
Dgxt4500.c239 int m, n, pdiv1, pdiv2, postdiv; in calc_pll() local
249 postdiv = pdiv1 * pdiv2; in calc_pll()
250 pll_period = DIV_ROUND_UP(period_ps, postdiv); in calc_pll()
258 n = intf * postdiv / period_ps; in calc_pll()
261 t = par->refclk_ps * m * postdiv / n; in calc_pll()
/linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dvegam_smumgr.c683 table->SclkFcwRangeTable[i].postdiv = in vegam_get_sclk_range_table()
702 (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv; in vegam_get_sclk_range_table()
704 (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv; in vegam_get_sclk_range_table()
707 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv; in vegam_get_sclk_range_table()
760 ((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / in vegam_calculate_sclk_params()
762 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in vegam_calculate_sclk_params()
770 ((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / in vegam_calculate_sclk_params()
779 ((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / in vegam_calculate_sclk_params()
781 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in vegam_calculate_sclk_params()
Dpolaris10_smumgr.c860 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv; in polaris10_get_sclk_range_table()
874 …le[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv; in polaris10_get_sclk_range_table()
875 …le[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv; in polaris10_get_sclk_range_table()
878 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv; in polaris10_get_sclk_range_table()
930 …_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); in polaris10_calculate_sclk_params()
931 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in polaris10_calculate_sclk_params()
938 …nt16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); in polaris10_calculate_sclk_params()
945 …int16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); in polaris10_calculate_sclk_params()
946 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in polaris10_calculate_sclk_params()
/linux-6.12.1/drivers/phy/rockchip/
Dphy-rockchip-inno-hdmi.c270 u8 postdiv; member
1076 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3228_power_on()
1080 int div = cfg->postdiv / 2 - 1; in inno_hdmi_phy_rk3228_power_on()
1182 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3328_power_on()
1188 v = (cfg->postdiv / 2) - 1; in inno_hdmi_phy_rk3328_power_on()
/linux-6.12.1/drivers/clk/rockchip/
Dclk-pll.c900 u64 rate64 = prate, postdiv; in rockchip_rk3588_pll_recalc_rate() local
911 postdiv = cur.p * 65535; in rockchip_rk3588_pll_recalc_rate()
912 do_div(frac_rate64, postdiv); in rockchip_rk3588_pll_recalc_rate()
/linux-6.12.1/drivers/net/can/rcar/
Drcar_canfd.c515 u8 postdiv; member
591 .postdiv = 2,
597 .postdiv = 2,
603 .postdiv = 1,
1939 fcan_freq = clk_get_rate(gpriv->can_clk) / info->postdiv; in rcar_canfd_probe()
/linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/inc/
Dsmu74_discrete.h45 uint8_t postdiv; member

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