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Searched refs:pllp (Results 1 – 3 of 3) sorted by relevance

/linux-6.12.1/drivers/clk/tegra/
Dclk-tegra210.c1295 static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp) in tegra210_pllp_set_defaults() argument
1298 u32 val = readl_relaxed(clk_base + pllp->params->base_reg); in tegra210_pllp_set_defaults()
1300 pllp->params->defaults_set = true; in tegra210_pllp_set_defaults()
1308 pllp_check_defaults(pllp, true); in tegra210_pllp_set_defaults()
1309 if (!pllp->params->defaults_set) in tegra210_pllp_set_defaults()
1313 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1317 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1325 clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1328 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]); in tegra210_pllp_set_defaults()
1332 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]); in tegra210_pllp_set_defaults()
/linux-6.12.1/drivers/net/ethernet/mellanox/mlxsw/
Dreg.h6342 MLXSW_REG_DEFINE(pllp, MLXSW_REG_PLLP_ID, MLXSW_REG_PLLP_LEN);
6348 MLXSW_ITEM32_LP(reg, pllp, 0x00, 16, 0x00, 12);
6354 MLXSW_ITEM32(reg, pllp, label_port, 0x00, 0, 8);
6360 MLXSW_ITEM32(reg, pllp, split_num, 0x04, 0, 4);
6366 MLXSW_ITEM32(reg, pllp, slot_index, 0x08, 0, 4);
6370 MLXSW_REG_ZERO(pllp, payload); in mlxsw_reg_pllp_pack()
13077 MLXSW_REG(pllp),
Dspectrum.c1583 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pllp), pllp_pl); in mlxsw_sp_port_label_info_get()