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Searched refs:pll_value (Results 1 – 7 of 7) sorted by relevance

/linux-6.12.1/drivers/staging/sm750fb/
Dddk750_chip.h42 struct pll_value { struct
97 unsigned int sm750_calc_pll_value(unsigned int request, struct pll_value *pll);
98 unsigned int sm750_format_pll_reg(struct pll_value *p_PLL);
Dddk750_chip.c58 struct pll_value pll; in set_chip_clock()
313 struct pll_value *pll) in sm750_calc_pll_value()
385 unsigned int sm750_format_pll_reg(struct pll_value *p_PLL) in sm750_format_pll_reg()
Dddk750_mode.c79 struct pll_value *pll) in program_mode_registers()
208 struct pll_value pll; in ddk750_set_mode_timing()
/linux-6.12.1/arch/m68k/q40/
Dconfig.c251 pll->pll_value = tmp & Q40_RTC_PLL_MASK; in q40_get_rtc_pll()
253 pll->pll_value = -pll->pll_value; in q40_get_rtc_pll()
268 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) | in q40_set_rtc_pll()
/linux-6.12.1/drivers/video/fbdev/geode/
Dvideo_cs5530.c25 u32 pll_value; member
76 value = cs5530_pll_table[0].pll_value; in cs5530_set_dclk_frequency()
84 value = cs5530_pll_table[i].pll_value; in cs5530_set_dclk_frequency()
/linux-6.12.1/include/uapi/linux/
Drtc.h62 int pll_value; /* get/set correction value */ member
/linux-6.12.1/drivers/mmc/host/
Dsdhci-pci-gli.c255 u32 pll_value; in gli_set_9750() local
265 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gli_set_9750()
287 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV; in gli_set_9750()
288 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY; in gli_set_9750()
289 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, in gli_set_9750()
291 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, in gli_set_9750()
315 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); in gli_set_9750()