| /linux-6.12.1/drivers/clk/axs10x/ |
| D | pll_clock.c | 219 struct axs10x_pll_clk *pll_clk; in axs10x_pll_clk_probe() local
223 pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL); in axs10x_pll_clk_probe()
224 if (!pll_clk) in axs10x_pll_clk_probe()
227 pll_clk->base = devm_platform_ioremap_resource(pdev, 0); in axs10x_pll_clk_probe()
228 if (IS_ERR(pll_clk->base)) in axs10x_pll_clk_probe()
229 return PTR_ERR(pll_clk->base); in axs10x_pll_clk_probe()
231 pll_clk->lock = devm_platform_ioremap_resource(pdev, 1); in axs10x_pll_clk_probe()
232 if (IS_ERR(pll_clk->lock)) in axs10x_pll_clk_probe()
233 return PTR_ERR(pll_clk->lock); in axs10x_pll_clk_probe()
240 pll_clk->hw.init = &init; in axs10x_pll_clk_probe()
[all …]
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| D | i2s_pll_clock.c | 170 struct i2s_pll_clk *pll_clk; in i2s_pll_clk_probe() local
173 pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL); in i2s_pll_clk_probe()
174 if (!pll_clk) in i2s_pll_clk_probe()
177 pll_clk->base = devm_platform_ioremap_resource(pdev, 0); in i2s_pll_clk_probe()
178 if (IS_ERR(pll_clk->base)) in i2s_pll_clk_probe()
179 return PTR_ERR(pll_clk->base); in i2s_pll_clk_probe()
188 pll_clk->hw.init = &init; in i2s_pll_clk_probe()
189 pll_clk->dev = dev; in i2s_pll_clk_probe()
191 clk = devm_clk_register(dev, &pll_clk->hw); in i2s_pll_clk_probe()
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| /linux-6.12.1/drivers/clk/socfpga/ |
| D | clk-pll-s10.c | 194 struct socfpga_pll *pll_clk; in s10_register_pll() local
199 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); in s10_register_pll()
200 if (WARN_ON(!pll_clk)) in s10_register_pll()
203 pll_clk->hw.reg = reg + clks->offset; in s10_register_pll()
216 pll_clk->hw.hw.init = &init; in s10_register_pll()
218 pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER; in s10_register_pll()
220 hw_clk = &pll_clk->hw.hw; in s10_register_pll()
224 kfree(pll_clk); in s10_register_pll()
234 struct socfpga_pll *pll_clk; in agilex_register_pll() local
239 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); in agilex_register_pll()
[all …]
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| D | clk-pll-a10.c | 71 struct socfpga_pll *pll_clk; in __socfpga_pll_init() local
81 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); in __socfpga_pll_init()
82 if (WARN_ON(!pll_clk)) in __socfpga_pll_init()
89 pll_clk->hw.reg = clk_mgr_a10_base_addr + reg; in __socfpga_pll_init()
102 pll_clk->hw.hw.init = &init; in __socfpga_pll_init()
104 pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; in __socfpga_pll_init()
105 hw_clk = &pll_clk->hw.hw; in __socfpga_pll_init()
125 kfree(pll_clk); in __socfpga_pll_init()
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| D | clk-pll.c | 78 struct socfpga_pll *pll_clk; in __socfpga_pll_init() local
87 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); in __socfpga_pll_init()
88 if (WARN_ON(!pll_clk)) in __socfpga_pll_init()
95 pll_clk->hw.reg = clk_mgr_base_addr + reg; in __socfpga_pll_init()
105 pll_clk->hw.hw.init = &init; in __socfpga_pll_init()
107 pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; in __socfpga_pll_init()
109 hw_clk = &pll_clk->hw.hw; in __socfpga_pll_init()
129 kfree(pll_clk); in __socfpga_pll_init()
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| /linux-6.12.1/drivers/clk/ |
| D | clk-hsdk-pll.c | 308 struct hsdk_pll_clk *pll_clk; in hsdk_pll_clk_probe() local
312 pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL); in hsdk_pll_clk_probe()
313 if (!pll_clk) in hsdk_pll_clk_probe()
316 pll_clk->regs = devm_platform_ioremap_resource(pdev, 0); in hsdk_pll_clk_probe()
317 if (IS_ERR(pll_clk->regs)) in hsdk_pll_clk_probe()
318 return PTR_ERR(pll_clk->regs); in hsdk_pll_clk_probe()
331 pll_clk->hw.init = &init; in hsdk_pll_clk_probe()
332 pll_clk->dev = dev; in hsdk_pll_clk_probe()
333 pll_clk->pll_devdata = of_device_get_match_data(dev); in hsdk_pll_clk_probe()
335 if (!pll_clk->pll_devdata) { in hsdk_pll_clk_probe()
[all …]
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| D | clk-vt8500.c | 677 struct clk_pll *pll_clk; in vtwm_pll_clk_init() local
690 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); in vtwm_pll_clk_init()
691 if (WARN_ON(!pll_clk)) in vtwm_pll_clk_init()
694 pll_clk->reg = pmc_base + reg; in vtwm_pll_clk_init()
695 pll_clk->lock = &_lock; in vtwm_pll_clk_init()
696 pll_clk->type = pll_type; in vtwm_pll_clk_init()
707 pll_clk->hw.init = &init; in vtwm_pll_clk_init()
709 hw = &pll_clk->hw; in vtwm_pll_clk_init()
710 rc = clk_hw_register(NULL, &pll_clk->hw); in vtwm_pll_clk_init()
712 kfree(pll_clk); in vtwm_pll_clk_init()
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| D | clk-moxart.c | 59 struct clk *pll_clk; in moxart_of_apb_clk_init() local
81 pll_clk = of_clk_get(node, 0); in moxart_of_apb_clk_init()
82 if (IS_ERR(pll_clk)) { in moxart_of_apb_clk_init()
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| /linux-6.12.1/drivers/clk/renesas/ |
| D | rcar-gen4-cpg.c | 85 struct cpg_pll_clk *pll_clk = to_pll_clk(hw); in cpg_pll_8_25_clk_recalc_rate() local
86 u32 cr0 = readl(pll_clk->pllcr0_reg); in cpg_pll_8_25_clk_recalc_rate()
93 nf = FIELD_GET(CPG_PLLxCR1_NF25, readl(pll_clk->pllcr1_reg)); in cpg_pll_8_25_clk_recalc_rate()
103 struct cpg_pll_clk *pll_clk = to_pll_clk(hw); in cpg_pll_8_25_clk_determine_rate() local
105 u32 cr0 = readl(pll_clk->pllcr0_reg); in cpg_pll_8_25_clk_determine_rate()
137 struct cpg_pll_clk *pll_clk = to_pll_clk(hw); in cpg_pll_8_25_clk_set_rate() local
139 u32 cr0 = readl(pll_clk->pllcr0_reg); in cpg_pll_8_25_clk_set_rate()
158 if (readl(pll_clk->pllcr0_reg) & CPG_PLLxCR0_KICK) in cpg_pll_8_25_clk_set_rate()
161 cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_NI8, in cpg_pll_8_25_clk_set_rate()
164 cpg_reg_modify(pll_clk->pllcr1_reg, CPG_PLLxCR1_NF25, in cpg_pll_8_25_clk_set_rate()
[all …]
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| D | rcar-gen3-cpg.c | 55 struct cpg_pll_clk *pll_clk = to_pll_clk(hw); in cpg_pll_clk_recalc_rate() local
59 val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; in cpg_pll_clk_recalc_rate()
62 return parent_rate * mult * pll_clk->fixed_mult; in cpg_pll_clk_recalc_rate()
68 struct cpg_pll_clk *pll_clk = to_pll_clk(hw); in cpg_pll_clk_determine_rate() local
72 prate = req->best_parent_rate * pll_clk->fixed_mult; in cpg_pll_clk_determine_rate()
88 struct cpg_pll_clk *pll_clk = to_pll_clk(hw); in cpg_pll_clk_set_rate() local
92 mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult); in cpg_pll_clk_set_rate()
95 val = readl(pll_clk->pllcr_reg); in cpg_pll_clk_set_rate()
98 writel(val, pll_clk->pllcr_reg); in cpg_pll_clk_set_rate()
101 if (readl(pll_clk->pllecr_reg) & pll_clk->pllecr_pllst_mask) in cpg_pll_clk_set_rate()
[all …]
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| D | rzv2h-cpg.c | 86 struct pll_clk { struct
94 #define to_pll(_hw) container_of(_hw, struct pll_clk, hw) argument
135 struct pll_clk *pll_clk = to_pll(hw); in rzv2h_cpg_pll_clk_recalc_rate() local
136 struct rzv2h_cpg_priv *priv = pll_clk->priv; in rzv2h_cpg_pll_clk_recalc_rate()
140 if (!PLL_CLK_ACCESS(pll_clk->conf)) in rzv2h_cpg_pll_clk_recalc_rate()
143 clk1 = readl(priv->base + PLL_CLK1_OFFSET(pll_clk->conf)); in rzv2h_cpg_pll_clk_recalc_rate()
144 clk2 = readl(priv->base + PLL_CLK2_OFFSET(pll_clk->conf)); in rzv2h_cpg_pll_clk_recalc_rate()
166 struct pll_clk *pll_clk; in rzv2h_cpg_pll_clk_register() local
173 pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL); in rzv2h_cpg_pll_clk_register()
174 if (!pll_clk) in rzv2h_cpg_pll_clk_register()
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| D | rzg2l-cpg.c | 943 struct pll_clk { struct
951 #define to_pll(_hw) container_of(_hw, struct pll_clk, hw) argument
956 struct pll_clk *pll_clk = to_pll(hw); in rzg2l_cpg_pll_clk_recalc_rate() local
957 struct rzg2l_cpg_priv *priv = pll_clk->priv; in rzg2l_cpg_pll_clk_recalc_rate()
961 if (pll_clk->type != CLK_TYPE_SAM_PLL) in rzg2l_cpg_pll_clk_recalc_rate()
964 val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf)); in rzg2l_cpg_pll_clk_recalc_rate()
965 val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf)); in rzg2l_cpg_pll_clk_recalc_rate()
980 struct pll_clk *pll_clk = to_pll(hw); in rzg3s_cpg_pll_clk_recalc_rate() local
981 struct rzg2l_cpg_priv *priv = pll_clk->priv; in rzg3s_cpg_pll_clk_recalc_rate()
985 if (pll_clk->type != CLK_TYPE_G3S_PLL) in rzg3s_cpg_pll_clk_recalc_rate()
[all …]
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| /linux-6.12.1/arch/sh/kernel/cpu/sh2a/ |
| D | clock-sh7269.c | 47 static struct clk pll_clk = { variable
64 .parent = &pll_clk,
79 .parent = &pll_clk,
86 &pll_clk,
106 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
142 CLKDEV_CON_ID("pll_clk", &pll_clk),
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| D | clock-sh7264.c | 51 static struct clk pll_clk = { variable
60 &pll_clk,
78 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
108 CLKDEV_CON_ID("pll_clk", &pll_clk),
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| /linux-6.12.1/drivers/spi/ |
| D | spi-bcmbca-hsspi.c | 117 struct clk *pll_clk; member
439 struct clk *clk, *pll_clk = NULL; in bcmbca_hsspi_probe() local
465 pll_clk = devm_clk_get(dev, "pll"); in bcmbca_hsspi_probe()
467 if (IS_ERR(pll_clk)) { in bcmbca_hsspi_probe()
468 ret = PTR_ERR(pll_clk); in bcmbca_hsspi_probe()
472 ret = clk_prepare_enable(pll_clk); in bcmbca_hsspi_probe()
476 rate = clk_get_rate(pll_clk); in bcmbca_hsspi_probe()
492 bs->pll_clk = pll_clk; in bcmbca_hsspi_probe()
564 clk_disable_unprepare(pll_clk); in bcmbca_hsspi_probe()
577 clk_disable_unprepare(bs->pll_clk); in bcmbca_hsspi_remove()
[all …]
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| D | spi-bcm63xx-hsspi.c | 136 struct clk *pll_clk; member
730 struct clk *clk, *pll_clk = NULL; in bcm63xx_hsspi_probe() local
764 pll_clk = devm_clk_get(dev, "pll"); in bcm63xx_hsspi_probe()
766 if (IS_ERR(pll_clk)) { in bcm63xx_hsspi_probe()
767 ret = PTR_ERR(pll_clk); in bcm63xx_hsspi_probe()
771 ret = clk_prepare_enable(pll_clk); in bcm63xx_hsspi_probe()
775 rate = clk_get_rate(pll_clk); in bcm63xx_hsspi_probe()
791 bs->pll_clk = pll_clk; in bcm63xx_hsspi_probe()
874 clk_disable_unprepare(pll_clk); in bcm63xx_hsspi_probe()
888 clk_disable_unprepare(bs->pll_clk); in bcm63xx_hsspi_remove()
[all …]
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| /linux-6.12.1/arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7722.c | 82 static struct clk pll_clk = { variable
91 &pll_clk,
109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
138 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
174 CLKDEV_CON_ID("pll_clk", &pll_clk),
226 pll_clk.parent = &dll_clk; in arch_clk_init()
228 pll_clk.parent = &extal_clk; in arch_clk_init()
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| D | clock-sh7366.c | 79 static struct clk pll_clk = { variable
88 &pll_clk,
109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
125 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
188 CLKDEV_CON_ID("pll_clk", &pll_clk),
251 pll_clk.parent = &dll_clk; in arch_clk_init()
253 pll_clk.parent = &extal_clk; in arch_clk_init()
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| D | clock-shx3.c | 36 static struct clk pll_clk = { variable
44 &pll_clk,
62 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
103 CLKDEV_CON_ID("pll_clk", &pll_clk),
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| D | clock-sh7757.c | 37 static struct clk pll_clk = { variable
45 &pll_clk,
63 SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
105 CLKDEV_CON_ID("pll_clk", &pll_clk),
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| D | clock-sh7343.c | 76 static struct clk pll_clk = { variable
85 &pll_clk,
106 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
122 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
190 CLKDEV_CON_ID("pll_clk", &pll_clk),
258 pll_clk.parent = &dll_clk; in arch_clk_init()
260 pll_clk.parent = &extal_clk; in arch_clk_init()
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| D | clock-sh7723.c | 83 static struct clk pll_clk = { variable
92 &pll_clk,
112 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
138 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
199 CLKDEV_CON_ID("pll_clk", &pll_clk),
274 pll_clk.parent = &dll_clk; in arch_clk_init()
276 pll_clk.parent = &extal_clk; in arch_clk_init()
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| D | clock-sh7785.c | 40 static struct clk pll_clk = { variable
48 &pll_clk,
67 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
119 CLKDEV_CON_ID("pll_clk", &pll_clk),
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| D | clock-sh7724.c | 85 static struct clk pll_clk = { variable
102 .parent = &pll_clk,
119 &pll_clk,
151 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
264 CLKDEV_CON_ID("pll_clk", &pll_clk),
348 pll_clk.parent = &fll_clk; in arch_clk_init()
350 pll_clk.parent = &extal_clk; in arch_clk_init()
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| /linux-6.12.1/drivers/clk/imx/ |
| D | clk-fracn-gppll.c | 350 const struct imx_fracn_gppll_clk *pll_clk, in _imx_clk_fracn_gppll() argument
363 init.flags = pll_clk->flags; in _imx_clk_fracn_gppll()
370 pll->rate_table = pll_clk->rate_table; in _imx_clk_fracn_gppll()
371 pll->rate_count = pll_clk->rate_count; in _imx_clk_fracn_gppll()
387 const struct imx_fracn_gppll_clk *pll_clk) in imx_clk_fracn_gppll() argument
389 return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_FRACN); in imx_clk_fracn_gppll()
395 const struct imx_fracn_gppll_clk *pll_clk) in imx_clk_fracn_gppll_integer() argument
397 return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_INTEGER); in imx_clk_fracn_gppll_integer()
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