/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce60/ |
D | dce60_hw_sequencer.c | 151 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; in dce60_set_default_colors() 158 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; in dce60_set_default_colors() 160 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( in dce60_set_default_colors() 161 pipe_ctx->plane_res.xfm, &default_adjust); in dce60_set_default_colors() 202 switch (pipe_ctx->plane_res.scl_data.format) { in dce60_get_surface_visual_confirm_color() 246 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( in dce60_program_scaler() 247 pipe_ctx->plane_res.xfm, in dce60_program_scaler() 248 pipe_ctx->plane_res.scl_data.lb_params.depth, in dce60_program_scaler() 265 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, in dce60_program_scaler() 266 &pipe_ctx->plane_res.scl_data); in dce60_program_scaler() [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
D | dcn_calcs.c | 318 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) { in pipe_ctx_to_e2e_pipe_params() 333 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params() 341 input->src.viewport_width = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params() 342 input->src.viewport_height = pipe->plane_res.scl_data.viewport.height; in pipe_ctx_to_e2e_pipe_params() 343 input->src.data_pitch = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params() 344 input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params() 398 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; in pipe_ctx_to_e2e_pipe_params() 399 input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params() 400 input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params() 401 input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params() [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/core/ |
D | dc_resource.c | 774 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; in calculate_viewport_size() 950 if (dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE || !pipe_ctx->plane_res.dpp) in calculate_adjust_recout_for_visual_confirm() 954 *dpp_offset *= pipe_ctx->plane_res.dpp->inst; in calculate_adjust_recout_for_visual_confirm() 1121 pipe_ctx->plane_res.scl_data.recout = shift_rec( in calculate_recout() 1125 &pipe_ctx->plane_res.scl_data.recout, in calculate_recout() 1129 memset(&pipe_ctx->plane_res.scl_data.recout, 0, in calculate_recout() 1150 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction( in calculate_scaling_ratios() 1153 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction( in calculate_scaling_ratios() 1158 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; in calculate_scaling_ratios() 1160 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; in calculate_scaling_ratios() [all …]
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D | dc_stream.c | 351 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || in program_cursor_position() 353 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) || in program_cursor_position() 354 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp)) in program_cursor_position() 445 pipe_ctx->plane_res.hubp->mpcc_id); in dc_stream_program_cursor_position() 764 hubp = pipe_ctx->plane_res.hubp; in dc_stream_set_dynamic_metadata()
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D | dc_surface.c | 76 if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp) in dc_plane_get_pipe_mask() 77 pipe_mask |= 1 << pipe_ctx->plane_res.hubp->inst; in dc_plane_get_pipe_mask()
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D | dc_hw_sequencer.c | 336 switch (pipe_ctx->plane_res.scl_data.format) { in get_surface_visual_confirm_color() 393 switch (top_pipe_ctx->plane_res.scl_data.format) { in get_hdr_visual_confirm_color() 703 …ce[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst; in hwss_build_fast_sequence() 881 struct dpp *dpp = pipe_ctx->plane_res.dpp; in hwss_setup_dpp() 904 struct dpp *dpp = pipe_ctx->plane_res.dpp; in hwss_program_bias_and_scale() 1077 hubp = pipe_ctx->plane_res.hubp; in hwss_wait_for_outstanding_hw_updates()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
D | dce110_hwseq.c | 285 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; in dce110_set_input_transfer_func() 608 struct transform *xfm = pipe_ctx->plane_res.xfm; in dce110_set_output_transfer_func() 1473 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) in program_scaler() 1483 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( in program_scaler() 1484 pipe_ctx->plane_res.xfm, in program_scaler() 1485 pipe_ctx->plane_res.scl_data.lb_params.depth, in program_scaler() 1502 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, in program_scaler() 1503 &pipe_ctx->plane_res.scl_data); in program_scaler() 1692 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; in dce110_apply_single_controller_ctx_to_hw() 2022 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( in dce110_set_displaymarks() [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
D | dcn35_hwseq.c | 795 pipe_ctx->plane_res.hubp = hubp; in dcn35_init_pipes() 796 pipe_ctx->plane_res.dpp = dpp; in dcn35_init_pipes() 797 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn35_init_pipes() 804 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn35_init_pipes() 815 pipe_ctx->plane_res.hubp = NULL; in dcn35_init_pipes() 887 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); in dcn35_enable_plane() 890 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); in dcn35_enable_plane() 906 …pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &a… in dcn35_enable_plane() 912 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) in dcn35_enable_plane() 913 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); in dcn35_enable_plane() [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/ |
D | dc_spl_translate.c | 91 spl_in->basic_in.format = (enum spl_pixel_format)pipe_ctx->plane_res.scl_data.format; in translate_SPL_in_params_from_pipe_ctx() 130 spl_in->basic_out.alpha_en = pipe_ctx->plane_res.scl_data.lb_params.alpha_en; in translate_SPL_in_params_from_pipe_ctx() 187 spl_in->h_active = pipe_ctx->plane_res.scl_data.h_active; in translate_SPL_in_params_from_pipe_ctx() 188 spl_in->v_active = pipe_ctx->plane_res.scl_data.v_active; in translate_SPL_in_params_from_pipe_ctx() 208 populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.recout, &spl_out->dscl_prog_data->recout); in translate_SPL_out_params_to_pipe_ctx() 210 …populate_ratios_from_splratios(&pipe_ctx->plane_res.scl_data.ratios, &spl_out->dscl_prog_data->rat… in translate_SPL_out_params_to_pipe_ctx() 212 …populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport, &spl_out->dscl_prog_data->viewp… in translate_SPL_out_params_to_pipe_ctx() 214 …populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport_c, &spl_out->dscl_prog_data->vie… in translate_SPL_out_params_to_pipe_ctx() 216 populate_taps_from_spltaps(&pipe_ctx->plane_res.scl_data.taps, &spl_out->dscl_prog_data->taps); in translate_SPL_out_params_to_pipe_ctx() 218 populate_inits_from_splinits(&pipe_ctx->plane_res.scl_data.inits, &spl_out->dscl_prog_data->init); in translate_SPL_out_params_to_pipe_ctx()
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D | dc_trace.h | 31 pipe_ctx->stream, &pipe_ctx->plane_res, \
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D | dc_dmub_srv.c | 413 fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst; in dc_dmub_srv_populate_fams_pipe_info() 418 fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst; in dc_dmub_srv_populate_fams_pipe_info() 834 …>pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst; in populate_subvp_cmd_pipe_info() 836 …ipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst; in populate_subvp_cmd_pipe_info() 996 const struct scaler_data *scl_data = &pipe_ctx->plane_res.scl_data; in dc_can_pipe_disable_cursor() 1012 r2 = test_pipe->plane_res.scl_data.recout; in dc_can_pipe_disable_cursor() 1024 r2_half = split_pipe->plane_res.scl_data.recout; in dc_can_pipe_disable_cursor() 1063 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dc_build_cursor_update_payload0() 1157 pCtx->plane_res.hubp, pCtx->plane_res.dpp); in dc_send_update_cursor_info_to_dmu() 1167 pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp); in dc_send_update_cursor_info_to_dmu()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
D | dcn20_hwseq.c | 292 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) in dcn20_set_flip_control_gsl() 293 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( in dcn20_set_flip_control_gsl() 294 pipe_ctx->plane_res.hubp, flip_immediate); in dcn20_set_flip_control_gsl() 388 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { in dcn20_program_triple_buffer() 389 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( in dcn20_program_triple_buffer() 390 pipe_ctx->plane_res.hubp, in dcn20_program_triple_buffer() 696 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn20_plane_atomic_disable() 697 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn20_plane_atomic_disable() 719 pipe_ctx->plane_res.dpp, in dcn20_plane_atomic_disable() 720 pipe_ctx->plane_res.hubp); in dcn20_plane_atomic_disable() [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
D | dcn201_hwseq.c | 149 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( in dcn201_update_plane_addr() 150 pipe_ctx->plane_res.hubp, in dcn201_update_plane_addr() 313 pipe_ctx->plane_res.hubp = hubp; in dcn201_init_hw() 314 pipe_ctx->plane_res.dpp = dpp; in dcn201_init_hw() 315 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn201_init_hw() 323 res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn201_init_hw() 346 pipe_ctx->plane_res.hubp = NULL; in dcn201_init_hw() 380 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn201_plane_atomic_disconnect() 381 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn201_plane_atomic_disconnect() 411 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn201_plane_atomic_disconnect() [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
D | dcn10_hwseq.c | 598 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_did_underflow_occur() 1155 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery() 1168 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery() 1178 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery() 1190 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery() 1230 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_plane_atomic_disconnect() 1231 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn10_plane_atomic_disconnect() 1248 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn10_plane_atomic_disconnect() 1307 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_plane_atomic_disable() 1308 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn10_plane_atomic_disable() [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
D | dcn401_hwseq.c | 84 unsigned int mpcc_id = pipe_ctx->plane_res.mpcc_inst; in dcn401_program_gamut_remap() 457 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn401_get_mcm_lut_xable_from_pipe_ctx() 487 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn401_populate_mcm_luts() 488 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn401_populate_mcm_luts() 660 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn401_trigger_3dlut_dma_load() 670 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn401_set_mcm_luts() 671 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn401_set_mcm_luts() 716 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn401_set_output_transfer_func() 1045 const struct scaler_data *scl_data = &pipe_ctx->plane_res.scl_data; in dcn401_can_pipe_disable_cursor() 1063 r2 = test_pipe->plane_res.scl_data.recout; in dcn401_can_pipe_disable_cursor() [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/amdgpu_dm/ |
D | amdgpu_dm_trace.h | 386 const struct plane_resource *plane_res, 388 TP_ARGS(pipe_idx, plane_state, stream, plane_res, update_flags), 439 __entry->recout_x = plane_res->scl_data.recout.x; 440 __entry->recout_y = plane_res->scl_data.recout.y; 441 __entry->recout_w = plane_res->scl_data.recout.width; 442 __entry->recout_h = plane_res->scl_data.recout.height; 443 __entry->viewport_x = plane_res->scl_data.viewport.x; 444 __entry->viewport_y = plane_res->scl_data.viewport.y; 445 __entry->viewport_w = plane_res->scl_data.viewport.width; 446 __entry->viewport_h = plane_res->scl_data.viewport.height;
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
D | dcn20_resource.c | 1490 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm() 1491 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm() 1492 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm() 1493 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm() 1494 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm() 1495 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; in dcn20_split_stream_for_odm() 1513 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; in dcn20_split_stream_for_odm() 1530 sd = &next_odm_pipe->plane_res.scl_data; in dcn20_split_stream_for_odm() 1575 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc() 1576 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc() [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
D | dcn30_hwseq.c | 224 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut() 246 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_mpc_shaper_3dlut() 247 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_mpc_shaper_3dlut() 301 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_input_transfer_func() 341 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_program_gamut_remap() 355 pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, in dcn30_program_gamut_remap() 377 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_output_transfer_func() 592 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dcn30_program_all_writeback_pipes_in_tree() 869 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn30_program_dmdata_engine()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/ |
D | dml2_mall_phantom.c | 62 full_vp_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x + in dml2_helper_calculate_num_ways_for_subvp() 63 pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) + in dml2_helper_calculate_num_ways_for_subvp() 64 (pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width); in dml2_helper_calculate_num_ways_for_subvp() 126 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in merge_pipes_for_subvp() 140 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in merge_pipes_for_subvp()
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D | dml2_utils.c | 273 pipe_ctx->pipe_dlg_param.recout_height = pipe_ctx->plane_res.scl_data.recout.height; in populate_pipe_ctx_dlg_params_from_dml() 274 pipe_ctx->pipe_dlg_param.recout_width = pipe_ctx->plane_res.scl_data.recout.width; in populate_pipe_ctx_dlg_params_from_dml() 275 pipe_ctx->pipe_dlg_param.full_recout_height = pipe_ctx->plane_res.scl_data.recout.height; in populate_pipe_ctx_dlg_params_from_dml() 276 pipe_ctx->pipe_dlg_param.full_recout_width = pipe_ctx->plane_res.scl_data.recout.width; in populate_pipe_ctx_dlg_params_from_dml() 335 …context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz = dml_get_dppclk_calculated(&… in dml2_calculate_rq_and_dlg_params() 336 …w_ctx.bw.dcn.clk.dppclk_khz < context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz) in dml2_calculate_rq_and_dlg_params() 337 …context->bw_ctx.bw.dcn.clk.dppclk_khz = context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.… in dml2_calculate_rq_and_dlg_params()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
D | dml21_translation_helper.c | 710 temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps; in get_scaler_data_for_plane() 718 return &temp_pipe->plane_res.scl_data; in get_scaler_data_for_plane() 1147 pipe_ctx->pipe_dlg_param.recout_height = pipe_ctx->plane_res.scl_data.recout.height; in dml21_populate_pipe_ctx_dlg_params() 1148 pipe_ctx->pipe_dlg_param.recout_width = pipe_ctx->plane_res.scl_data.recout.width; in dml21_populate_pipe_ctx_dlg_params() 1149 pipe_ctx->pipe_dlg_param.full_recout_height = pipe_ctx->plane_res.scl_data.recout.height; in dml21_populate_pipe_ctx_dlg_params() 1150 pipe_ctx->pipe_dlg_param.full_recout_width = pipe_ctx->plane_res.scl_data.recout.width; in dml21_populate_pipe_ctx_dlg_params() 1172 mcache_pipe_config->plane0.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x; in dml21_get_pipe_mcache_config() 1173 mcache_pipe_config->plane0.viewport_width = pipe_ctx->plane_res.scl_data.viewport.width; in dml21_get_pipe_mcache_config() 1175 mcache_pipe_config->plane1.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport_c.x; in dml21_get_pipe_mcache_config() 1176 mcache_pipe_config->plane1.viewport_width = pipe_ctx->plane_res.scl_data.viewport_c.width; in dml21_get_pipe_mcache_config()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
D | dcn32_resource_helpers.c | 44 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn32_helper_calculate_mall_bytes_for_cursor() 133 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn32_merge_pipes_for_subvp() 147 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn32_merge_pipes_for_subvp()
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D | dcn32_resource.c | 2707 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer() 2708 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer() 2709 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer() 2710 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer() 2766 free_pipe->plane_res.hubp = pool->hubps[free_pipe->pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe() 2767 free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe() 2768 free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe() 2769 free_pipe->plane_res.mpcc_inst = in dcn32_acquire_free_pipe_as_secondary_dpp_pipe() 2797 free_pipe->plane_res.mi = pool->mis[free_pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_opp_head() 2798 free_pipe->plane_res.hubp = pool->hubps[free_pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_opp_head() [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
D | rv1_clk_mgr.c | 169 pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control( in ramp_up_dispclk_with_dpp() 170 pipe_ctx->plane_res.dpp, in ramp_up_dispclk_with_dpp()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/ |
D | dmub_psr.c | 341 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dmub_psr_copy_settings() 343 if (pipe_ctx->plane_res.dpp) in dmub_psr_copy_settings() 344 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; in dmub_psr_copy_settings()
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