Home
last modified time | relevance | path

Searched refs:pixel_rep (Results 1 – 3 of 3) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/vc4/
Dvc4_crtc.c335 u32 pixel_rep = ((mode->flags & DRM_MODE_FLAG_DBLCLK) && !is_hdmi) ? 2 : 1; in vc4_crtc_config_pv() local
363 VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc, in vc4_crtc_config_pv()
365 VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc, in vc4_crtc_config_pv()
369 VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc, in vc4_crtc_config_pv()
371 VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc, in vc4_crtc_config_pv()
376 u32 field_delay = mode->htotal * pixel_rep / (2 * ppc); in vc4_crtc_config_pv()
429 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); in vc4_crtc_config_pv()
439 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | in vc4_crtc_config_pv()
Dvc4_hdmi.c1219 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; in vc4_hdmi_set_timings() local
1245 VC4_SET_FIELD(mode->hdisplay * pixel_rep, in vc4_hdmi_set_timings()
1250 mode->hsync_end) * pixel_rep, in vc4_hdmi_set_timings()
1253 mode->hsync_start) * pixel_rep, in vc4_hdmi_set_timings()
1256 mode->hdisplay) * pixel_rep, in vc4_hdmi_set_timings()
1267 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP); in vc4_hdmi_set_timings()
1283 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; in vc5_hdmi_set_timings() local
1289 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep), in vc5_hdmi_set_timings()
1311 VC4_SET_FIELD(mode->hdisplay * pixel_rep, in vc5_hdmi_set_timings()
1314 mode->hdisplay) * pixel_rep, in vc5_hdmi_set_timings()
[all …]
/linux-6.12.1/drivers/video/fbdev/aty/
Dmach64_gx.c87 u8 pixel_rep; in aty_set_dac_514() member
117 aty_st_514(0x0a, tab[i].pixel_rep, par); /* Pixel Format */ in aty_set_dac_514()