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/linux-6.12.1/drivers/staging/media/atomisp/pci/runtime/pipeline/src/
Dpipeline.c44 struct ia_css_pipeline *pipeline,
53 static void ia_css_pipeline_set_zoom_stage(struct ia_css_pipeline *pipeline);
66 struct ia_css_pipeline *pipeline, in ia_css_pipeline_create() argument
71 assert(pipeline); in ia_css_pipeline_create()
73 pipeline, pipe_id, pipe_num, dvs_frame_delay); in ia_css_pipeline_create()
74 if (!pipeline) { in ia_css_pipeline_create()
79 pipeline_init_defaults(pipeline, pipe_id, pipe_num, dvs_frame_delay); in ia_css_pipeline_create()
108 void ia_css_pipeline_destroy(struct ia_css_pipeline *pipeline) in ia_css_pipeline_destroy() argument
110 assert(pipeline); in ia_css_pipeline_destroy()
111 IA_CSS_ENTER_PRIVATE("pipeline = %p", pipeline); in ia_css_pipeline_destroy()
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/linux-6.12.1/drivers/gpu/drm/xen/
Dxen_drm_front_kms.c93 static void send_pending_event(struct xen_drm_front_drm_pipeline *pipeline) in send_pending_event() argument
95 struct drm_crtc *crtc = &pipeline->pipe.crtc; in send_pending_event()
100 if (pipeline->pending_event) in send_pending_event()
101 drm_crtc_send_vblank_event(crtc, pipeline->pending_event); in send_pending_event()
102 pipeline->pending_event = NULL; in send_pending_event()
110 struct xen_drm_front_drm_pipeline *pipeline = in display_enable() local
119 ret = xen_drm_front_mode_set(pipeline, crtc->x, crtc->y, in display_enable()
126 pipeline->conn_connected = false; in display_enable()
134 struct xen_drm_front_drm_pipeline *pipeline = in display_disable() local
139 ret = xen_drm_front_mode_set(pipeline, 0, 0, 0, 0, 0, in display_disable()
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Dxen_drm_front_conn.c50 struct xen_drm_front_drm_pipeline *pipeline = in connector_detect() local
54 pipeline->conn_connected = false; in connector_detect()
56 return pipeline->conn_connected ? connector_status_connected : in connector_detect()
64 struct xen_drm_front_drm_pipeline *pipeline = in connector_get_modes() local
75 videomode.hactive = pipeline->width; in connector_get_modes()
76 videomode.vactive = pipeline->height; in connector_get_modes()
105 struct xen_drm_front_drm_pipeline *pipeline = in xen_drm_front_conn_init() local
110 pipeline->conn_connected = true; in xen_drm_front_conn_init()
/linux-6.12.1/drivers/isdn/mISDN/
Ddsp_pipeline.c163 int dsp_pipeline_init(struct dsp_pipeline *pipeline) in dsp_pipeline_init() argument
165 if (!pipeline) in dsp_pipeline_init()
168 INIT_LIST_HEAD(&pipeline->list); in dsp_pipeline_init()
173 static inline void _dsp_pipeline_destroy(struct dsp_pipeline *pipeline) in _dsp_pipeline_destroy() argument
177 list_for_each_entry_safe(entry, n, &pipeline->list, list) { in _dsp_pipeline_destroy()
180 dsp_hwec_disable(container_of(pipeline, struct dsp, in _dsp_pipeline_destroy()
181 pipeline)); in _dsp_pipeline_destroy()
188 void dsp_pipeline_destroy(struct dsp_pipeline *pipeline) in dsp_pipeline_destroy() argument
191 if (!pipeline) in dsp_pipeline_destroy()
194 _dsp_pipeline_destroy(pipeline); in dsp_pipeline_destroy()
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Ddsp.h236 pipeline; member
271 extern int dsp_pipeline_init(struct dsp_pipeline *pipeline);
272 extern void dsp_pipeline_destroy(struct dsp_pipeline *pipeline);
273 extern int dsp_pipeline_build(struct dsp_pipeline *pipeline, const char *cfg);
274 extern void dsp_pipeline_process_tx(struct dsp_pipeline *pipeline, u8 *data,
276 extern void dsp_pipeline_process_rx(struct dsp_pipeline *pipeline, u8 *data,
/linux-6.12.1/drivers/staging/media/atomisp/pci/runtime/pipeline/interface/
Dia_css_pipeline.h102 struct ia_css_pipeline *pipeline,
113 void ia_css_pipeline_destroy(struct ia_css_pipeline *pipeline);
123 struct ia_css_pipeline *pipeline);
131 int ia_css_pipeline_request_stop(struct ia_css_pipeline *pipeline);
147 void ia_css_pipeline_clean(struct ia_css_pipeline *pipeline);
161 struct ia_css_pipeline *pipeline,
172 void ia_css_pipeline_finalize_stages(struct ia_css_pipeline *pipeline,
181 int ia_css_pipeline_get_stage(struct ia_css_pipeline *pipeline,
195 *pipeline,
209 *pipeline,
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/linux-6.12.1/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_crtc.c95 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; in crtc_flush() local
102 return mdp5_ctl_commit(ctl, pipeline, flush_mask, start); in crtc_flush()
127 mixer = mdp5_cstate->pipeline.mixer; in crtc_flush_all()
130 r_mixer = mdp5_cstate->pipeline.r_mixer; in crtc_flush_all()
141 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; in complete_flip() local
159 mdp5_ctl_blend(ctl, pipeline, NULL, NULL, 0, 0); in complete_flip()
215 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; in blend_setup() local
220 struct mdp5_hw_mixer *mixer = pipeline->mixer; in blend_setup()
222 struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer; in blend_setup()
355 mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt, in blend_setup()
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Dmdp5_ctl.c135 static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline) in set_ctl_op() argument
138 struct mdp5_interface *intf = pipeline->intf; in set_ctl_op()
159 if (pipeline->r_mixer) in set_ctl_op()
168 int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline) in mdp5_ctl_set_pipeline() argument
171 struct mdp5_interface *intf = pipeline->intf; in mdp5_ctl_set_pipeline()
177 set_ctl_op(ctl, pipeline); in mdp5_ctl_set_pipeline()
183 struct mdp5_pipeline *pipeline) in start_signal_needed() argument
185 struct mdp5_interface *intf = pipeline->intf; in start_signal_needed()
227 struct mdp5_pipeline *pipeline, in mdp5_ctl_set_encoder_state() argument
230 struct mdp5_interface *intf = pipeline->intf; in mdp5_ctl_set_encoder_state()
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Dmdp5_cmd_encoder.c129 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_cmd_encoder_disable() local
136 mdp5_ctl_set_encoder_state(ctl, pipeline, false); in mdp5_cmd_encoder_disable()
137 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_cmd_encoder_disable()
147 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_cmd_encoder_enable() local
155 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_cmd_encoder_enable()
157 mdp5_ctl_set_encoder_state(ctl, pipeline, true); in mdp5_cmd_encoder_enable()
Dmdp5_ctl.h36 int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
54 int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
71 u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
Dmdp5_encoder.c125 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_vid_encoder_disable() local
134 mdp5_ctl_set_encoder_state(ctl, pipeline, false); in mdp5_vid_encoder_disable()
139 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_vid_encoder_disable()
160 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_vid_encoder_enable() local
170 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_vid_encoder_enable()
172 mdp5_ctl_set_encoder_state(ctl, pipeline, true); in mdp5_vid_encoder_enable()
226 mdp5_cstate->pipeline.intf = intf; in mdp5_encoder_atomic_check()
/linux-6.12.1/drivers/net/wireless/ti/wl18xx/
Ddebugfs.c143 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, hs_tx_stat_fifo_int, "%u");
144 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, enc_tx_stat_fifo_int, "%u");
145 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, enc_rx_stat_fifo_int, "%u");
146 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, rx_complete_stat_fifo_int, "%u");
147 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, pre_proc_swi, "%u");
148 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, post_proc_swi, "%u");
149 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, sec_frag_swi, "%u");
150 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, pre_to_defrag_swi, "%u");
151 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, defrag_to_rx_xfer_swi, "%u");
152 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, dec_packet_in, "%u");
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/linux-6.12.1/Documentation/gpu/
Dkomeda-kms.rst15 architecture. A display pipeline is made up of multiple individual and
16 functional pipeline stages called components, and every component has some
17 specific capabilities that can give the flowed pipeline pixel data a
24 Layer is the first pipeline stage, which prepares the pixel data for the next
58 Final stage of display pipeline, Timing controller is not for the pixel
94 Single pipeline data flow
98 :alt: Single pipeline digraph
99 :caption: Single pipeline data flow
140 Dual pipeline with Slave enabled
144 :alt: Slave pipeline digraph
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/linux-6.12.1/sound/soc/sof/intel/
Dhda-dai-ops.c130 struct sof_ipc4_pipeline *pipeline; in hda_ipc4_get_hext_stream() local
137 pipeline = pipe_widget->private; in hda_ipc4_get_hext_stream()
140 pipeline->skip_during_fe_trigger = true; in hda_ipc4_get_hext_stream()
301 struct sof_ipc4_pipeline *pipeline; in hda_ipc4_pre_trigger() local
309 pipeline = pipe_widget->private; in hda_ipc4_pre_trigger()
328 pipeline->state = SOF_IPC4_PIPE_PAUSED; in hda_ipc4_pre_trigger()
378 struct sof_ipc4_pipeline *pipeline; in hda_ipc4_post_trigger() local
386 pipeline = pipe_widget->private; in hda_ipc4_post_trigger()
395 if (pipeline->state != SOF_IPC4_PIPE_PAUSED) { in hda_ipc4_post_trigger()
400 pipeline->state = SOF_IPC4_PIPE_PAUSED; in hda_ipc4_post_trigger()
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/linux-6.12.1/sound/soc/sof/
Dipc4-topology.c424 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; in sof_ipc4_update_card_components_string() local
434 if (!pipeline->use_chain_dma) in sof_ipc4_update_card_components_string()
595 struct sof_ipc4_pipeline *pipeline; in sof_ipc4_widget_setup_comp_dai() local
635 pipeline = pipe_widget->private; in sof_ipc4_widget_setup_comp_dai()
637 if (pipeline->use_chain_dma && in sof_ipc4_widget_setup_comp_dai()
763 struct sof_ipc4_pipeline *pipeline; in sof_ipc4_widget_setup_comp_pipeline() local
767 pipeline = kzalloc(sizeof(*pipeline), GFP_KERNEL); in sof_ipc4_widget_setup_comp_pipeline()
768 if (!pipeline) in sof_ipc4_widget_setup_comp_pipeline()
771 ret = sof_update_ipc_object(scomp, pipeline, SOF_SCHED_TOKENS, swidget->tuples, in sof_ipc4_widget_setup_comp_pipeline()
772 swidget->num_tuples, sizeof(*pipeline), 1); in sof_ipc4_widget_setup_comp_pipeline()
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Dipc4-pcm.c110 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; in sof_ipc4_add_pipeline_by_priority() local
115 if (ascend && pipeline->priority < pipe_priority[i]) in sof_ipc4_add_pipeline_by_priority()
118 else if (!ascend && pipeline->priority > pipe_priority[i]) in sof_ipc4_add_pipeline_by_priority()
129 pipe_priority[i] = pipeline->priority; in sof_ipc4_add_pipeline_by_priority()
139 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; in sof_ipc4_add_pipeline_to_trigger_list() local
141 if (pipeline->skip_during_fe_trigger && state != SOF_IPC4_PIPE_RESET) in sof_ipc4_add_pipeline_to_trigger_list()
177 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; in sof_ipc4_update_pipeline_state() local
180 if (pipeline->skip_during_fe_trigger && state != SOF_IPC4_PIPE_RESET) in sof_ipc4_update_pipeline_state()
186 pipeline->state = state; in sof_ipc4_update_pipeline_state()
333 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; in sof_ipc4_chain_dma_trigger() local
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/linux-6.12.1/drivers/staging/media/atomisp/pci/runtime/binary/src/
Dbinary.c82 + info->pipeline.left_cropping + binary_dvs_env.width; in ia_css_binary_internal_res()
84 + info->pipeline.top_cropping + binary_dvs_env.height; in ia_css_binary_internal_res()
103 info->pipeline.left_cropping, info->pipeline.mode, in ia_css_binary_internal_res()
104 info->pipeline.c_subsampling, in ia_css_binary_internal_res()
105 info->output.num_chunks, info->pipeline.pipelining); in ia_css_binary_internal_res()
107 info->pipeline.top_cropping, in ia_css_binary_internal_res()
181 if (need_bds_factor_2_00 && binary->info->sp.pipeline.left_cropping > 0) in ia_css_binary_compute_shading_table_bayer_origin()
405 metrics->mode = info->pipeline.mode; in binary_init_metrics()
501 binary->next = binary_infos[binary->sp.pipeline.mode]; in ia_css_binary_init_infos()
502 binary_infos[binary->sp.pipeline.mode] = binary; in ia_css_binary_init_infos()
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/linux-6.12.1/tools/testing/selftests/kvm/lib/
Dassert.c30 const char *pipeline = "|cat -n 1>&2"; in test_dump_stack() local
31 char cmd[strlen(addr2line) + strlen(pipeline) + in test_dump_stack()
54 c += sprintf(c, "%s", pipeline); in test_dump_stack()
/linux-6.12.1/Documentation/gpu/amdgpu/display/
Ddcn-overview.rst6 (DCN) works, we need to start with an overview of the hardware pipeline. Below
53 pipeline is connected to the Scalable Data Port (SDP) via DCHUB; you can see
86 Display pipeline can be broken down into two components that are usually
130 When discussing graphics on Linux, the **pipeline** term can sometimes be
132 when we say **pipeline**. In the DCN driver, we use the term **hardware
133 pipeline** or **pipeline** or just **pipe** as an abstraction to indicate a
135 core treats DCN blocks as individual resources, meaning we can build a pipeline
136 by taking resources for all individual hardware blocks to compose one pipeline.
139 arbitrarily assigned as needed. We have this pipeline concept for trying to
146 this log can help us to see part of this pipeline behavior in real-time::
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/linux-6.12.1/drivers/staging/media/atomisp/
Dnotes.txt5 pipeline. It does not have its own memory, but instead uses main memory.
14 The actual processing pipeline is made by loading one or more programs,
25 So in this case a single binary handles the entire pipeline.
29 on the ISP can do multiple processing steps in a single pipeline
/linux-6.12.1/sound/soc/intel/avs/
Dtopology.c1227 struct avs_tplg_pipeline *pipeline; in avs_tplg_pipeline_create() local
1231 pipeline = devm_kzalloc(comp->card->dev, sizeof(*pipeline), GFP_KERNEL); in avs_tplg_pipeline_create()
1232 if (!pipeline) in avs_tplg_pipeline_create()
1235 pipeline->owner = owner; in avs_tplg_pipeline_create()
1236 INIT_LIST_HEAD(&pipeline->mod_list); in avs_tplg_pipeline_create()
1247 ret = avs_parse_tokens(comp, pipeline, pipeline_parsers, in avs_tplg_pipeline_create()
1263 if (pipeline->num_bindings) in avs_tplg_pipeline_create()
1268 pipeline->bindings = devm_kcalloc(comp->card->dev, pipeline->num_bindings, in avs_tplg_pipeline_create()
1269 sizeof(*pipeline->bindings), GFP_KERNEL); in avs_tplg_pipeline_create()
1270 if (!pipeline->bindings) in avs_tplg_pipeline_create()
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/linux-6.12.1/drivers/staging/media/atomisp/pci/
Dsh_css_param_shading.c265 left_cropping = (binary->info->sp.pipeline.left_cropping == 0) ? in prepare_shading_table()
270 left_padding = (left_padding + binary->info->sp.pipeline.left_cropping) * in prepare_shading_table()
272 binary->info->sp.pipeline.left_cropping; in prepare_shading_table()
276 top_padding = binary->info->sp.pipeline.top_cropping * bds.numerator / in prepare_shading_table()
278 binary->info->sp.pipeline.top_cropping; in prepare_shading_table()
/linux-6.12.1/Documentation/driver-api/media/
Dmc-core.rst24 in a System-on-Chip image processing pipeline), DMA channels or physical
199 A media pipeline is a set of media streams which are interdependent. This
202 due to the software design. Most commonly a media pipeline consists of a single
205 When starting streaming, drivers must notify all entities in the pipeline to
209 The function will mark all the pads which are part of the pipeline as streaming.
212 stored in every pad in the pipeline. Drivers should embed the struct
213 media_pipeline in higher-level pipeline structures and can then access the
214 pipeline through the struct media_pad pipe field.
217 The pipeline pointer must be identical for all nested calls to the function.
244 for any entity which has sink pads in the pipeline. The
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/linux-6.12.1/drivers/staging/media/imx/
DTODO7 pipeline. The controls for each capture device are updated in the
8 link_notify callback when the pipeline is modified. This feature should be
/linux-6.12.1/Documentation/admin-guide/media/
Dqcom_camss.rst38 - 1 / 2 VFE (Video Front End) module(s). Contain a pipeline of image processing
40 interface feeds the input data to the image processing pipeline. The image
41 processing pipeline contains also a scale and crop module at the end. Three
43 pipeline. The VFE also contains the AXI bus interface which writes the output
137 The media controller pipeline graph is as follows (with connected two / three
146 Media pipeline graph 8x16
152 Media pipeline graph 8x96

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